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Re-add netlisting logic inadvertently removed during refactor 

Fixes https://gitlab.com/kicad/code/kicad/-/issues/4692
This commit is contained in:
Jon Evans 2020-06-21 21:43:24 -04:00
parent 202b55f4d2
commit 40e0a4295d
5 changed files with 209 additions and 37 deletions
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142
eeschema/netlist_exporters/netlist_exporter.cpp
View File

@ -111,3 +111,145 @@ SCH_COMPONENT* NETLIST_EXPORTER::findNextComponent( EDA_ITEM* aItem, SCH_SHEET_P
return comp;
}
/// Comparison routine for sorting by pin numbers.
static bool sortPinsByNum( PIN_INFO& aPin1, PIN_INFO& aPin2 )
{
// return "lhs < rhs"
return UTIL::RefDesStringCompare( aPin1.num, aPin2.num ) < 0;
}
void NETLIST_EXPORTER::CreatePinList( SCH_COMPONENT* comp, SCH_SHEET_PATH* aSheetPath )
{
wxString ref( comp->GetRef( aSheetPath ) );
// Power symbols and other components which have the reference starting
// with "#" are not included in netlist (pseudo or virtual components)
if( ref[0] == wxChar( '#' ) )
return;
// if( Component->m_FlagControlMulti == 1 )
// continue; /* yes */
// removed because with multiple instances of one schematic
// (several sheets pointing to 1 screen), this will be erroneously be
// toggled.
if( !comp->GetPartRef() )
return;
m_SortedComponentPinList.clear();
// If component is a "multi parts per package" type
if( comp->GetPartRef()->GetUnitCount() > 1 )
{
// Collect all pins for this reference designator by searching
// the entire design for other parts with the same reference designator.
// This is only done once, it would be too expensive otherwise.
findAllUnitsOfComponent( comp, comp->GetPartRef().get(), aSheetPath );
}
else // entry->GetUnitCount() <= 1 means one part per package
{
for( const auto& pin : comp->GetSchPins( aSheetPath ) )
{
if( auto conn = pin->Connection( *aSheetPath ) )
{
const wxString& netName = conn->Name();
// Skip unconnected pins
CONNECTION_SUBGRAPH* sg =
m_schematic->ConnectionGraph()->FindSubgraphByName( netName, *aSheetPath );
if( !sg || sg->m_no_connect || sg->m_items.size() < 2 )
continue;
m_SortedComponentPinList.emplace_back( pin->GetNumber(), netName );
}
}
}
// Sort pins in m_SortedComponentPinList by pin number
sort( m_SortedComponentPinList.begin(), m_SortedComponentPinList.end(), sortPinsByNum );
// Remove duplicate Pins in m_SortedComponentPinList
eraseDuplicatePins();
// record the usage of this library component entry.
m_LibParts.insert( comp->GetPartRef().get() ); // rejects non-unique pointers
}
void NETLIST_EXPORTER::eraseDuplicatePins()
{
for( unsigned ii = 0; ii < m_SortedComponentPinList.size(); ii++ )
{
if( m_SortedComponentPinList[ii].num.empty() ) /* already deleted */
continue;
/* Search for duplicated pins
* If found, remove duplicates. The priority is to keep connected pins
* and remove unconnected
* - So this allows (for instance when using multi op amps per package
* - to connect only one op amp to power
* Because the pin list is sorted by m_PinNum value, duplicated pins
* are necessary successive in list
*/
int idxref = ii;
for( unsigned jj = ii + 1; jj < m_SortedComponentPinList.size(); jj++ )
{
if( m_SortedComponentPinList[jj].num.empty() ) // Already removed
continue;
// if other pin num, stop search,
// because all pins having the same number are consecutive in list.
if( m_SortedComponentPinList[idxref].num != m_SortedComponentPinList[jj].num )
break;
m_SortedComponentPinList[jj].num.clear();
}
}
}
void NETLIST_EXPORTER::findAllUnitsOfComponent( SCH_COMPONENT* aComponent,
LIB_PART* aEntry, SCH_SHEET_PATH* aSheetPath )
{
wxString ref = aComponent->GetRef( aSheetPath );
wxString ref2;
SCH_SHEET_LIST sheetList = m_schematic->GetSheets();
for( unsigned i = 0; i < sheetList.size(); i++ )
{
for( auto item : sheetList[i].LastScreen()->Items().OfType( SCH_COMPONENT_T ) )
{
SCH_COMPONENT* comp2 = static_cast<SCH_COMPONENT*>( item );
ref2 = comp2->GetRef( &sheetList[i] );
if( ref2.CmpNoCase( ref ) != 0 )
continue;
for( const auto& pin : comp2->GetSchPins( aSheetPath ) )
{
if( auto conn = pin->Connection( *aSheetPath ) )
{
const wxString& netName = conn->Name();
// Skip unconnected pins
CONNECTION_SUBGRAPH* sg = m_schematic->ConnectionGraph()->FindSubgraphByName(
netName, *aSheetPath );
if( !sg || sg->m_no_connect || sg->m_items.size() < 2 )
continue;
m_SortedComponentPinList.emplace_back( pin->GetNumber(), netName );
}
}
}
}
}

55
eeschema/netlist_exporters/netlist_exporter.h
View File

@ -81,6 +81,17 @@ struct LIB_PART_LESS_THAN
}
};
struct PIN_INFO
{
PIN_INFO( const wxString& aPinNumber, const wxString& aNetName ) :
num( aPinNumber ),
netName( aNetName )
{}
wxString num;
wxString netName;
};
/**
* NETLIST_EXPORTER
* is a abstract class used for the netlist exporters that eeschema supports.
@ -88,16 +99,32 @@ struct LIB_PART_LESS_THAN
class NETLIST_EXPORTER
{
protected:
/// Used to temporarily store and filter the list of pins of a schematic component
/// when generating schematic component data in netlist (comp section). No ownership
/// of members.
/// TODO(snh): Descope this object
std::vector<PIN_INFO> m_SortedComponentPinList;
/// Used for "multi parts per package" components,
/// avoids processing a lib component more than once.
UNIQUE_STRINGS m_ReferencesAlreadyFound;
/// unique library parts used. LIB_PART items are sorted by names
/// unique library parts used. LIB_PART items are s
/// orted by names
std::set<LIB_PART*, LIB_PART_LESS_THAN> m_LibParts;
/// The schematic we're generating a netlist for
SCHEMATIC* m_schematic;
/**
* Function findNextComponentAndCreatePinList
* finds a component from the DrawList and builds
* its pin list in m_SortedComponentPinList. This list is sorted by pin num.
* the component is the next actual component after aItem
* (power symbols and virtual components that have their reference starting by '#'are skipped).
*/
void CreatePinList( SCH_COMPONENT* aItem, SCH_SHEET_PATH* aSheetPath );
/**
* Checks if the given component should be processed for netlisting.
* Prevents processing multi-unit components more than once, etc.
@ -107,6 +134,32 @@ protected:
*/
SCH_COMPONENT* findNextComponent( EDA_ITEM* aItem, SCH_SHEET_PATH* aSheetPath );
/**
* Function eraseDuplicatePins
* erase duplicate Pins from m_SortedComponentPinList (i.e. set pointer in this list to NULL).
* (This is a list of pins found in the whole schematic, for a single
* component.) These duplicate pins were put in list because some pins (powers... )
* are found more than one time when we have a multiple parts per package
* component. For instance, a 74ls00 has 4 parts, and therefore the VCC pin
* and GND pin appears 4 times in the list.
* Note: this list *MUST* be sorted by pin number (.m_PinNum member value)
* Also set the m_Flag member of "removed" NETLIST_OBJECT pin item to 1
*/
void eraseDuplicatePins();
/**
* Function findAllUnitsOfComponent
* is used for "multiple parts per package" components.
* <p>
* Search the entire design for all units of \a aComponent based on
* matching reference designator, and for each unit, add all its pins
* to the temporary sorted pin list, m_SortedComponentPinList.
*/
void findAllUnitsOfComponent( SCH_COMPONENT* aComponent,
LIB_PART* aEntry,
SCH_SHEET_PATH* aSheetPath );
public:
/**

2
eeschema/netlist_exporters/netlist_exporter_cadstar.cpp
View File

@ -163,6 +163,8 @@ bool NETLIST_EXPORTER_CADSTAR::writeListOfNets( FILE* f )
} ),
sorted_items.end() );
print_ter = 0;
for( const auto& pair : sorted_items )
{
SCH_PIN* pin = pair.first;

24
eeschema/netlist_exporters/netlist_exporter_orcadpcb2.cpp
View File

@ -78,6 +78,8 @@ bool NETLIST_EXPORTER_ORCADPCB2::WriteNetlist( const wxString& aOutFileName,
if( !comp )
continue;
CreatePinList( comp, &sheet );
if( comp->GetPartRef() && comp->GetPartRef()->GetFootprints().GetCount() != 0 )
cmpList.push_back( SCH_REFERENCE( comp, comp->GetPartRef().get(), sheet ) );
@ -106,28 +108,12 @@ bool NETLIST_EXPORTER_ORCADPCB2::WriteNetlist( const wxString& aOutFileName,
ret |= fprintf( f, "\n" );
// Write pin list:
std::vector<SCH_PIN*> pins;
for( const auto& pin : comp->GetSchPins( &sheet ) )
pins.emplace_back( pin );
std::sort( pins.begin(), pins.end(),
[]( const SCH_PIN* a, const SCH_PIN* b )
{
return UTIL::RefDesStringCompare( a->GetNumber(), b->GetNumber() ) < 0;
} );
for( const auto* pin : pins )
for( const PIN_INFO& pin : m_SortedComponentPinList )
{
if( auto conn = pin->Connection( sheet ) )
netName = conn->Name();
else
netName = wxT( "?" );
netName = pin.netName;
netName.Replace( wxT( " " ), wxT( "_" ) );
ret |= fprintf( f, " ( %4.4s %s )\n", TO_UTF8( pin->GetNumber() ),
TO_UTF8( netName ) );
ret |= fprintf( f, " ( %4.4s %s )\n", TO_UTF8( pin.num ), TO_UTF8( netName ) );
}
ret |= fprintf( f, " )\n" );

23
eeschema/netlist_exporters/netlist_exporter_pspice.cpp
View File

@ -291,6 +291,7 @@ bool NETLIST_EXPORTER_PSPICE::ProcessNetlist( unsigned aCtl )
if( !comp )
continue;
CreatePinList( comp, &sheet );
SPICE_ITEM spiceItem;
spiceItem.m_parent = comp;
@ -321,26 +322,14 @@ bool NETLIST_EXPORTER_PSPICE::ProcessNetlist( unsigned aCtl )
wxArrayString pinNames;
// Store pin information
for( const auto& pin : comp->GetSchPins( &sheet ) )
for( const PIN_INFO& pin : m_SortedComponentPinList )
{
if( auto conn = pin->Connection( sheet ) )
{
const wxString& netName = conn->Name();
// Skip unconnected pins
CONNECTION_SUBGRAPH* sg =
m_schematic->ConnectionGraph()->FindSubgraphByName( netName, sheet );
if( !sg || sg->m_no_connect || sg->m_items.size() < 2 )
continue;
// Create net mapping
spiceItem.m_pins.push_back( netName );
pinNames.Add( pin->GetName() );
spiceItem.m_pins.push_back( pin.netName );
pinNames.Add( pin.num );
if( m_netMap.count( netName ) == 0 )
m_netMap[netName] = netIdx++;
}
if( m_netMap.count( pin.netName ) == 0 )
m_netMap[pin.netName] = netIdx++;
}
// Check if an alternative pin sequence is available: