Collapse silk constraints down to one.
Also updates the rule syntax help and code-completion with a bunch of diff-pair and other stuff that hadn't been updated yet.
This commit is contained in:
parent
bcebb19665
commit
42eecdfd3a
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@ -29,8 +29,7 @@ zone
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edge_clearance
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edge_clearance
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hole_clearance
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hole_clearance
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courtyard_clearance
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courtyard_clearance
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silk_to_mask
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silk_clearance
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silk_to_silk
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skew
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skew
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diff_pair_gap
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diff_pair_gap
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diff_pair_uncoupled
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diff_pair_uncoupled
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@ -251,7 +251,7 @@ set( PCBNEW_DRC_SRCS
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drc/drc_test_provider_track_width.cpp
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drc/drc_test_provider_track_width.cpp
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drc/drc_test_provider_via_diameter.cpp
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drc/drc_test_provider_via_diameter.cpp
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drc/drc_test_provider_silk_to_mask.cpp
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drc/drc_test_provider_silk_to_mask.cpp
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drc/drc_test_provider_silk_to_silk.cpp
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drc/drc_test_provider_silk_clearance.cpp
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drc/drc_test_provider_matched_length.cpp
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drc/drc_test_provider_matched_length.cpp
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drc/drc_test_provider_diff_pair_coupling.cpp
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drc/drc_test_provider_diff_pair_coupling.cpp
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)
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)
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@ -236,8 +236,8 @@ void PANEL_SETUP_RULES::onScintillaCharAdded( wxStyledTextEvent &aEvent )
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"length "
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"length "
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"hole "
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"hole "
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"hole_clearance "
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"hole_clearance "
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"silk_to_mask "
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"silk_clearance "
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"silk_to_silk skew "
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"skew "
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"track_width "
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"track_width "
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"via_count ";
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"via_count ";
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}
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}
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@ -18,9 +18,18 @@
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* annular_width
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* annular_width
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* clearance
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* clearance
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* courtyard_clearance
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* diff_pair_gap
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* diff_pair_uncoupled
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* disallow
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* disallow
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* edge_clearance
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* length
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* hole
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* hole
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* hole_clearance
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* silk_clearance
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* skew
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* track_width
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* track_width
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* via_count
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### Item Types
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### Item Types
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@ -129,14 +129,10 @@ void DRC_ENGINE::loadImplicitRules()
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holeClearanceConstraint.Value().SetMin( 0 );
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holeClearanceConstraint.Value().SetMin( 0 );
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rule->AddConstraint( courtyardClearanceConstraint );
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rule->AddConstraint( courtyardClearanceConstraint );
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DRC_CONSTRAINT silkToPadClearanceConstraint( DRC_CONSTRAINT_TYPE_SILK_TO_MASK );
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DRC_CONSTRAINT silkToPadClearanceConstraint( DRC_CONSTRAINT_TYPE_SILK_CLEARANCE );
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silkToPadClearanceConstraint.Value().SetMin( 0 );
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silkToPadClearanceConstraint.Value().SetMin( 0 );
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rule->AddConstraint( silkToPadClearanceConstraint );
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rule->AddConstraint( silkToPadClearanceConstraint );
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DRC_CONSTRAINT silkToSilkClearanceConstraint( DRC_CONSTRAINT_TYPE_SILK_TO_SILK );
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silkToSilkClearanceConstraint.Value().SetMin( 0 );
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rule->AddConstraint( silkToSilkClearanceConstraint );
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DRC_CONSTRAINT diffPairGapConstraint( DRC_CONSTRAINT_TYPE_DIFF_PAIR_GAP );
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DRC_CONSTRAINT diffPairGapConstraint( DRC_CONSTRAINT_TYPE_DIFF_PAIR_GAP );
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diffPairGapConstraint.Value().SetMin( bds.GetDefault()->GetClearance() );
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diffPairGapConstraint.Value().SetMin( bds.GetDefault()->GetClearance() );
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diffPairGapConstraint.Value().SetOpt( bds.GetDefault()->GetClearance() );
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diffPairGapConstraint.Value().SetOpt( bds.GetDefault()->GetClearance() );
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@ -363,8 +359,7 @@ static wxString formatConstraint( const DRC_CONSTRAINT& constraint )
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{ DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE, "edge_clearance", formatMinMax },
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{ DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE, "edge_clearance", formatMinMax },
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{ DRC_CONSTRAINT_TYPE_HOLE_SIZE, "hole_size", formatMinMax },
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{ DRC_CONSTRAINT_TYPE_HOLE_SIZE, "hole_size", formatMinMax },
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{ DRC_CONSTRAINT_TYPE_COURTYARD_CLEARANCE, "courtyard_clearance", formatMinMax },
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{ DRC_CONSTRAINT_TYPE_COURTYARD_CLEARANCE, "courtyard_clearance", formatMinMax },
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{ DRC_CONSTRAINT_TYPE_SILK_TO_MASK, "silk_to_mask", formatMinMax },
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{ DRC_CONSTRAINT_TYPE_SILK_CLEARANCE, "silk_clearance", formatMinMax },
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{ DRC_CONSTRAINT_TYPE_SILK_TO_SILK, "silk_to_silk", formatMinMax },
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{ DRC_CONSTRAINT_TYPE_TRACK_WIDTH, "track_width", formatMinMax },
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{ DRC_CONSTRAINT_TYPE_TRACK_WIDTH, "track_width", formatMinMax },
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{ DRC_CONSTRAINT_TYPE_ANNULAR_WIDTH, "annular_width", formatMinMax },
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{ DRC_CONSTRAINT_TYPE_ANNULAR_WIDTH, "annular_width", formatMinMax },
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{ DRC_CONSTRAINT_TYPE_DISALLOW, "disallow", nullptr },
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{ DRC_CONSTRAINT_TYPE_DISALLOW, "disallow", nullptr },
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@ -250,21 +250,19 @@ public:
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int count = 0;
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int count = 0;
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auto visit = [&] ( ITEM_WITH_SHAPE* aItem ) -> bool
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auto visit =
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[&] ( ITEM_WITH_SHAPE* aItem ) -> bool
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{
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if( !aFilter || aFilter( aItem->parent ) )
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{
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{
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int actual;
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int actual;
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// keep searching
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if( aRefShape->Collide( aItem->shape, aClearance, &actual ) )
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if( aFilter && ! aFilter( aItem->parent ) )
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return true;
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bool colliding = aRefShape->Collide( aItem->shape, aClearance, &actual );
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if( colliding )
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{
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{
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count++;
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count++;
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return false;
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return false;
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}
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}
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}
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return true;
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return true;
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};
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};
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@ -278,8 +276,7 @@ public:
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PCB_LAYER_ID aTargetLayer,
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PCB_LAYER_ID aTargetLayer,
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std::function<bool( BOARD_ITEM*)> aFilter = nullptr,
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std::function<bool( BOARD_ITEM*)> aFilter = nullptr,
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std::function<bool( BOARD_ITEM*, int)> aVisitor = nullptr,
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std::function<bool( BOARD_ITEM*, int)> aVisitor = nullptr,
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int aClearance = 0
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int aClearance = 0 )
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)
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{
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{
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// keep track of BOARD_ITEMs that have been already found to collide (some items
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// keep track of BOARD_ITEMs that have been already found to collide (some items
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// might be build of COMPOUND/triangulated shapes and a single subshape collision
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// might be build of COMPOUND/triangulated shapes and a single subshape collision
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int count = 0;
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int count = 0;
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auto visit = [&] ( ITEM_WITH_SHAPE* aItem ) -> bool
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auto visit =
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[&]( ITEM_WITH_SHAPE* aItem ) -> bool
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{
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{
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if( collidingCompounds.find( aItem->parent ) != collidingCompounds.end() )
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if( collidingCompounds.find( aItem->parent ) != collidingCompounds.end() )
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return true;
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return true;
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if( aFilter && !aFilter( aItem->parent ) )
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if( !aFilter || aFilter( aItem->parent ) )
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return true;
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{
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int actual;
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int actual;
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bool colliding = refShape->Collide( aItem->shape, aClearance, &actual );
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if( refShape->Collide( aItem->shape, aClearance, &actual ) )
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if( colliding )
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{
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{
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collidingCompounds.insert( aItem->parent );
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collidingCompounds.insert( aItem->parent );
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count++;
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count++;
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if( aVisitor )
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if( aVisitor )
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{
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return aVisitor( aItem->parent, actual );
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return aVisitor( aItem->parent, actual );
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}
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}
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else
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{
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return true;
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}
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}
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}
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return true;
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return true;
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};
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};
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@ -389,8 +379,7 @@ public:
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#if 0
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#if 0
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std::vector<std::pair<int, BOARD_ITEM*>> GetNearest( const wxPoint &aPoint,
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std::vector<std::pair<int, BOARD_ITEM*>> GetNearest( const wxPoint &aPoint,
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PCB_LAYER_ID aLayer,
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PCB_LAYER_ID aLayer, int aLimit )
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int aLimit )
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{
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{
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const int point[2] = { aPoint.x, aPoint.y };
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const int point[2] = { aPoint.x, aPoint.y };
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@ -46,8 +46,7 @@ enum DRC_CONSTRAINT_TYPE_T
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DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE,
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DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE,
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DRC_CONSTRAINT_TYPE_HOLE_SIZE,
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DRC_CONSTRAINT_TYPE_HOLE_SIZE,
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DRC_CONSTRAINT_TYPE_COURTYARD_CLEARANCE,
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DRC_CONSTRAINT_TYPE_COURTYARD_CLEARANCE,
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DRC_CONSTRAINT_TYPE_SILK_TO_MASK,
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DRC_CONSTRAINT_TYPE_SILK_CLEARANCE,
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DRC_CONSTRAINT_TYPE_SILK_TO_SILK,
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DRC_CONSTRAINT_TYPE_TRACK_WIDTH,
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DRC_CONSTRAINT_TYPE_TRACK_WIDTH,
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DRC_CONSTRAINT_TYPE_ANNULAR_WIDTH,
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DRC_CONSTRAINT_TYPE_ANNULAR_WIDTH,
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DRC_CONSTRAINT_TYPE_DISALLOW,
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DRC_CONSTRAINT_TYPE_DISALLOW,
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@ -276,8 +276,7 @@ void DRC_RULES_PARSER::parseConstraint( DRC_RULE* aRule )
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case T_edge_clearance: constraint.m_Type = DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE; break;
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case T_edge_clearance: constraint.m_Type = DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE; break;
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case T_hole: constraint.m_Type = DRC_CONSTRAINT_TYPE_HOLE_SIZE; break;
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case T_hole: constraint.m_Type = DRC_CONSTRAINT_TYPE_HOLE_SIZE; break;
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case T_courtyard_clearance: constraint.m_Type = DRC_CONSTRAINT_TYPE_COURTYARD_CLEARANCE; break;
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case T_courtyard_clearance: constraint.m_Type = DRC_CONSTRAINT_TYPE_COURTYARD_CLEARANCE; break;
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case T_silk_to_mask: constraint.m_Type = DRC_CONSTRAINT_TYPE_SILK_TO_MASK; break;
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case T_silk_clearance: constraint.m_Type = DRC_CONSTRAINT_TYPE_SILK_CLEARANCE; break;
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case T_silk_to_silk: constraint.m_Type = DRC_CONSTRAINT_TYPE_SILK_TO_SILK; break;
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case T_track_width: constraint.m_Type = DRC_CONSTRAINT_TYPE_TRACK_WIDTH; break;
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case T_track_width: constraint.m_Type = DRC_CONSTRAINT_TYPE_TRACK_WIDTH; break;
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case T_annular_width: constraint.m_Type = DRC_CONSTRAINT_TYPE_ANNULAR_WIDTH; break;
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case T_annular_width: constraint.m_Type = DRC_CONSTRAINT_TYPE_ANNULAR_WIDTH; break;
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case T_disallow: constraint.m_Type = DRC_CONSTRAINT_TYPE_DISALLOW; break;
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case T_disallow: constraint.m_Type = DRC_CONSTRAINT_TYPE_DISALLOW; break;
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@ -190,7 +190,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
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const std::shared_ptr<SHAPE>& shape = boardItem->GetEffectiveShape();
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const std::shared_ptr<SHAPE>& shape = boardItem->GetEffectiveShape();
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auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_SILK_TO_MASK,
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auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_SILK_CLEARANCE,
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outlineItem, boardItem );
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outlineItem, boardItem );
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int minClearance = constraint.GetValue().Min();
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int minClearance = constraint.GetValue().Min();
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@ -235,7 +235,7 @@ int DRC_TEST_PROVIDER_EDGE_CLEARANCE::GetNumPhases() const
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std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_EDGE_CLEARANCE::GetConstraintTypes() const
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std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_EDGE_CLEARANCE::GetConstraintTypes() const
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{
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{
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return { DRC_CONSTRAINT_TYPE_T::DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE };
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return { DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE, DRC_CONSTRAINT_TYPE_SILK_CLEARANCE };
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}
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}
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@ -42,14 +42,14 @@
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*/
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*/
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class DRC_TEST_PROVIDER_SILK_TO_SILK : public DRC_TEST_PROVIDER
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class DRC_TEST_PROVIDER_SILK_CLEARANCE : public DRC_TEST_PROVIDER
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{
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{
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public:
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public:
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DRC_TEST_PROVIDER_SILK_TO_SILK ()
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DRC_TEST_PROVIDER_SILK_CLEARANCE ()
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{
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{
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}
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}
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virtual ~DRC_TEST_PROVIDER_SILK_TO_SILK()
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virtual ~DRC_TEST_PROVIDER_SILK_CLEARANCE()
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{
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{
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}
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}
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virtual const wxString GetName() const override
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virtual const wxString GetName() const override
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{
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{
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return "silk_to_silk";
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return "silk_clearance";
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};
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};
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virtual const wxString GetDescription() const override
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virtual const wxString GetDescription() const override
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@ -79,14 +79,14 @@ private:
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};
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};
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bool DRC_TEST_PROVIDER_SILK_TO_SILK::Run()
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bool DRC_TEST_PROVIDER_SILK_CLEARANCE::Run()
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{
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{
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m_board = m_drcEngine->GetBoard();
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m_board = m_drcEngine->GetBoard();
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DRC_CONSTRAINT worstClearanceConstraint;
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DRC_CONSTRAINT worstClearanceConstraint;
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m_largestClearance = 0;
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m_largestClearance = 0;
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if( m_drcEngine->QueryWorstConstraint( DRC_CONSTRAINT_TYPE_SILK_TO_SILK,
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if( m_drcEngine->QueryWorstConstraint( DRC_CONSTRAINT_TYPE_SILK_CLEARANCE,
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worstClearanceConstraint, DRCCQ_LARGEST_MINIMUM ) )
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worstClearanceConstraint, DRCCQ_LARGEST_MINIMUM ) )
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{
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{
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m_largestClearance = worstClearanceConstraint.m_Value.Min();
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m_largestClearance = worstClearanceConstraint.m_Value.Min();
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@ -97,15 +97,22 @@ bool DRC_TEST_PROVIDER_SILK_TO_SILK::Run()
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if( !reportPhase( _( "Checking silkscreen for overlapping items..." ) ) )
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if( !reportPhase( _( "Checking silkscreen for overlapping items..." ) ) )
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return false;
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return false;
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DRC_RTREE silkTree;
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DRC_RTREE silkTree, targetTree;
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auto addToTree =
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auto addToSilkTree =
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[&silkTree]( BOARD_ITEM *item ) -> bool
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[&silkTree]( BOARD_ITEM *item ) -> bool
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{
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{
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silkTree.insert( item );
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silkTree.insert( item );
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return true;
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return true;
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};
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};
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auto addToTargetTree =
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[&targetTree]( BOARD_ITEM *item ) -> bool
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{
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targetTree.insert( item );
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return true;
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};
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auto checkClearance =
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auto checkClearance =
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[&]( const DRC_RTREE::LAYER_PAIR& aLayers, DRC_RTREE::ITEM_WITH_SHAPE* aRefItem,
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[&]( const DRC_RTREE::LAYER_PAIR& aLayers, DRC_RTREE::ITEM_WITH_SHAPE* aRefItem,
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DRC_RTREE::ITEM_WITH_SHAPE* aTestItem, bool* aCollisionDetected ) -> bool
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DRC_RTREE::ITEM_WITH_SHAPE* aTestItem, bool* aCollisionDetected ) -> bool
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@ -113,20 +120,31 @@ bool DRC_TEST_PROVIDER_SILK_TO_SILK::Run()
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_SILK_CLEARANCE ) )
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_SILK_CLEARANCE ) )
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return false;
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return false;
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auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_SILK_TO_SILK,
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auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_SILK_CLEARANCE,
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aRefItem->parent,
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aRefItem->parent,
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aTestItem->parent );
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aTestItem->parent,
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aLayers.second );
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int minClearance = constraint.GetValue().Min();
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int minClearance = constraint.GetValue().Min();
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int actual;
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int actual;
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VECTOR2I pos;
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VECTOR2I pos;
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accountCheck( constraint );
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accountCheck( constraint );
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// only check for silkscreen collisions belonging to different footprints or
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if( minClearance == 0 )
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// overlapping texts
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{
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// MinClearance == 0 means the author didn't specify anything and we want to
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// use heuristics for a silk : silk collision.
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//
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// MinClearance > 0 means we're in an author-specified condition that the
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// rule matched, and we don't want any heuristics.
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KICAD_T typeRef = aRefItem->parent->Type();
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// We know that aLayers.first is a silk layer, so we just need to check that
|
||||||
KICAD_T typeTest = aTestItem->parent->Type();
|
// aLayers.second matches.
|
||||||
|
if( aLayers.second != aLayers.first )
|
||||||
|
return true;
|
||||||
|
|
||||||
|
KICAD_T refType = aRefItem->parent->Type();
|
||||||
|
KICAD_T testType = aTestItem->parent->Type();
|
||||||
|
|
||||||
MODULE *parentModRef = nullptr;
|
MODULE *parentModRef = nullptr;
|
||||||
MODULE *parentModTest = nullptr;
|
MODULE *parentModTest = nullptr;
|
||||||
|
@ -137,30 +155,25 @@ bool DRC_TEST_PROVIDER_SILK_TO_SILK::Run()
|
||||||
if ( isInvisibleText( aTestItem->parent ) )
|
if ( isInvisibleText( aTestItem->parent ) )
|
||||||
return true;
|
return true;
|
||||||
|
|
||||||
if( typeRef == PCB_FP_SHAPE_T || typeRef == PCB_FP_TEXT_T )
|
if( refType == PCB_FP_SHAPE_T || refType == PCB_FP_TEXT_T )
|
||||||
{
|
|
||||||
parentModRef = static_cast<MODULE*> ( aRefItem->parent->GetParent() );
|
parentModRef = static_cast<MODULE*> ( aRefItem->parent->GetParent() );
|
||||||
}
|
|
||||||
|
|
||||||
if( typeTest == PCB_FP_SHAPE_T || typeTest == PCB_FP_TEXT_T )
|
if( testType == PCB_FP_SHAPE_T || testType == PCB_FP_TEXT_T )
|
||||||
{
|
|
||||||
parentModTest = static_cast<MODULE*> ( aTestItem->parent->GetParent() );
|
parentModTest = static_cast<MODULE*> ( aTestItem->parent->GetParent() );
|
||||||
}
|
|
||||||
|
|
||||||
// silkscreen drawings within the same module (or globally on the board)
|
// Silkscreen drawings within the same module (or globally on the board)
|
||||||
// don't report clearance errors. Everything else does.
|
// don't report clearance errors. Everything else does.
|
||||||
|
|
||||||
if( parentModRef && parentModRef == parentModTest )
|
if( parentModRef && parentModRef == parentModTest )
|
||||||
{
|
{
|
||||||
if( typeRef == PCB_FP_SHAPE_T && typeTest == PCB_FP_SHAPE_T )
|
if( refType == PCB_FP_SHAPE_T && testType == PCB_FP_SHAPE_T )
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
else if( !parentModRef && !parentModTest )
|
||||||
if( !parentModRef && !parentModTest )
|
|
||||||
{
|
{
|
||||||
if( typeRef == PCB_SHAPE_T && typeTest == PCB_SHAPE_T )
|
if( refType == PCB_SHAPE_T && testType == PCB_SHAPE_T )
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
|
||||||
if( !aRefItem->shape->Collide( aTestItem->shape, minClearance, &actual, &pos ) )
|
if( !aRefItem->shape->Collide( aTestItem->shape, minClearance, &actual, &pos ) )
|
||||||
return true;
|
return true;
|
||||||
|
@ -187,17 +200,32 @@ bool DRC_TEST_PROVIDER_SILK_TO_SILK::Run()
|
||||||
};
|
};
|
||||||
|
|
||||||
int numSilk = forEachGeometryItem( { PCB_SHAPE_T, PCB_FP_SHAPE_T, PCB_TEXT_T, PCB_FP_TEXT_T },
|
int numSilk = forEachGeometryItem( { PCB_SHAPE_T, PCB_FP_SHAPE_T, PCB_TEXT_T, PCB_FP_TEXT_T },
|
||||||
LSET( 2, F_SilkS, B_SilkS ), addToTree );
|
LSET( 2, F_SilkS, B_SilkS ), addToSilkTree );
|
||||||
|
forEachGeometryItem( {}, LSET::FrontMask() | LSET::BackMask(), addToTargetTree );
|
||||||
|
|
||||||
reportAux( _("Testing %d silkscreen features."), numSilk );
|
reportAux( _("Testing %d silkscreen features."), numSilk );
|
||||||
|
|
||||||
const std::vector<DRC_RTREE::LAYER_PAIR> layerPairs =
|
const std::vector<DRC_RTREE::LAYER_PAIR> layerPairs =
|
||||||
{
|
{
|
||||||
DRC_RTREE::LAYER_PAIR( F_SilkS, F_SilkS ),
|
DRC_RTREE::LAYER_PAIR( F_SilkS, F_SilkS ),
|
||||||
DRC_RTREE::LAYER_PAIR( B_SilkS, B_SilkS )
|
DRC_RTREE::LAYER_PAIR( F_SilkS, F_Mask ),
|
||||||
|
DRC_RTREE::LAYER_PAIR( F_SilkS, F_Adhes ),
|
||||||
|
DRC_RTREE::LAYER_PAIR( F_SilkS, F_Paste ),
|
||||||
|
DRC_RTREE::LAYER_PAIR( F_SilkS, F_CrtYd ),
|
||||||
|
DRC_RTREE::LAYER_PAIR( F_SilkS, F_Fab ),
|
||||||
|
DRC_RTREE::LAYER_PAIR( F_SilkS, F_Cu ),
|
||||||
|
DRC_RTREE::LAYER_PAIR( F_SilkS, Edge_Cuts ),
|
||||||
|
DRC_RTREE::LAYER_PAIR( B_SilkS, B_SilkS ),
|
||||||
|
DRC_RTREE::LAYER_PAIR( B_SilkS, B_Mask ),
|
||||||
|
DRC_RTREE::LAYER_PAIR( B_SilkS, B_Adhes ),
|
||||||
|
DRC_RTREE::LAYER_PAIR( B_SilkS, B_Paste ),
|
||||||
|
DRC_RTREE::LAYER_PAIR( B_SilkS, B_CrtYd ),
|
||||||
|
DRC_RTREE::LAYER_PAIR( B_SilkS, B_Fab ),
|
||||||
|
DRC_RTREE::LAYER_PAIR( B_SilkS, B_Cu ),
|
||||||
|
DRC_RTREE::LAYER_PAIR( B_SilkS, Edge_Cuts ),
|
||||||
};
|
};
|
||||||
|
|
||||||
silkTree.QueryCollidingPairs( &silkTree, layerPairs, checkClearance, m_largestClearance );
|
silkTree.QueryCollidingPairs( &targetTree, layerPairs, checkClearance, m_largestClearance );
|
||||||
|
|
||||||
reportRuleStatistics();
|
reportRuleStatistics();
|
||||||
|
|
||||||
|
@ -205,13 +233,13 @@ bool DRC_TEST_PROVIDER_SILK_TO_SILK::Run()
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_SILK_TO_SILK::GetConstraintTypes() const
|
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_SILK_CLEARANCE::GetConstraintTypes() const
|
||||||
{
|
{
|
||||||
return { DRC_CONSTRAINT_TYPE_SILK_TO_SILK };
|
return { DRC_CONSTRAINT_TYPE_SILK_CLEARANCE };
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
namespace detail
|
namespace detail
|
||||||
{
|
{
|
||||||
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_SILK_TO_SILK> dummy;
|
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_SILK_CLEARANCE> dummy;
|
||||||
}
|
}
|
|
@ -87,7 +87,7 @@ bool DRC_TEST_PROVIDER_SILK_TO_MASK::Run()
|
||||||
DRC_CONSTRAINT worstClearanceConstraint;
|
DRC_CONSTRAINT worstClearanceConstraint;
|
||||||
m_largestClearance = 0;
|
m_largestClearance = 0;
|
||||||
|
|
||||||
if( m_drcEngine->QueryWorstConstraint( DRC_CONSTRAINT_TYPE_SILK_TO_MASK,
|
if( m_drcEngine->QueryWorstConstraint( DRC_CONSTRAINT_TYPE_SILK_CLEARANCE,
|
||||||
worstClearanceConstraint, DRCCQ_LARGEST_MINIMUM ) )
|
worstClearanceConstraint, DRCCQ_LARGEST_MINIMUM ) )
|
||||||
{
|
{
|
||||||
m_largestClearance = worstClearanceConstraint.m_Value.Min();
|
m_largestClearance = worstClearanceConstraint.m_Value.Min();
|
||||||
|
@ -121,7 +121,7 @@ bool DRC_TEST_PROVIDER_SILK_TO_MASK::Run()
|
||||||
if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_MASK_CLEARANCE ) )
|
if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_MASK_CLEARANCE ) )
|
||||||
return false;
|
return false;
|
||||||
|
|
||||||
auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_SILK_TO_MASK,
|
auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_SILK_CLEARANCE,
|
||||||
aRefItem->parent,
|
aRefItem->parent,
|
||||||
aTestItem->parent );
|
aTestItem->parent );
|
||||||
|
|
||||||
|
@ -192,7 +192,7 @@ bool DRC_TEST_PROVIDER_SILK_TO_MASK::Run()
|
||||||
|
|
||||||
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_SILK_TO_MASK::GetConstraintTypes() const
|
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_SILK_TO_MASK::GetConstraintTypes() const
|
||||||
{
|
{
|
||||||
return { DRC_CONSTRAINT_TYPE_SILK_TO_MASK };
|
return { DRC_CONSTRAINT_TYPE_SILK_CLEARANCE };
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -53,7 +53,7 @@ add_executable( drc_proto
|
||||||
../../pcbnew/drc/drc_test_provider_lvs.cpp
|
../../pcbnew/drc/drc_test_provider_lvs.cpp
|
||||||
../../pcbnew/drc/drc_test_provider_misc.cpp
|
../../pcbnew/drc/drc_test_provider_misc.cpp
|
||||||
../../pcbnew/drc/drc_test_provider_silk_to_mask.cpp
|
../../pcbnew/drc/drc_test_provider_silk_to_mask.cpp
|
||||||
../../pcbnew/drc/drc_test_provider_silk_to_silk.cpp
|
../../pcbnew/drc/drc_test_provider_silk_clearance.cpp
|
||||||
../../pcbnew/drc/drc_test_provider_matched_length.cpp
|
../../pcbnew/drc/drc_test_provider_matched_length.cpp
|
||||||
../../pcbnew/drc/drc_test_provider_diff_pair_coupling.cpp
|
../../pcbnew/drc/drc_test_provider_diff_pair_coupling.cpp
|
||||||
../../pcbnew/drc/drc_engine.cpp
|
../../pcbnew/drc/drc_engine.cpp
|
||||||
|
|
Loading…
Reference in New Issue