Remove ddr3_length_match.py
The script is designed to be used with a particular board that does not exist in the repository.
This commit is contained in:
Graham Keeth
jean-pierre charras
parent
d59053b775
commit
4bf79f2b90
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@ -1,4 +1,4 @@
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#!/usr/bin/env python2.7
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#!/usr/bin/env python
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import os.path
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from pcbnew import *
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@ -40,7 +40,7 @@ pad_s1 = smdRectPad(module,size_150_200mm,wxPointMM((pads-1)*0.5+1.6,1.3),"0")
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module.Add(pad_s0)
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module.Add(pad_s1)
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e = EDGE_MODULE(module)
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e = FP_SHAPE(module)
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e.SetStart0(wxPointMM(-1,0))
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e.SetEnd0(wxPointMM(0,0))
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e.SetWidth(FromMM(0.2))
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@ -1,308 +0,0 @@
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#!/usr/bin/env python2
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# Author: Dick Hollenbeck
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# Report any length problems pertaining to a SDRAM DDR3 T topology using
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# 4 memory chips: a T into 2 Ts routing strategy from the CPU.
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# Designed to be run from the command line in a process separate from pcbnew.
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# It can monitor writes to disk which will trigger updates to its output, or
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# it can be run with --once option.
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from __future__ import print_function
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import pcbnew
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import os.path
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import sys
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import time
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CPU_REF = 'U7' # CPU reference designator
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# four SDRAM memory chips:
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DDR_LF = 'U15' # left front DRAM
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DDR_RF = 'U17' # right front DRAM
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DDR_LB = 'U16' # left back DRAM
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DDR_RB = 'U18' # right back DRAM
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# Length of SDRAM clock, it sets the maximum or equal needed for other traces
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CLOCK_LEN = pcbnew.FromMils( 2.25 * 1000 )
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def addr_line_netname(line_no):
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"""From an address line number, return the netname"""
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netname = '/DDR3/DRAM_A' + str(line_no)
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return netname
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# Establish GOALS which are LENs, TOLERANCEs and NETs for each group of nets.
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# Net Group: ADDR_AND_CMD
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ADDR_AND_CMD_LEN = pcbnew.FromMils( 2.22 * 1000 )
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ADDR_AND_CMD_TOLERANCE = pcbnew.FromMils( 25 ) / 2
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ADDR_AND_CMD_NETS = [addr_line_netname(a) for a in range(0,16)]
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ADDR_AND_CMD_NETS += [
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'/DDR3/DRAM_SDBA0',
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'/DDR3/DRAM_SDBA1',
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'/DDR3/DRAM_SDBA2',
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'/DDR3/DRAM_RAS_B',
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'/DDR3/DRAM_CAS_B',
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'/DDR3/DRAM_WE_B'
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]
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# Net Group: CONTROL
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CONTROL_LEN = pcbnew.FromMils( 2.10 * 1000 )
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CONTROL_TOLERANCE = pcbnew.FromMils( 50 ) / 2
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CONTROL_NETS = [
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'/DDR3/DRAM_SDODT0',
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#'/DDR3/DRAM_SDODT1',
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'/DDR3/DRAM_CS0_B',
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#'/DDR3/DRAM_CS1_B',
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'/DDR3/DRAM_SDCKE0',
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#'/DDR3/DRAM_SDCKE1',
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]
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BRIGHTGREEN = '\033[92;1m'
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GREEN = '\033[92m'
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BRIGHTRED = '\033[91;1m'
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RED = '\033[91m'
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ENDC = '\033[0m'
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pcb = None
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nets = None
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dbg_conn = False # when true prints out reason for track discontinuity
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def print_color(color, s):
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print(color + s + ENDC)
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def addr_line_netname(line_no):
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netname = '/DDR3/DRAM_A' + str(line_no)
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return netname
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def pad_name(pad):
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return str( pad.GetParent().Reference().GetShownText() ) + '/' + pad.GetPadName()
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def pad_pos(pad):
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return str(pad.GetPosition())
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def pads_in_net(netname):
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byname = {}
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pads = nets[netname].Pads()
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for pad in pads:
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byname[pad_name(pad)] = pad
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return byname
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def track_ends(track):
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"""return a string showing both ends of a track"""
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return str(track.GetStart()) + ' ' + str(track.GetEnd())
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def print_tracks(net_name,tracks):
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print('net:', net_name)
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for track in tracks:
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print(' track:', track_ends(track))
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def sum_track_lengths(point1,point2,netcode):
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tracks = pcb.TracksInNetBetweenPoints(point1, point2, netcode)
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sum = 0
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for t in tracks:
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sum += t.GetLength()
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return sum
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def tracks_in_net(netname):
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nc = pcb.GetNetcodeFromNetname(netname)
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tracks_and_vias = pcb.TracksInNet(nc)
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# remove vias while making new non-owning list
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tracks = [t for t in tracks_and_vias if not t.Type() == pcbnew.PCB_VIA_T]
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return tracks
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def print_pad(pad):
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print( " pad name:'%s' pos:%s" % ( pad_name(pad), pad_pos(pad) ) )
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def print_pads(prompt,pads):
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print(prompt)
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for pad in pads:
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print_pad(pad)
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def is_connected(start_pad, end_pad):
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"""
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Return True if the two pads are copper connected only with vias and tracks
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directly and with no intervening pads, else False.
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"""
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netcode = start_pad.GetNet().GetNet()
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try:
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tracks = pcb.TracksInNetBetweenPoints(start_pad.GetPosition(), end_pad.GetPosition(), netcode)
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except IOError as ioe:
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if dbg_conn: # can be True when wanting details on discontinuity
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print(ioe)
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return False
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return True
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def find_connected_pad(start_pad, pads):
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for p in pads:
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if p == start_pad:
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continue
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if is_connected(start_pad,p):
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return p
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raise IOError( 'no connection to pad %s' % pad_name(start_pad) )
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def find_cpu_pad(pads):
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for p in pads:
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if CPU_REF in pad_name(p):
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return p
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raise IOError( 'no cpu pad' )
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def report_teed_lengths(groupname, netname, target_length, tolerance):
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global dbg_conn
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print(groupname, netname)
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nc = pcb.GetNetcodeFromNetname(netname)
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#print("nc", nc)
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pads = nets[netname].Pads()
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# convert from std::vector<> to python list
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pads = list(pads)
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#print_pads(netname, pads )
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cpu_pad = find_cpu_pad(pads)
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pads.remove(cpu_pad)
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# a trap for a troublesome net that appears to be disconnected or has stray segments.
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if netname == None:
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#if netname == '/DDR3/DRAM_SDCKE0':
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dbg_conn = True
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# find the first T
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#print_pads(netname + ' without cpu pad', pads )
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t1 = find_connected_pad(cpu_pad, pads)
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pads.remove(t1)
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# find 2 second tier T pads
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t2_1 = find_connected_pad(t1, pads)
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pads.remove(t2_1)
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t2_2 = find_connected_pad(t1, pads)
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pads.remove(t2_2)
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cpad = [0] * 4
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# find 4 memory pads off of each 2nd tier T
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cpad[0] = find_connected_pad(t2_1, pads)
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pads.remove(cpad[0])
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cpad[1] = find_connected_pad(t2_1, pads)
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pads.remove(cpad[1])
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cpad[2] = find_connected_pad(t2_2, pads)
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pads.remove(cpad[2])
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cpad[3] = find_connected_pad(t2_2, pads)
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pads.remove(cpad[3])
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len_t1 = sum_track_lengths(cpu_pad.GetPosition(),t1.GetPosition(),nc)
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#print("len_t1 %.0f" % len_t1)
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len_t2_1 = sum_track_lengths(t1.GetPosition(),t2_1.GetPosition(),nc)
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len_t2_2 = sum_track_lengths(t1.GetPosition(),t2_2.GetPosition(),nc)
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#print("len_t2_1 %.0f" % len_t2_1)
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#print("len_t2_2 %.0f" % len_t2_2)
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lens = [0] * 4
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lens[0] = sum_track_lengths(t2_1.GetPosition(),cpad[0].GetPosition(),nc)
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lens[1] = sum_track_lengths(t2_1.GetPosition(),cpad[1].GetPosition(),nc)
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lens[2] = sum_track_lengths(t2_2.GetPosition(),cpad[2].GetPosition(),nc)
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lens[3] = sum_track_lengths(t2_2.GetPosition(),cpad[3].GetPosition(),nc)
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"""
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for index, total_len in enumerate(lens):
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print( "%s: %.0f" % (pad_name(cpad[index]), lens[index]))
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"""
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# Each net goes from CPU to four memory chips, these are the 4 lengths from
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# CPU to each of the for memory chip balls/pads, some of these journeys are
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# common with one another but branch off at each T.
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lens[0] += len_t1 + len_t2_1
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lens[1] += len_t1 + len_t2_1
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lens[2] += len_t1 + len_t2_2
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lens[3] += len_t1 + len_t2_2
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for index, total_len in enumerate(lens):
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delta = total_len - target_length
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if delta > tolerance:
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print_color( BRIGHTRED, "%s %s len:%.0f long by %.0f mils" %
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(netname, pad_name(cpad[index]), pcbnew.ToMils(total_len), pcbnew.ToMils(delta - tolerance) ))
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elif delta < -tolerance:
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print_color( BRIGHTRED, "%s %s len:%.0f short by %.0f mils" %
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(netname, pad_name(cpad[index]), pcbnew.ToMils(total_len), pcbnew.ToMils(tolerance - delta) ))
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def load_board_and_report_lengths(filename):
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global pcb
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pcb = pcbnew.LoadBoard(filename)
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pcb.BuildListOfNets() # required so 'pcb' contains valid netclass data
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global nets
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nets = pcb.GetNetsByName()
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for netname in ADDR_AND_CMD_NETS:
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report_teed_lengths("addr_and_cmd", netname, ADDR_AND_CMD_LEN, ADDR_AND_CMD_TOLERANCE)
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for netname in CONTROL_NETS:
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report_teed_lengths("control", netname, CONTROL_LEN, CONTROL_TOLERANCE)
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if __name__ == "__main__":
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try:
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boardfile = sys.argv[1]
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except IndexError:
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print("Usage: %s <boardname.kicad_pcb> [--once]" % sys.argv[0])
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sys.exit(1)
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first = True
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while True:
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# wait for the file contents to change
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lastmtime = os.path.getmtime(boardfile)
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mtime = lastmtime
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while mtime == lastmtime and not first:
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try:
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mtime = os.path.getmtime(boardfile)
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except OSError:
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pass # kicad save process seems to momentarily delete file, so there's a race here with "No such file.."
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time.sleep(0.5)
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# The "Debug" build of pcbnew writes to disk slowly, new file takes time to get to disk.
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time.sleep(1)
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first = False
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print( '\033[2J' ) # clear screen, maybe
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load_board_and_report_lengths(boardfile)
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if "--once" in sys.argv:
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sys.exit(0)
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@ -1,4 +1,4 @@
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#!/usr/bin/python
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#!/usr/bin/env python
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# Test the KiCad plugin regarding some expected features.
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@ -13,14 +13,15 @@
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# 3) Entered following command line, script takes no arguments
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# $ PYTHONPATH=. <path_to>/test_kicad_plugin.py
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from pcbnew import IO_MGR, BOARD, FOOTPRINT, FPID, UTF8
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from __future__ import print_function
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from pcbnew import IO_MGR, BOARD, FOOTPRINT, LIB_ID, UTF8
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from os import rename as mv
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tmp_path = '/tmp'
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lib_path1 = "%s/lib1.pretty" % tmp_path
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lib_path2 = "%s/lib2.pretty" % tmp_path
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plugin = IO_MGR.PluginFind( IO_MGR.KICAD )
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plugin = IO_MGR.PluginFind( IO_MGR.KICAD_SEXP )
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# Expecting "KiCad":
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print( "Plugin Type: %s" % plugin.PluginName() )
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@ -46,7 +47,7 @@ board = BOARD()
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# The only way to construct a FOOTPRINT is to pass it a BOARD? Yep.
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module = FOOTPRINT( board )
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fpid = FPID( 'mine' )
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fpid = LIB_ID( '', 'mine' )
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module.SetFPID( fpid )
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@ -65,7 +66,7 @@ footprint = plugin.FootprintLoad( lib_path2, 'footprint' )
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fpid = footprint.GetFPID()
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fpid.SetLibNickname( UTF8( 'mylib' ) )
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name = fpid.Format().GetChars() # example to get the UTF8 char buffer
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name = fpid.Format( fpid ).GetChars() # example to get the UTF8 char buffer
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# Always after a FootprintLoad() the internal name should match the one used to load it.
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print( "Internal name should be 'footprint': '%s'" % name )
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@ -79,7 +80,7 @@ fpid.SetLibNickname( UTF8( 'other_mylib' ) )
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# Always after a FootprintLoad() the internal name should match the one used to load it.
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# Example to print an UTF8 string
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print( "Internal name should be 'mine': '%s'" % fpid.Format() )
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print( "Internal name should be 'mine': '%s'" % fpid.Format( fpid ) )
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# As of 3-Dec-2013 this test is passed by KICAD_PLUGIN and Wayne is owed an atta boy!
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Reference in New Issue