Be cognizant of flashed layers when generating pad shapes.

This commit is contained in:
Jeff Young 2022-02-11 00:51:01 +00:00
parent 6e063247e5
commit 50a4d610a6
6 changed files with 24 additions and 33 deletions

View File

@ -1535,30 +1535,6 @@ bool DRC_ENGINE::IsNetADiffPair( BOARD* aBoard, NETINFO_ITEM* aNet, int& aNetP,
}
std::shared_ptr<SHAPE> DRC_ENGINE::GetShape( BOARD_ITEM* aItem, PCB_LAYER_ID aLayer )
{
if( aItem->Type() == PCB_PAD_T && !static_cast<PAD*>( aItem )->FlashLayer( aLayer ) )
{
PAD* aPad = static_cast<PAD*>( aItem );
if( aPad->GetAttribute() == PAD_ATTRIB::PTH )
{
BOARD_DESIGN_SETTINGS& bds = aPad->GetBoard()->GetDesignSettings();
// Note: drill size represents finish size, which means the actual holes size is the
// plating thickness larger.
auto hole = static_cast<SHAPE_SEGMENT*>( aPad->GetEffectiveHoleShape()->Clone() );
hole->SetWidth( hole->GetWidth() + bds.GetHolePlatingThickness() );
return std::make_shared<SHAPE_SEGMENT>( *hole );
}
return std::make_shared<SHAPE_NULL>();
}
return aItem->GetEffectiveShape( aLayer );
}
bool DRC_ENGINE::IsNetTie( BOARD_ITEM* aItem )
{
if( aItem->GetParent() && aItem->GetParent()->Type() == PCB_FOOTPRINT_T )

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@ -191,8 +191,6 @@ public:
static bool IsNetTie( BOARD_ITEM* aItem );
static std::shared_ptr<SHAPE> GetShape( BOARD_ITEM* aItem, PCB_LAYER_ID aLayer );
private:
void addRule( std::shared_ptr<DRC_RULE>& rule )
{

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@ -297,7 +297,7 @@ bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackAgainstItem( PCB_TRACK* track,
}
}
std::shared_ptr<SHAPE> otherShape = DRC_ENGINE::GetShape( other, layer );
std::shared_ptr<SHAPE> otherShape = other->GetEffectiveShape( layer );
if( trackShape->Collide( otherShape.get(), clearance - m_drcEpsilon, &actual, &pos ) )
{
@ -630,7 +630,7 @@ bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadAgainstItem( PAD* pad, SHAPE* pa
if( !testClearance && !testShorting && !testHoles )
return false;
std::shared_ptr<SHAPE> otherShape = DRC_ENGINE::GetShape( other, aLayer );
std::shared_ptr<SHAPE> otherShape = other->GetEffectiveShape( aLayer );
DRC_CONSTRAINT constraint;
int clearance;
int actual;
@ -791,7 +791,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadClearances( )
for( PCB_LAYER_ID layer : pad->GetLayerSet().Seq() )
{
std::shared_ptr<SHAPE> padShape = DRC_ENGINE::GetShape( pad, layer );
std::shared_ptr<SHAPE> padShape = pad->GetEffectiveShape( layer );
m_copperTree.QueryColliding( pad, layer, layer,
// Filter:

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@ -583,7 +583,7 @@ bool DRC_TEST_PROVIDER_MECHANICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* it
int actual;
VECTOR2I pos;
std::shared_ptr<SHAPE> otherShape = DRC_ENGINE::GetShape( other, layer );
std::shared_ptr<SHAPE> otherShape = other->GetEffectiveShape( layer );
if( testClearance )
{

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@ -33,6 +33,7 @@
#include <geometry/shape_simple.h>
#include <geometry/shape_rect.h>
#include <geometry/shape_compound.h>
#include <geometry/shape_null.h>
#include <string_utils.h>
#include <i18n_utility.h>
#include <view/view.h>
@ -310,6 +311,22 @@ const std::shared_ptr<SHAPE_POLY_SET>& PAD::GetEffectivePolygon() const
std::shared_ptr<SHAPE> PAD::GetEffectiveShape( PCB_LAYER_ID aLayer ) const
{
if( !FlashLayer( aLayer ) )
{
if( GetAttribute() == PAD_ATTRIB::PTH )
{
BOARD_DESIGN_SETTINGS& bds = GetBoard()->GetDesignSettings();
// Note: drill size represents finish size, which means the actual holes size is the
// plating thickness larger.
auto hole = static_cast<SHAPE_SEGMENT*>( GetEffectiveHoleShape()->Clone() );
hole->SetWidth( hole->GetWidth() + bds.GetHolePlatingThickness() );
return std::make_shared<SHAPE_SEGMENT>( *hole );
}
return std::make_shared<SHAPE_NULL>();
}
if( m_shapesDirty )
BuildEffectiveShapes( aLayer );

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@ -2477,8 +2477,8 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent )
if( clearance >= 0 )
{
std::shared_ptr<SHAPE> viaShape = DRC_ENGINE::GetShape( aVia, layer );
std::shared_ptr<SHAPE> otherShape = DRC_ENGINE::GetShape( aOther, layer );
std::shared_ptr<SHAPE> viaShape = aVia->GetEffectiveShape( layer );
std::shared_ptr<SHAPE> otherShape = aOther->GetEffectiveShape( layer );
if( viaShape->Collide( otherShape.get(), clearance - m_drcEpsilon ) )
return true;
@ -2510,7 +2510,7 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent )
if( clearance >= 0 )
{
std::shared_ptr<SHAPE> viaShape = DRC_ENGINE::GetShape( aVia, UNDEFINED_LAYER );
std::shared_ptr<SHAPE> viaShape = aVia->GetEffectiveShape( UNDEFINED_LAYER );
if( viaShape->Collide( holeShape.get(), clearance - m_drcEpsilon ) )
return true;