demo update.
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(module TO-92_BC237_307 (layer F.Cu) (tedit 5A227438)
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(descr "TO-92 leads molded, narrow, drill 0.6mm")
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(tags "to-92 transistor")
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(fp_text reference REF** (at 1.27 -3.56) (layer F.SilkS)
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_text value TO-92_BC307 (at 1.27 2.79) (layer F.Fab)
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_text user %R (at 1.27 -3.56) (layer F.Fab)
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_line (start -0.53 1.85) (end 3.07 1.85) (layer F.SilkS) (width 0.12))
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(fp_line (start -0.5 1.75) (end 3 1.75) (layer F.Fab) (width 0.1))
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(fp_line (start -1.46 -2.73) (end 4 -2.73) (layer F.CrtYd) (width 0.05))
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(fp_line (start -1.46 -2.73) (end -1.46 2.01) (layer F.CrtYd) (width 0.05))
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(fp_line (start 4 2.01) (end 4 -2.73) (layer F.CrtYd) (width 0.05))
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(fp_line (start 4 2.01) (end -1.46 2.01) (layer F.CrtYd) (width 0.05))
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(fp_arc (start 1.27 0) (end 1.27 -2.48) (angle 135) (layer F.Fab) (width 0.1))
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(fp_arc (start 1.27 0) (end 1.27 -2.6) (angle -135) (layer F.SilkS) (width 0.12))
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(fp_arc (start 1.27 0) (end 1.27 -2.48) (angle -135) (layer F.Fab) (width 0.1))
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(fp_arc (start 1.27 0) (end 1.27 -2.6) (angle 135) (layer F.SilkS) (width 0.12))
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(pad 2 thru_hole circle (at 1.27 -1.27 90) (size 1 1) (drill 0.6) (layers *.Cu *.Mask))
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(pad 1 thru_hole rect (at 2.54 0 90) (size 1 1) (drill 0.6) (layers *.Cu *.Mask))
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(pad 3 thru_hole circle (at 0 0 90) (size 1 1) (drill 0.6) (layers *.Cu *.Mask))
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(model ${KISYS3DMOD}/TO_SOT_Packages_THT.3dshapes/TO-92_Molded_Narrow.wrl
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(offset (xyz 1.269999980926514 0 0))
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(scale (xyz 1 1 1))
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(rotate (xyz 0 0 -90))
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)
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)
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update=19/01/2020 20:27:59
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update=15/04/2020 15:22:14
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last_client=kicad
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last_client=pcbnew
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[common]
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[common]
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NetDir=
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NetDir=
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[cvpcb]
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[cvpcb]
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@ -12,11 +12,13 @@ version=1
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[eeschema]
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[eeschema]
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version=1
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version=1
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LibDir=
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LibDir=
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[ModEditFrame]
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version=1
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[pcbnew]
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[pcbnew]
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version=1
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version=1
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PageLayoutDescrFile=
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PageLayoutDescrFile=
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LastNetListRead=pic_programmer.net
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LastNetListRead=pic_programmer.net
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LastSTEPExportPath=
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LastSTEPExportPath=pic_programmer.step
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LastIDFExportPath=
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LastIDFExportPath=
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LastVRMLExportPath=
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LastVRMLExportPath=
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LastSpecctraDSNExportPath=
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LastSpecctraDSNExportPath=
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@ -25,14 +27,14 @@ CopperLayerCount=2
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BoardThickness=1.6
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BoardThickness=1.6
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AllowMicroVias=0
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AllowMicroVias=0
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AllowBlindVias=0
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AllowBlindVias=0
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RequireCourtyardDefinitions=0
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ProhibitOverlappingCourtyards=1
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MinTrackWidth=0.25
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MinTrackWidth=0.25
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MinViaDiameter=0.8999999999999999
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MinViaDiameter=0.8999999999999999
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MinViaDrill=0.5
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MinViaDrill=0.5
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MinMicroViaDiameter=0.508
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MinMicroViaDiameter=0.508
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MinMicroViaDrill=0.127
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MinMicroViaDrill=0.127
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MinHoleToHole=0.25
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MinHoleToHole=0.25
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RequireCourtyardDefinitions=0
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ProhibitOverlappingCourtyards=1
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CopperEdgeClearance=0.01
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CopperEdgeClearance=0.01
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TrackWidth1=0.5
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TrackWidth1=0.5
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TrackWidth2=0.4
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TrackWidth2=0.4
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@ -67,7 +69,7 @@ DimensionPrecision=1
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SolderMaskClearance=0.09999999999999999
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SolderMaskClearance=0.09999999999999999
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SolderMaskMinWidth=0
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SolderMaskMinWidth=0
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SolderPasteClearance=0
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SolderPasteClearance=0
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SolderPasteRatio=-0
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SolderPasteRatio=0
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[pcbnew/Layer.F.Cu]
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[pcbnew/Layer.F.Cu]
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Name=top_layer
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Name=top_layer
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Type=0
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Type=0
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