demo update.

This commit is contained in:
jean-pierre charras 2020-04-15 15:31:40 +02:00
parent 5aac36dba9
commit 515e57c02f
4 changed files with 4646 additions and 8363 deletions

View File

@ -1,31 +0,0 @@
(module TO-92_BC237_307 (layer F.Cu) (tedit 5A227438)
(descr "TO-92 leads molded, narrow, drill 0.6mm")
(tags "to-92 transistor")
(fp_text reference REF** (at 1.27 -3.56) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TO-92_BC307 (at 1.27 2.79) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 1.27 -3.56) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.53 1.85) (end 3.07 1.85) (layer F.SilkS) (width 0.12))
(fp_line (start -0.5 1.75) (end 3 1.75) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 -2.73) (end 4 -2.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.46 -2.73) (end -1.46 2.01) (layer F.CrtYd) (width 0.05))
(fp_line (start 4 2.01) (end 4 -2.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 4 2.01) (end -1.46 2.01) (layer F.CrtYd) (width 0.05))
(fp_arc (start 1.27 0) (end 1.27 -2.48) (angle 135) (layer F.Fab) (width 0.1))
(fp_arc (start 1.27 0) (end 1.27 -2.6) (angle -135) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end 1.27 -2.48) (angle -135) (layer F.Fab) (width 0.1))
(fp_arc (start 1.27 0) (end 1.27 -2.6) (angle 135) (layer F.SilkS) (width 0.12))
(pad 2 thru_hole circle (at 1.27 -1.27 90) (size 1 1) (drill 0.6) (layers *.Cu *.Mask))
(pad 1 thru_hole rect (at 2.54 0 90) (size 1 1) (drill 0.6) (layers *.Cu *.Mask))
(pad 3 thru_hole circle (at 0 0 90) (size 1 1) (drill 0.6) (layers *.Cu *.Mask))
(model ${KISYS3DMOD}/TO_SOT_Packages_THT.3dshapes/TO-92_Molded_Narrow.wrl
(offset (xyz 1.269999980926514 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 -90))
)
)

File diff suppressed because it is too large Load Diff

View File

@ -1,5 +1,5 @@
update=19/01/2020 20:27:59 update=15/04/2020 15:22:14
last_client=kicad last_client=pcbnew
[common] [common]
NetDir= NetDir=
[cvpcb] [cvpcb]
@ -12,11 +12,13 @@ version=1
[eeschema] [eeschema]
version=1 version=1
LibDir= LibDir=
[ModEditFrame]
version=1
[pcbnew] [pcbnew]
version=1 version=1
PageLayoutDescrFile= PageLayoutDescrFile=
LastNetListRead=pic_programmer.net LastNetListRead=pic_programmer.net
LastSTEPExportPath= LastSTEPExportPath=pic_programmer.step
LastIDFExportPath= LastIDFExportPath=
LastVRMLExportPath= LastVRMLExportPath=
LastSpecctraDSNExportPath= LastSpecctraDSNExportPath=
@ -25,14 +27,14 @@ CopperLayerCount=2
BoardThickness=1.6 BoardThickness=1.6
AllowMicroVias=0 AllowMicroVias=0
AllowBlindVias=0 AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.25 MinTrackWidth=0.25
MinViaDiameter=0.8999999999999999 MinViaDiameter=0.8999999999999999
MinViaDrill=0.5 MinViaDrill=0.5
MinMicroViaDiameter=0.508 MinMicroViaDiameter=0.508
MinMicroViaDrill=0.127 MinMicroViaDrill=0.127
MinHoleToHole=0.25 MinHoleToHole=0.25
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
CopperEdgeClearance=0.01 CopperEdgeClearance=0.01
TrackWidth1=0.5 TrackWidth1=0.5
TrackWidth2=0.4 TrackWidth2=0.4
@ -67,7 +69,7 @@ DimensionPrecision=1
SolderMaskClearance=0.09999999999999999 SolderMaskClearance=0.09999999999999999
SolderMaskMinWidth=0 SolderMaskMinWidth=0
SolderPasteClearance=0 SolderPasteClearance=0
SolderPasteRatio=-0 SolderPasteRatio=0
[pcbnew/Layer.F.Cu] [pcbnew/Layer.F.Cu]
Name=top_layer Name=top_layer
Type=0 Type=0