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altium: initial code to parse ports. Includes a hack until we know which side to connect to. 

Fix: https://gitlab.com/kicad/code/kicad/-/issues/6056
This commit is contained in:
Thomas Pointhuber 2020-10-26 16:54:49 +01:00
parent f7084afb72
commit 52b5e4d0b3
4 changed files with 141 additions and 0 deletions
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21
eeschema/sch_plugins/altium/altium_parser_sch.cpp
View File

@ -387,6 +387,27 @@ ASCH_POWER_PORT::ASCH_POWER_PORT( const std::map<wxString, wxString>& aPropertie
aProperties, "STYLE", 0, 10, ASCH_POWER_PORT_STYLE::CIRCLE );
}
ASCH_PORT::ASCH_PORT( const std::map<wxString, wxString>& aProperties )
{
wxASSERT( PropertiesReadRecord( aProperties ) == ALTIUM_SCH_RECORD::PORT );
ownerpartid =
ALTIUM_PARSER::PropertiesReadInt( aProperties, "OWNERPARTID", ALTIUM_COMPONENT_NONE );
location = wxPoint( PropertiesReadKiCadUnitFrac( aProperties, "LOCATION.X" ),
-PropertiesReadKiCadUnitFrac( aProperties, "LOCATION.Y" ) );
name = ALTIUM_PARSER::PropertiesReadString( aProperties, "NAME", "" );
width = PropertiesReadKiCadUnitFrac( aProperties, "WIDTH" );
height = PropertiesReadKiCadUnitFrac( aProperties, "HEIGHT" );
iotype = PropertiesReadEnum<ASCH_PORT_IOTYPE>(
aProperties, "IOTYPE", 0, 3, ASCH_PORT_IOTYPE::UNSPECIFIED );
style = PropertiesReadEnum<ASCH_PORT_STYLE>(
aProperties, "STYLE", 0, 7, ASCH_PORT_STYLE::NONE_HORIZONTAL );
}
ASCH_NO_ERC::ASCH_NO_ERC( const std::map<wxString, wxString>& aProperties )
{

39
eeschema/sch_plugins/altium/altium_parser_sch.h
View File

@ -406,6 +406,45 @@ struct ASCH_POWER_PORT
};
enum class ASCH_PORT_IOTYPE
{
UNSPECIFIED = 0,
OUTPUT = 1,
INPUT = 2,
BIDI = 3,
};
enum class ASCH_PORT_STYLE
{
NONE_HORIZONTAL = 0,
LEFT = 1,
RIGHT = 2,
LEFT_RIGHT = 3,
NONE_VERTICAL = 4,
TOP = 5,
BOTTOM = 6,
TOP_BOTTOM = 7
};
struct ASCH_PORT
{
int ownerpartid;
wxString name;
wxPoint location;
int width;
int height;
ASCH_PORT_IOTYPE iotype;
ASCH_PORT_STYLE style;
explicit ASCH_PORT( const std::map<wxString, wxString>& aProperties );
};
struct ASCH_NO_ERC
{
wxPoint location;

80
eeschema/sch_plugins/altium/sch_altium_plugin.cpp
View File

@ -345,6 +345,7 @@ void SCH_ALTIUM_PLUGIN::Parse( const CFB::CompoundFileReader& aReader )
ParsePowerPort( properties );
break;
case ALTIUM_SCH_RECORD::PORT:
ParsePort( properties );
break;
case ALTIUM_SCH_RECORD::NO_ERC:
ParseNoERC( properties );
@ -1527,6 +1528,85 @@ void SCH_ALTIUM_PLUGIN::ParsePowerPort( const std::map<wxString, wxString>& aPro
}
void SCH_ALTIUM_PLUGIN::ParsePort( const std::map<wxString, wxString>& aProperties )
{
ASCH_PORT elem( aProperties );
SCH_TEXT* const label = new SCH_GLOBALLABEL( elem.location + m_sheetOffset, elem.name );
// TODO: detect correct label type depending on sheet settings, etc.
// label = new SCH_HIERLABEL( elem.location + m_sheetOffset, elem.name );
switch( elem.iotype )
{
default:
case ASCH_PORT_IOTYPE::UNSPECIFIED:
label->SetShape( PINSHEETLABEL_SHAPE::PS_UNSPECIFIED );
break;
case ASCH_PORT_IOTYPE::OUTPUT:
label->SetShape( PINSHEETLABEL_SHAPE::PS_OUTPUT );
break;
case ASCH_PORT_IOTYPE::INPUT:
label->SetShape( PINSHEETLABEL_SHAPE::PS_INPUT );
break;
case ASCH_PORT_IOTYPE::BIDI:
label->SetShape( PINSHEETLABEL_SHAPE::PS_BIDI );
break;
}
switch( elem.style )
{
default:
case ASCH_PORT_STYLE::NONE_HORIZONTAL:
case ASCH_PORT_STYLE::LEFT:
case ASCH_PORT_STYLE::RIGHT:
case ASCH_PORT_STYLE::LEFT_RIGHT:
label->SetLabelSpinStyle( LABEL_SPIN_STYLE::RIGHT );
break;
case ASCH_PORT_STYLE::NONE_VERTICAL:
case ASCH_PORT_STYLE::TOP:
case ASCH_PORT_STYLE::BOTTOM:
case ASCH_PORT_STYLE::TOP_BOTTOM:
label->SetLabelSpinStyle( LABEL_SPIN_STYLE::UP );
break;
}
label->SetFlags( IS_NEW );
m_currentSheet->GetScreen()->Append( label );
// TODO: This is a hack until we know where we need to connect the label.
// The problem is that, apparently, Altium allows us to connect to the label from both sides
wxPoint start = elem.location + m_sheetOffset;
switch( elem.style )
{
default:
case ASCH_PORT_STYLE::NONE_HORIZONTAL:
case ASCH_PORT_STYLE::LEFT:
case ASCH_PORT_STYLE::RIGHT:
case ASCH_PORT_STYLE::LEFT_RIGHT:
{
SCH_LINE* wire = new SCH_LINE( start, SCH_LAYER_ID::LAYER_WIRE );
wire->SetEndPoint( { start.x + elem.width, start.y } );
wire->SetLineWidth( Mils2iu( 2 ) );
wire->SetFlags( IS_NEW );
m_currentSheet->GetScreen()->Append( wire );
break;
}
case ASCH_PORT_STYLE::NONE_VERTICAL:
case ASCH_PORT_STYLE::TOP:
case ASCH_PORT_STYLE::BOTTOM:
case ASCH_PORT_STYLE::TOP_BOTTOM:
{
SCH_LINE* wire = new SCH_LINE( start, SCH_LAYER_ID::LAYER_WIRE );
wire->SetEndPoint( { start.x, start.y - elem.width } );
wire->SetLineWidth( Mils2iu( 2 ) );
wire->SetFlags( IS_NEW );
m_currentSheet->GetScreen()->Append( wire );
break;
}
}
}
void SCH_ALTIUM_PLUGIN::ParseNoERC( const std::map<wxString, wxString>& aProperties )
{
ASCH_NO_ERC elem( aProperties );

1
eeschema/sch_plugins/altium/sch_altium_plugin.h
View File

@ -115,6 +115,7 @@ private:
void ParseLine( const std::map<wxString, wxString>& aProperties );
void ParseRectangle( const std::map<wxString, wxString>& aProperties );
void ParsePowerPort( const std::map<wxString, wxString>& aProperties );
void ParsePort( const std::map<wxString, wxString>& aProperties );
void ParseNoERC( const std::map<wxString, wxString>& aProperties );
void ParseNetLabel( const std::map<wxString, wxString>& aProperties );
void ParseBus( const std::map<wxString, wxString>& aProperties );