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Optimize VIA LoD calculation.

This commit is contained in:
Alex Shvartzkop 2024-06-12 23:03:58 +03:00
parent 9d0ee029bc
commit 52daf14c78
1 changed files with 17 additions and 3 deletions
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20
pcbnew/pcb_track.cpp
View File

@ -1230,8 +1230,17 @@ double PCB_VIA::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
else if( LSET::BackTechMask().Contains( highContrastLayer ) ) else if( LSET::BackTechMask().Contains( highContrastLayer ) )
highContrastLayer = B_Cu; highContrastLayer = B_Cu;
if( !GetLayerSet().Contains( highContrastLayer ) ) if( !IsCopperLayer( highContrastLayer ) )
return HIDE; return HIDE;
if( GetViaType() != VIATYPE::THROUGH )
{
if( highContrastLayer < Padstack().Drill().start
|| highContrastLayer > Padstack().Drill().end )
{
return HIDE;
}
}
} }
if( IsHoleLayer( aLayer ) ) if( IsHoleLayer( aLayer ) )
@ -1248,6 +1257,9 @@ double PCB_VIA::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
if( !( visible & LSET::PhysicalLayersMask() ).any() ) if( !( visible & LSET::PhysicalLayersMask() ).any() )
return HIDE; return HIDE;
} }
// The hole won't be visible anyway at this scale
return (double) pcbIUScale.mmToIU( 0.25 ) / GetDrillValue();
} }
else if( IsNetnameLayer( aLayer ) ) else if( IsNetnameLayer( aLayer ) )
{ {
@ -1268,8 +1280,10 @@ double PCB_VIA::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
return m_Width == 0 ? HIDE : ( (double)pcbIUScale.mmToIU( 10 ) / m_Width ); return m_Width == 0 ? HIDE : ( (double)pcbIUScale.mmToIU( 10 ) / m_Width );
} }
// Passed all tests; show. if( IsCopperLayer( aLayer ) )
return 0.0; return (double) pcbIUScale.mmToIU( 1 ) / m_Width;
else
return (double) pcbIUScale.mmToIU( 0.6 ) / m_Width;
} }