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Fix hierarchical propagation for designs with unmatched hier ports 

Fixes https://gitlab.com/kicad/code/kicad/-/issues/8397
This commit is contained in:
Jon Evans 2021-05-10 17:54:09 -04:00
parent 7356f9568d
commit 55c1d814f9
7 changed files with 708 additions and 11 deletions
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29
eeschema/connection_graph.cpp
View File

@ -1365,6 +1365,9 @@ void CONNECTION_GRAPH::buildConnectionGraph()
if( !subgraph->m_dirty )
continue;
wxLogTrace( ConnTrace, "Processing %lu (%s) for propagation", subgraph->m_code,
subgraph->m_driver_connection->Name() );
// For subgraphs that are driven by a global (power port or label) and have more
// than one global driver, we need to seek out other subgraphs driven by the
// same name as the non-chosen driver and update them to match the chosen one.
@ -1423,6 +1426,9 @@ void CONNECTION_GRAPH::buildConnectionGraph()
for( CONNECTION_SUBGRAPH* subgraph : m_driver_subgraphs )
{
// All SGs should have been processed by propagateToNeighbors above
wxASSERT_MSG( !subgraph->m_dirty, "Subgraph not processed by propagateToNeighbors!" );
if( subgraph->m_bus_parents.size() < 2 )
continue;
@ -1789,21 +1795,22 @@ void CONNECTION_GRAPH::propagateToNeighbors( CONNECTION_SUBGRAPH* aSubgraph )
if( conn->IsBus() )
propagate_bus_neighbors( aSubgraph );
// If we don't have any hier pins (i.e. no children), nothing to do
if( aSubgraph->m_hier_pins.empty() )
// If we have both ports and pins, skip processing as we'll be visited by a parent or child.
// If we only have one or the other, process (we can either go bottom-up or top-down depending
// on which subgraph comes up first)
if( !aSubgraph->m_hier_ports.empty() && !aSubgraph->m_hier_pins.empty() )
{
// If we also don't have any parents, we'll never be visited again
if( aSubgraph->m_hier_ports.empty() )
aSubgraph->m_dirty = false;
wxLogTrace( ConnTrace, "%lu (%s) has both hier ports and pins; deferring processing",
aSubgraph->m_code, conn->Name() );
return;
}
// If we do have hier ports, skip this subgraph as it will be visited by a parent
// TODO(JE) this will leave the subgraph dirty if there is no matching parent subgraph,
// which should be flagged as an ERC error
if( !aSubgraph->m_hier_ports.empty() )
else if( aSubgraph->m_hier_ports.empty() && aSubgraph->m_hier_pins.empty() )
{
wxLogTrace( ConnTrace, "%lu (%s) has no hier pins or ports; marking clean",
aSubgraph->m_code, conn->Name() );
aSubgraph->m_dirty = false;
return;
}
visited.insert( aSubgraph );

48
qa/eeschema/data/netlists/top_level_hier_pins/subsheet.kicad_sch Normal file
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qa/eeschema/data/netlists/top_level_hier_pins/top_level_hier_pins.kicad_pro Normal file
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(comment (number "8") (value ""))
(comment (number "9") (value ""))))
(sheet (number "3") (name "/Subsheet1/SubSubSheet/") (tstamps "/8b055b93-d115-4991-b853-dd747f0957ab/d1e0bb44-07da-4574-92bf-3f9adc5e8751/")
(title_block
(title)
(company)
(rev)
(date)
(source "subsubsheet.kicad_sch")
(comment (number "1") (value ""))
(comment (number "2") (value ""))
(comment (number "3") (value ""))
(comment (number "4") (value ""))
(comment (number "5") (value ""))
(comment (number "6") (value ""))
(comment (number "7") (value ""))
(comment (number "8") (value ""))
(comment (number "9") (value "")))))
(components
(comp (ref "R1")
(value "R")
(datasheet "~")
(libsource (lib "Device") (part "R") (description "Resistor"))
(property (name "Sheetname") (value "SubSubSheet"))
(property (name "Sheetfile") (value "subsubsheet.kicad_sch"))
(sheetpath (names "/Subsheet1/SubSubSheet/") (tstamps "/8b055b93-d115-4991-b853-dd747f0957ab/d1e0bb44-07da-4574-92bf-3f9adc5e8751/"))
(tstamps "d21dccc4-3b84-4309-8a03-49ef532d46d9"))
(comp (ref "R2")
(value "R")
(datasheet "~")
(libsource (lib "Device") (part "R") (description "Resistor"))
(property (name "Sheetname") (value "SubSubSheet"))
(property (name "Sheetfile") (value "subsubsheet.kicad_sch"))
(sheetpath (names "/Subsheet1/SubSubSheet/") (tstamps "/8b055b93-d115-4991-b853-dd747f0957ab/d1e0bb44-07da-4574-92bf-3f9adc5e8751/"))
(tstamps "34621417-dac8-4a11-b54c-b5b5c180b754")))
(libparts
(libpart (lib "Device") (part "R")
(description "Resistor")
(docs "~")
(footprints
(fp "R_*"))
(fields
(field (name "Reference") "R")
(field (name "Value") "R")
(field (name "Datasheet") "~"))
(pins
(pin (num "1") (name "~") (type "passive"))
(pin (num "2") (name "~") (type "passive")))))
(libraries
(library (logical "Device")
(uri "/usr/local/share/kicad/library//Device.kicad_sym")))
(nets
(net (code "1") (name "/INPUT")
(node (ref "R1") (pin "1") (pintype "passive")))
(net (code "2") (name "/Subsheet1/SUB_OUTPUT")
(node (ref "R2") (pin "1") (pintype "passive")))
(net (code "3") (name "GND")
(node (ref "R1") (pin "2") (pintype "passive"))
(node (ref "R2") (pin "2") (pintype "passive")))))

6
qa/eeschema/test_netlists.cpp
View File

@ -290,4 +290,10 @@ BOOST_AUTO_TEST_CASE( GroupBusMatching )
}
BOOST_AUTO_TEST_CASE( TopLevelHierPins )
{
doNetlistTest( "top_level_hier_pins" );
}
BOOST_AUTO_TEST_SUITE_END()