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Remove extraneous files added in 69858ab4c0 

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Seth Hillbrand 2022-06-30 11:09:03 -07:00
parent ef2bb0b621
commit 55de16e874
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pcbnew/drc/drc_test_provider_physical_clearance.cpp
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/*
* This program source code file is part of KiCad, a free EDA CAD application.
*
* Copyright (C) 2021-2022 KiCad Developers.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you may find one here:
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
* or you may search the http://www.gnu.org website for the version 2 license,
* or you may write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
#include <common.h>
#include <macros.h>
#include <board_design_settings.h>
#include <footprint.h>
#include <pad.h>
#include <pcb_track.h>
#include <pcb_shape.h>
#include <zone.h>
#include <advanced_config.h>
#include <geometry/seg.h>
#include <geometry/shape_segment.h>
#include <drc/drc_engine.h>
#include <drc/drc_rtree.h>
#include <drc/drc_item.h>
#include <drc/drc_rule.h>
#include <drc/drc_test_provider_clearance_base.h>
/*
Physical clearance tests.
Errors generated:
- DRCE_PHYSICAL_CLEARANCE
- DRCE_PHYSICAL_HOLE_CLEARANCE
*/
class DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE : public DRC_TEST_PROVIDER_CLEARANCE_BASE
{
public:
DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE () :
DRC_TEST_PROVIDER_CLEARANCE_BASE()
{
}
virtual ~DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE()
{
}
virtual bool Run() override;
virtual const wxString GetName() const override
{
return wxT( "physical_clearance" );
};
virtual const wxString GetDescription() const override
{
return wxT( "Tests item clearances irrespective of nets" );
}
private:
bool testItemAgainstItem( BOARD_ITEM* item, SHAPE* itemShape, PCB_LAYER_ID layer,
BOARD_ITEM* other );
void testItemAgainstZones( BOARD_ITEM* aItem, PCB_LAYER_ID aLayer );
void testShapeLineChain( const SHAPE_LINE_CHAIN& aOutline, int aLineWidth, PCB_LAYER_ID aLayer,
BOARD_ITEM* aParentItem, DRC_CONSTRAINT& aConstraint );
void testZoneLayer( ZONE* aZone, PCB_LAYER_ID aLayer, DRC_CONSTRAINT& aConstraint );
private:
DRC_RTREE m_itemTree;
std::vector<ZONE*> m_zones;
};
bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::Run()
{
m_board = m_drcEngine->GetBoard();
m_itemTree.clear();
m_zones.clear();
m_zones.reserve( m_board->Zones().size() );
int errorMax = m_board->GetDesignSettings().m_MaxError;
DRC_CONSTRAINT worstConstraint;
if( m_drcEngine->QueryWorstConstraint( PHYSICAL_CLEARANCE_CONSTRAINT, worstConstraint ) )
m_largestClearance = worstConstraint.GetValue().Min();
if( m_drcEngine->QueryWorstConstraint( PHYSICAL_HOLE_CLEARANCE_CONSTRAINT, worstConstraint ) )
m_largestClearance = std::max( m_largestClearance, worstConstraint.GetValue().Min() );
if( m_largestClearance <= 0 )
{
reportAux( wxT( "No Clearance constraints found. Tests not run." ) );
return true; // continue with other tests
}
for( ZONE* zone : m_board->Zones() )
{
if( !zone->GetIsRuleArea() )
{
m_zones.push_back( zone );
m_largestClearance = std::max( m_largestClearance, zone->GetLocalClearance() );
}
}
for( FOOTPRINT* footprint : m_board->Footprints() )
{
for( PAD* pad : footprint->Pads() )
m_largestClearance = std::max( m_largestClearance, pad->GetLocalClearance() );
for( ZONE* zone : footprint->Zones() )
{
if( !zone->GetIsRuleArea() )
{
m_zones.push_back( zone );
m_largestClearance = std::max( m_largestClearance, zone->GetLocalClearance() );
}
}
}
reportAux( wxT( "Worst clearance : %d nm" ), m_largestClearance );
// This is the number of tests between 2 calls to the progress bar
size_t delta = 100;
size_t count = 0;
size_t ii = 0;
if( !reportPhase( _( "Gathering items..." ) ) )
return false; // DRC cancelled
static const std::vector<KICAD_T> itemTypes = {
PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T,
PCB_FOOTPRINT_T,
PCB_PAD_T,
PCB_SHAPE_T, PCB_FP_SHAPE_T,
PCB_TEXT_T, PCB_FP_TEXT_T, PCB_TEXTBOX_T, PCB_FP_TEXTBOX_T,
PCB_DIMENSION_T
};
static const LSET courtyards( 2, F_CrtYd, B_CrtYd );
forEachGeometryItem( itemTypes, LSET::AllLayersMask(),
[&]( BOARD_ITEM* item ) -> bool
{
++count;
return true;
} );
forEachGeometryItem( itemTypes, LSET::AllLayersMask(),
[&]( BOARD_ITEM* item ) -> bool
{
if( !reportProgress( ii++, count, delta ) )
return false;
LSET layers = item->GetLayerSet();
// Special-case holes and edge-cuts which pierce all physical layers
if( item->Type() == PCB_PAD_T )
{
PAD* pad = static_cast<PAD*>( item );
if( pad->GetDrillSizeX() > 0 && pad->GetDrillSizeY() > 0 )
layers |= LSET::PhysicalLayersMask() | courtyards;
}
else if( item->Type() == PCB_VIA_T )
{
PCB_VIA* via = static_cast<PCB_VIA*>( item );
if( via->GetDrill() > 0 )
layers |= LSET::PhysicalLayersMask() | courtyards;
}
else if( item->Type() == PCB_FOOTPRINT_T )
{
layers = courtyards;
}
else if( item->IsOnLayer( Edge_Cuts ) )
{
layers |= LSET::PhysicalLayersMask() | courtyards;
}
for( PCB_LAYER_ID layer : layers.Seq() )
m_itemTree.Insert( item, layer, m_largestClearance );
return true;
} );
std::map< std::pair<BOARD_ITEM*, BOARD_ITEM*>, int> checkedPairs;
ii = 0;
if( !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE )
|| !m_drcEngine->IsErrorLimitExceeded( DRCE_HOLE_CLEARANCE ) )
{
if( !reportPhase( _( "Checking physical clearances..." ) ) )
return false; // DRC cancelled
forEachGeometryItem( itemTypes, LSET::AllLayersMask(),
[&]( BOARD_ITEM* item ) -> bool
{
if( !reportProgress( ii++, count, delta ) )
return false;
LSET layers = item->GetLayerSet();
if( item->Type() == PCB_FOOTPRINT_T )
layers = courtyards;
for( PCB_LAYER_ID layer : layers.Seq() )
{
std::shared_ptr<SHAPE> itemShape = item->GetEffectiveShape( layer );
m_itemTree.QueryColliding( item, layer, layer,
// Filter:
[&]( BOARD_ITEM* other ) -> bool
{
BOARD_ITEM* a = item;
BOARD_ITEM* b = other;
// store canonical order so we don't collide in both
// directions (a:b and b:a)
if( static_cast<void*>( a ) > static_cast<void*>( b ) )
std::swap( a, b );
if( checkedPairs.count( { a, b } ) )
{
return false;
}
else
{
checkedPairs[ { a, b } ] = 1;
return true;
}
},
// Visitor:
[&]( BOARD_ITEM* other ) -> bool
{
return testItemAgainstItem( item, itemShape.get(), layer,
other );
},
m_largestClearance );
testItemAgainstZones( item, layer );
}
return true;
} );
}
count = 0;
ii = 0;
forEachGeometryItem( { PCB_ZONE_T, PCB_FP_ZONE_T, PCB_SHAPE_T, PCB_FP_SHAPE_T },
LSET::AllCuMask(),
[&]( BOARD_ITEM* item ) -> bool
{
ZONE* zone = dynamic_cast<ZONE*>( item );
if( zone && zone->GetIsRuleArea() )
return true; // Continue with other items
count += ( item->GetLayerSet() & LSET::AllCuMask() ).count();
return true;
} );
forEachGeometryItem( { PCB_ZONE_T, PCB_FP_ZONE_T, PCB_SHAPE_T, PCB_FP_SHAPE_T },
LSET::AllCuMask(),
[&]( BOARD_ITEM* item ) -> bool
{
PCB_SHAPE* shape = dynamic_cast<PCB_SHAPE*>( item );
ZONE* zone = dynamic_cast<ZONE*>( item );
if( zone && zone->GetIsRuleArea() )
return true; // Continue with other items
for( PCB_LAYER_ID layer : item->GetLayerSet().Seq() )
{
if( IsCopperLayer( layer ) )
{
if( !reportProgress( ii++, count, delta ) )
return false;
DRC_CONSTRAINT c = m_drcEngine->EvalRules( PHYSICAL_CLEARANCE_CONSTRAINT,
item, nullptr, layer );
if( shape )
{
switch( shape->GetShape() )
{
case SHAPE_T::POLY:
testShapeLineChain( shape->GetPolyShape().Outline( 0 ),
shape->GetWidth(), layer, item, c );
break;
case SHAPE_T::BEZIER:
{
SHAPE_LINE_CHAIN asPoly;
shape->RebuildBezierToSegmentsPointsList( shape->GetWidth() );
for( const VECTOR2I& pt : shape->GetBezierPoints() )
asPoly.Append( pt );
testShapeLineChain( asPoly, shape->GetWidth(), layer, item, c );
break;
}
case SHAPE_T::ARC:
{
SHAPE_LINE_CHAIN asPoly;
VECTOR2I center = shape->GetCenter();
EDA_ANGLE angle = -shape->GetArcAngle();
double r = shape->GetRadius();
int steps = GetArcToSegmentCount( r, errorMax, angle );
asPoly.Append( shape->GetStart() );
for( int step = 1; step <= steps; ++step )
{
EDA_ANGLE rotation = ( angle * step ) / steps;
VECTOR2I pt = shape->GetStart();
RotatePoint( pt, center, rotation );
asPoly.Append( pt );
}
testShapeLineChain( asPoly, shape->GetWidth(), layer, item, c );
break;
}
case SHAPE_T::RECT:
{
SHAPE_LINE_CHAIN asPoly;
std::vector<VECTOR2I> pts = shape->GetRectCorners();
asPoly.Append( pts[0] );
asPoly.Append( pts[1] );
asPoly.Append( pts[2] );
asPoly.Append( pts[3] );
asPoly.SetClosed( true );
testShapeLineChain( asPoly, shape->GetWidth(), layer, item, c );
break;
}
default:
UNIMPLEMENTED_FOR( shape->SHAPE_T_asString() );
}
}
if( zone )
testZoneLayer( static_cast<ZONE*>( item ), layer, c );
}
if( m_drcEngine->IsCancelled() )
return false;
}
return !m_drcEngine->IsCancelled();
} );
reportRuleStatistics();
return !m_drcEngine->IsCancelled();
}
void DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testShapeLineChain( const SHAPE_LINE_CHAIN& aOutline,
int aLineWidth, PCB_LAYER_ID aLayer,
BOARD_ITEM* aParentItem,
DRC_CONSTRAINT& aConstraint )
{
// We don't want to collide with neighboring segments forming a curve until the concavity
// approaches 180 degrees.
double angleTolerance = DEG2RAD( 180.0 - ADVANCED_CFG::GetCfg().m_SliverAngleTolerance );
int epsilon = m_board->GetDesignSettings().GetDRCEpsilon();
int count = aOutline.SegmentCount();
int clearance = aConstraint.GetValue().Min();
// Trigonometry is not cheap; cache seg angles
std::vector<double> angles;
angles.reserve( count );
auto angleDiff =
[]( double a, double b ) -> double
{
if( a > b )
std::swap( a, b );
double diff = b - a;
if( diff > M_PI )
return 2 * M_PI - diff;
else
return diff;
};
for( int ii = 0; ii < count; ++ii )
{
const SEG& seg = aOutline.CSegment( ii );
// NB: don't store angles of really short segments (which could point anywhere)
if( seg.SquaredLength() > SEG::Square( epsilon * 2 ) )
{
angles.push_back( EDA_ANGLE( seg.B - seg.A ).AsRadians() );
}
else if( ii > 0 )
{
angles.push_back( angles.back() );
}
else
{
for( int jj = 1; jj < count; ++jj )
{
const SEG& following = aOutline.CSegment( jj );
if( following.SquaredLength() > SEG::Square( epsilon * 2 ) || jj == count - 1 )
{
angles.push_back( EDA_ANGLE( following.B - following.A ).AsRadians() );
break;
}
}
}
}
// Find collisions before reporting so that we can condense them into fewer reports.
std::vector< std::pair<VECTOR2I, int> > collisions;
for( int ii = 0; ii < count; ++ii )
{
const SEG seg = aOutline.CSegment( ii );
double segAngle = angles[ ii ];
// Exclude segments on either side of us until we reach the angle tolerance
int firstCandidate = ii + 1;
int lastCandidate = count - 1;
while( firstCandidate < count )
{
if( angleDiff( segAngle, angles[ firstCandidate ] ) < angleTolerance )
firstCandidate++;
else
break;
}
if( aOutline.IsClosed() )
{
if( ii > 0 )
lastCandidate = ii - 1;
while( lastCandidate != std::min( firstCandidate, count - 1 ) )
{
if( angleDiff( segAngle, angles[ lastCandidate ] ) < angleTolerance )
lastCandidate = ( lastCandidate == 0 ) ? count - 1 : lastCandidate - 1;
else
break;
}
}
// Now run the collision between seg and each candidate seg in the candidate range.
if( lastCandidate < ii )
lastCandidate = count - 1;
for( int jj = firstCandidate; jj <= lastCandidate; ++jj )
{
const SEG candidate = aOutline.CSegment( jj );
int actual;
if( seg.Collide( candidate, clearance + aLineWidth - epsilon, &actual ) )
{
VECTOR2I firstPoint = seg.NearestPoint( candidate );
VECTOR2I secondPoint = candidate.NearestPoint( seg );
VECTOR2I pos = ( firstPoint + secondPoint ) / 2;
if( !collisions.empty() &&
( pos - collisions.back().first ).EuclideanNorm() < clearance * 2 )
{
if( actual < collisions.back().second )
{
collisions.back().first = pos;
collisions.back().second = actual;
}
continue;
}
collisions.push_back( { pos, actual } );
}
}
}
for( std::pair<VECTOR2I, int> collision : collisions )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_CLEARANCE );
wxString msg;
msg.Printf( _( "(%s clearance %s; actual %s)" ),
aConstraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), collision.second ) );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
drce->SetItems( aParentItem );
drce->SetViolatingRule( aConstraint.GetParentRule() );
reportViolation( drce, collision.first, aLayer );
}
}
void DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testZoneLayer( ZONE* aZone, PCB_LAYER_ID aLayer,
DRC_CONSTRAINT& aConstraint )
{
int epsilon = m_board->GetDesignSettings().GetDRCEpsilon();
int clearance = aConstraint.GetValue().Min();
SHAPE_POLY_SET fill = aZone->GetFilledPolysList( aLayer )->CloneDropTriangulation();
if( aConstraint.GetSeverity() == RPT_SEVERITY_IGNORE || clearance - epsilon <= 0 )
return;
// Turn fractured fill into outlines and holes
fill.Simplify( SHAPE_POLY_SET::PM_FAST );
for( int outlineIdx = 0; outlineIdx < fill.OutlineCount(); ++outlineIdx )
{
SHAPE_LINE_CHAIN* firstOutline = &fill.Outline( outlineIdx );
// Step one: outline to outline clearance violations
for( int ii = outlineIdx + 1; ii < fill.OutlineCount(); ++ii )
{
SHAPE_LINE_CHAIN* secondOutline = &fill.Outline( ii );
for( int jj = 0; jj < secondOutline->SegmentCount(); ++jj )
{
SEG secondSeg = secondOutline->Segment( jj );
int actual;
VECTOR2I pos;
if( firstOutline->Collide( secondSeg, clearance - epsilon, &actual, &pos ) )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_CLEARANCE );
wxString msg;
msg.Printf( _( "(%s clearance %s; actual %s)" ),
aConstraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
drce->SetItems( aZone );
drce->SetViolatingRule( aConstraint.GetParentRule() );
reportViolation( drce, pos, aLayer );
}
}
if( m_drcEngine->IsCancelled() )
return;
}
// Step two: interior hole clearance violations
for( int holeIdx = 0; holeIdx < fill.HoleCount( outlineIdx ); ++holeIdx )
{
testShapeLineChain( fill.Hole( outlineIdx, holeIdx ), 0, aLayer, aZone, aConstraint );
if( m_drcEngine->IsCancelled() )
return;
}
}
}
bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* item,
SHAPE* itemShape,
PCB_LAYER_ID layer,
BOARD_ITEM* other )
{
bool testClearance = !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE );
bool testHoles = !m_drcEngine->IsErrorLimitExceeded( DRCE_HOLE_CLEARANCE );
DRC_CONSTRAINT constraint;
int clearance = 0;
int actual;
VECTOR2I pos;
std::shared_ptr<SHAPE> otherShape = other->GetEffectiveShape( layer );
if( testClearance )
{
constraint = m_drcEngine->EvalRules( PHYSICAL_CLEARANCE_CONSTRAINT, item, other, layer );
clearance = constraint.GetValue().Min();
}
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance > 0 )
{
if( itemShape->Collide( otherShape.get(), clearance, &actual, &pos ) )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_CLEARANCE );
wxString msg;
msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
drce->SetItems( item, other );
drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, pos, layer );
}
}
if( testHoles )
{
std::unique_ptr<SHAPE_SEGMENT> itemHoleShape;
std::unique_ptr<SHAPE_SEGMENT> otherHoleShape;
clearance = 0;
if( item->Type() == PCB_VIA_T )
{
PCB_VIA* via = static_cast<PCB_VIA*>( item );
pos = via->GetPosition();
if( via->GetLayerSet().Contains( layer ) )
itemHoleShape.reset( new SHAPE_SEGMENT( pos, pos, via->GetDrill() ) );
}
else if( item->Type() == PCB_PAD_T )
{
PAD* pad = static_cast<PAD*>( item );
if( pad->GetDrillSize().x )
itemHoleShape.reset( new SHAPE_SEGMENT( *pad->GetEffectiveHoleShape() ) );
}
if( other->Type() == PCB_VIA_T )
{
PCB_VIA* via = static_cast<PCB_VIA*>( other );
pos = via->GetPosition();
if( via->GetLayerSet().Contains( layer ) )
otherHoleShape.reset( new SHAPE_SEGMENT( pos, pos, via->GetDrill() ) );
}
else if( other->Type() == PCB_PAD_T )
{
PAD* pad = static_cast<PAD*>( other );
if( pad->GetDrillSize().x )
otherHoleShape.reset( new SHAPE_SEGMENT( *pad->GetEffectiveHoleShape() ) );
}
if( itemHoleShape || otherHoleShape )
{
constraint = m_drcEngine->EvalRules( PHYSICAL_HOLE_CLEARANCE_CONSTRAINT, other, item,
layer );
clearance = constraint.GetValue().Min();
}
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance > 0 )
{
if( itemHoleShape && itemHoleShape->Collide( otherShape.get(), clearance, &actual, &pos ) )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
wxString msg;
msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
drce->SetItems( item, other );
drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, pos, layer );
}
if( otherHoleShape && otherHoleShape->Collide( itemShape, clearance, &actual, &pos ) )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
wxString msg;
msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
drce->SetItems( item, other );
drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, pos, layer );
}
}
}
return !m_drcEngine->IsCancelled();
}
void DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstZones( BOARD_ITEM* aItem,
PCB_LAYER_ID aLayer )
{
for( ZONE* zone : m_zones )
{
if( !zone->GetLayerSet().test( aLayer ) )
continue;
if( aItem->GetBoundingBox().Intersects( zone->GetCachedBoundingBox() ) )
{
bool testClearance = !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE );
bool testHoles = !m_drcEngine->IsErrorLimitExceeded( DRCE_HOLE_CLEARANCE );
if( !testClearance && !testHoles )
return;
DRC_RTREE* zoneTree = m_board->m_CopperZoneRTrees[ zone ].get();
EDA_RECT itemBBox = aItem->GetBoundingBox();
DRC_CONSTRAINT constraint;
bool colliding;
int clearance = -1;
int actual;
VECTOR2I pos;
if( testClearance )
{
constraint = m_drcEngine->EvalRules( PHYSICAL_CLEARANCE_CONSTRAINT, aItem, zone,
aLayer );
clearance = constraint.GetValue().Min();
}
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance > 0 )
{
std::shared_ptr<SHAPE> itemShape = aItem->GetEffectiveShape( aLayer );
if( aItem->Type() == PCB_PAD_T )
{
PAD* pad = static_cast<PAD*>( aItem );
if( !pad->FlashLayer( aLayer ) )
{
if( pad->GetDrillSize().x == 0 && pad->GetDrillSize().y == 0 )
continue;
const SHAPE_SEGMENT* hole = pad->GetEffectiveHoleShape();
int size = hole->GetWidth();
// Note: drill size represents finish size, which means the actual hole
// size is the plating thickness larger.
if( pad->GetAttribute() == PAD_ATTRIB::PTH )
size += m_board->GetDesignSettings().GetHolePlatingThickness();
itemShape = std::make_shared<SHAPE_SEGMENT>( hole->GetSeg(), size );
}
}
if( zoneTree )
{
colliding = zoneTree->QueryColliding( itemBBox, itemShape.get(), aLayer,
clearance, &actual, &pos );
}
else
{
colliding = zone->Outline()->Collide( itemShape.get(), clearance, &actual,
&pos );
}
if( colliding )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_CLEARANCE );
wxString msg;
msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
drce->SetItems( aItem, zone );
drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, pos, aLayer );
}
}
if( testHoles && ( aItem->Type() == PCB_VIA_T || aItem->Type() == PCB_PAD_T ) )
{
std::unique_ptr<SHAPE_SEGMENT> holeShape;
if( aItem->Type() == PCB_VIA_T )
{
PCB_VIA* via = static_cast<PCB_VIA*>( aItem );
pos = via->GetPosition();
if( via->GetLayerSet().Contains( aLayer ) )
holeShape.reset( new SHAPE_SEGMENT( pos, pos, via->GetDrill() ) );
}
else if( aItem->Type() == PCB_PAD_T )
{
PAD* pad = static_cast<PAD*>( aItem );
if( pad->GetDrillSize().x )
holeShape.reset( new SHAPE_SEGMENT( *pad->GetEffectiveHoleShape() ) );
}
if( holeShape )
{
constraint = m_drcEngine->EvalRules( PHYSICAL_HOLE_CLEARANCE_CONSTRAINT, aItem,
zone, aLayer );
clearance = constraint.GetValue().Min();
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE
&& clearance > 0
&& zoneTree->QueryColliding( itemBBox, holeShape.get(), aLayer,
clearance, &actual, &pos ) )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
wxString msg;
msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
drce->SetItems( aItem, zone );
drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, pos, aLayer );
}
}
}
}
if( m_drcEngine->IsCancelled() )
return;
}
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE> dummy;
}

700
pcbnew/drc/drc_test_provider_solder_mask.cpp
View File

@ -1,700 +0,0 @@
/*
* This program source code file is part of KiCad, a free EDA CAD application.
*
* Copyright (C) 2004-2022 KiCad Developers.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you may find one here:
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
* or you may search the http://www.gnu.org website for the version 2 license,
* or you may write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
#include <common.h>
#include <board_design_settings.h>
#include <board_connected_item.h>
#include <footprint.h>
#include <pad.h>
#include <pcb_track.h>
#include <zone.h>
#include <geometry/seg.h>
#include <drc/drc_engine.h>
#include <drc/drc_item.h>
#include <drc/drc_rule.h>
#include <drc/drc_test_provider_clearance_base.h>
#include <drc/drc_rtree.h>
/*
Solder mask tests. Checks for silkscreen which is clipped by mask openings and for bridges
between mask apertures with different nets.
Errors generated:
- DRCE_SILK_CLEARANCE
- DRCE_SOLDERMASK_BRIDGE
*/
class DRC_TEST_PROVIDER_SOLDER_MASK : public ::DRC_TEST_PROVIDER
{
public:
DRC_TEST_PROVIDER_SOLDER_MASK ():
m_board( nullptr ),
m_webWidth( 0 ),
m_maxError( 0 ),
m_largestClearance( 0 )
{
m_bridgeRule.m_Name = _( "board setup solder mask min width" );
}
virtual ~DRC_TEST_PROVIDER_SOLDER_MASK()
{
}
virtual bool Run() override;
virtual const wxString GetName() const override
{
return wxT( "solder_mask_issues" );
};
virtual const wxString GetDescription() const override
{
return wxT( "Tests for silkscreen being clipped by solder mask and copper being exposed "
"by mask apertures of other nets" );
}
private:
void addItemToRTrees( BOARD_ITEM* item );
void buildRTrees();
void testSilkToMaskClearance();
void testMaskBridges();
void testItemAgainstItems( BOARD_ITEM* aItem, const EDA_RECT& aItemBBox,
PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer );
void testMaskItemAgainstZones( BOARD_ITEM* item, const EDA_RECT& itemBBox,
PCB_LAYER_ID refLayer, PCB_LAYER_ID targetLayer );
private:
DRC_RULE m_bridgeRule;
BOARD* m_board;
int m_webWidth;
int m_maxError;
int m_largestClearance;
std::unique_ptr<DRC_RTREE> m_tesselatedTree;
std::unique_ptr<DRC_RTREE> m_itemTree;
std::vector<ZONE*> m_copperZones;
std::map< std::tuple<BOARD_ITEM*, BOARD_ITEM*, PCB_LAYER_ID>, int> m_checkedPairs;
// Shapes used to define solder mask apertures don't have nets, so we assign them the
// first net that bridges their aperture (after which any other nets will generate
// violations).
std::map< std::pair<BOARD_ITEM*, PCB_LAYER_ID>, int> m_maskApertureNetMap;
};
void DRC_TEST_PROVIDER_SOLDER_MASK::addItemToRTrees( BOARD_ITEM* item )
{
ZONE* solderMask = m_board->m_SolderMask;
if( item->Type() == PCB_ZONE_T || item->Type() == PCB_FP_ZONE_T )
{
ZONE* zone = static_cast<ZONE*>( item );
for( PCB_LAYER_ID layer : { F_Mask, B_Mask } )
{
if( zone->IsOnLayer( layer ) )
{
solderMask->GetFill( layer )->BooleanAdd( *zone->GetFilledPolysList( layer ),
SHAPE_POLY_SET::PM_FAST );
}
}
if( zone->IsOnCopperLayer() && !zone->GetIsRuleArea() )
m_copperZones.push_back( zone );
}
else if( item->Type() == PCB_PAD_T )
{
for( PCB_LAYER_ID layer : { F_Mask, B_Mask } )
{
if( item->IsOnLayer( layer ) )
{
PAD* pad = static_cast<PAD*>( item );
int clearance = ( m_webWidth / 2 ) + pad->GetSolderMaskExpansion();
item->TransformShapeWithClearanceToPolygon( *solderMask->GetFill( layer ), layer,
clearance, m_maxError, ERROR_OUTSIDE );
m_itemTree->Insert( item, layer, m_largestClearance );
}
}
}
else if( item->Type() == PCB_VIA_T )
{
for( PCB_LAYER_ID layer : { F_Mask, B_Mask } )
{
if( item->IsOnLayer( layer ) )
{
PCB_VIA* via = static_cast<PCB_VIA*>( item );
int clearance = ( m_webWidth / 2 ) + via->GetSolderMaskExpansion();
via->TransformShapeWithClearanceToPolygon( *solderMask->GetFill( layer ), layer,
clearance, m_maxError, ERROR_OUTSIDE );
m_itemTree->Insert( item, layer, m_largestClearance );
}
}
}
else
{
for( PCB_LAYER_ID layer : { F_Mask, B_Mask } )
{
if( item->IsOnLayer( layer ) )
{
item->TransformShapeWithClearanceToPolygon( *solderMask->GetFill( layer ),
layer, m_webWidth / 2, m_maxError,
ERROR_OUTSIDE );
m_itemTree->Insert( item, layer, m_largestClearance );
}
}
}
}
void DRC_TEST_PROVIDER_SOLDER_MASK::buildRTrees()
{
ZONE* solderMask = m_board->m_SolderMask;
LSET layers = { 4, F_Mask, B_Mask, F_Cu, B_Cu };
size_t delta = 50; // Number of tests between 2 calls to the progress bar
int count = 0;
int ii = 0;
solderMask->GetFill( F_Mask )->RemoveAllContours();
solderMask->GetFill( B_Mask )->RemoveAllContours();
m_tesselatedTree = std::make_unique<DRC_RTREE>();
m_itemTree = std::make_unique<DRC_RTREE>();
m_copperZones.clear();
// Unlikely to be correct, but better than starting at 0
m_copperZones.reserve( m_board->Zones().size() );
forEachGeometryItem( s_allBasicItems, layers,
[&]( BOARD_ITEM* item ) -> bool
{
++count;
return true;
} );
forEachGeometryItem( s_allBasicItems, layers,
[&]( BOARD_ITEM* item ) -> bool
{
if( !reportProgress( ii++, count, delta ) )
return false;
addItemToRTrees( item );
return true;
} );
solderMask->GetFill( F_Mask )->Simplify( SHAPE_POLY_SET::PM_STRICTLY_SIMPLE );
solderMask->GetFill( B_Mask )->Simplify( SHAPE_POLY_SET::PM_STRICTLY_SIMPLE );
int numSegs = GetArcToSegmentCount( m_webWidth / 2, m_maxError, FULL_CIRCLE );
solderMask->GetFill( F_Mask )->Deflate( m_webWidth / 2, numSegs );
solderMask->GetFill( B_Mask )->Deflate( m_webWidth / 2, numSegs );
solderMask->SetFillFlag( F_Mask, true );
solderMask->SetFillFlag( B_Mask, true );
solderMask->SetIsFilled( true );
solderMask->CacheTriangulation();
m_tesselatedTree->Insert( solderMask, F_Mask );
m_tesselatedTree->Insert( solderMask, B_Mask );
m_checkedPairs.clear();
}
void DRC_TEST_PROVIDER_SOLDER_MASK::testSilkToMaskClearance()
{
LSET silkLayers = { 2, F_SilkS, B_SilkS };
size_t delta = 100; // Number of tests between 2 calls to the progress bar
int count = 0;
int ii = 0;
forEachGeometryItem( s_allBasicItems, silkLayers,
[&]( BOARD_ITEM* item ) -> bool
{
++count;
return true;
} );
forEachGeometryItem( s_allBasicItems, silkLayers,
[&]( BOARD_ITEM* item ) -> bool
{
if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_CLEARANCE ) )
return false;
if( !reportProgress( ii++, count, delta ) )
return false;
if( isInvisibleText( item ) )
return true;
for( PCB_LAYER_ID layer : silkLayers.Seq() )
{
if( !item->IsOnLayer( layer ) )
continue;
EDA_RECT itemBBox = item->GetBoundingBox();
DRC_CONSTRAINT constraint = m_drcEngine->EvalRules( SILK_CLEARANCE_CONSTRAINT,
item, nullptr, layer );
int clearance = constraint.GetValue().Min();
int actual;
VECTOR2I pos;
if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE || clearance <= 0 )
return true;
std::shared_ptr<SHAPE> itemShape = item->GetEffectiveShape( layer );
if( m_tesselatedTree->QueryColliding( itemBBox, itemShape.get(), layer,
clearance, &actual, &pos ) )
{
auto drce = DRC_ITEM::Create( DRCE_SILK_CLEARANCE );
wxString msg;
msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
drce->SetItems( item );
drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, pos, layer );
}
}
return true;
} );
}
bool isMaskAperture( BOARD_ITEM* aItem )
{
static const LSET saved( 2, F_Mask, B_Mask );
LSET maskLayers = aItem->GetLayerSet() & saved;
LSET otherLayers = aItem->GetLayerSet() & ~saved;
return maskLayers.count() > 0 && otherLayers.count() == 0;
}
bool isNullAperture( BOARD_ITEM* aItem )
{
if( aItem->Type() == PCB_PAD_T )
{
PAD* pad = static_cast<PAD*>( aItem );
if( pad->GetAttribute() == PAD_ATTRIB::NPTH
&& ( pad->GetShape() == PAD_SHAPE::CIRCLE || pad->GetShape() == PAD_SHAPE::OVAL )
&& pad->GetSize().x <= pad->GetDrillSize().x
&& pad->GetSize().y <= pad->GetDrillSize().y )
{
return true;
}
}
return false;
}
void DRC_TEST_PROVIDER_SOLDER_MASK::testItemAgainstItems( BOARD_ITEM* aItem,
const EDA_RECT& aItemBBox,
PCB_LAYER_ID aRefLayer,
PCB_LAYER_ID aTargetLayer )
{
int itemNet = -1;
if( aItem->IsConnected() )
itemNet = static_cast<BOARD_CONNECTED_ITEM*>( aItem )->GetNetCode();
PAD* pad = dynamic_cast<PAD*>( aItem );
PCB_VIA* via = dynamic_cast<PCB_VIA*>( aItem );
std::shared_ptr<SHAPE> itemShape = aItem->GetEffectiveShape( aRefLayer );
m_itemTree->QueryColliding( aItem, aRefLayer, aTargetLayer,
// Filter:
[&]( BOARD_ITEM* other ) -> bool
{
PAD* otherPad = dynamic_cast<PAD*>( other );
int otherNet = -1;
if( other->IsConnected() )
otherNet = static_cast<BOARD_CONNECTED_ITEM*>( other )->GetNetCode();
if( otherNet > 0 && otherNet == itemNet )
return false;
if( isNullAperture( other ) )
return false;
if( aItem->GetParentFootprint() && other->GetParentFootprint() )
{
int attr = static_cast<FOOTPRINT*>( aItem->GetParentFootprint() )->GetAttributes();
if( attr & FP_ALLOW_SOLDERMASK_BRIDGES )
return false;
}
if( pad && otherPad && pad->GetParent() == otherPad->GetParent() )
{
if( pad->SameLogicalPadAs( otherPad ) )
return false;
}
BOARD_ITEM* a = aItem;
BOARD_ITEM* b = other;
// store canonical order so we don't collide in both directions
// (a:b and b:a)
if( static_cast<void*>( a ) > static_cast<void*>( b ) )
std::swap( a, b );
if( m_checkedPairs.count( { a, b, aTargetLayer } ) )
{
return false;
}
else
{
m_checkedPairs[ { a, b, aTargetLayer } ] = 1;
return true;
}
},
// Visitor:
[&]( BOARD_ITEM* other ) -> bool
{
PAD* otherPad = dynamic_cast<PAD*>( other );
PCB_VIA* otherVia = dynamic_cast<PCB_VIA*>( other );
auto otherShape = other->GetEffectiveShape( aTargetLayer );
int otherNet = -1;
if( other->IsConnected() )
otherNet = static_cast<BOARD_CONNECTED_ITEM*>( other )->GetNetCode();
int actual;
VECTOR2I pos;
int clearance = 0;
if( aRefLayer == F_Mask || aRefLayer == B_Mask )
{
// Aperture-to-aperture must enforce web-min-width
clearance = m_webWidth;
}
else
{
// Copper-to-aperture uses the solder-mask-to-copper-clearance
clearance = m_board->GetDesignSettings().m_SolderMaskToCopperClearance;
}
if( pad )
clearance += pad->GetSolderMaskExpansion();
else if( via )
clearance += via->GetSolderMaskExpansion();
if( otherPad )
clearance += otherPad->GetSolderMaskExpansion();
else if( otherVia )
clearance += otherVia->GetSolderMaskExpansion();
if( itemShape->Collide( otherShape.get(), clearance, &actual, &pos ) )
{
// Simple mask apertures aren't associated with copper items, so they only
// constitute a bridge when they expose other copper items having at least
// two distinct nets. We use a map to record the first net exposed by each
// mask aperture.
if( isMaskAperture( aItem ) )
{
std::pair<BOARD_ITEM*, PCB_LAYER_ID> key = { aItem, aRefLayer };
if( m_maskApertureNetMap.count( key ) == 0 )
{
m_maskApertureNetMap[ key ] = otherNet;
// First net; no bridge yet....
return true;
}
if( m_maskApertureNetMap.at( key ) == otherNet && otherNet > 0 )
return true;
}
if( isMaskAperture( other ) )
{
std::pair<BOARD_ITEM*, PCB_LAYER_ID> key = { other, aRefLayer };
if( m_maskApertureNetMap.count( key ) == 0 )
{
m_maskApertureNetMap[ key ] = itemNet;
// First net; no bridge yet....
return true;
}
if( m_maskApertureNetMap.at( key ) == itemNet && itemNet > 0 )
return true;
}
auto drce = DRC_ITEM::Create( DRCE_SOLDERMASK_BRIDGE );
if( aTargetLayer == F_Mask )
{
drce->SetErrorMessage( _( "Front solder mask aperture bridges items with "
"different nets" ) );
}
else
{
drce->SetErrorMessage( _( "Rear solder mask aperture bridges items with "
"different nets" ) );
}
drce->SetItems( aItem, other );
drce->SetViolatingRule( &m_bridgeRule );
reportViolation( drce, pos, aTargetLayer );
}
return !m_drcEngine->IsCancelled();
},
m_largestClearance );
}
void DRC_TEST_PROVIDER_SOLDER_MASK::testMaskItemAgainstZones( BOARD_ITEM* aItem,
const EDA_RECT& aItemBBox,
PCB_LAYER_ID aMaskLayer,
PCB_LAYER_ID aTargetLayer )
{
for( ZONE* zone : m_copperZones )
{
if( !zone->GetLayerSet().test( aTargetLayer ) )
continue;
int zoneNet = zone->GetNetCode();
if( aItem->IsConnected() )
{
BOARD_CONNECTED_ITEM* connectedItem = static_cast<BOARD_CONNECTED_ITEM*>( aItem );
if( zoneNet == connectedItem->GetNetCode() && zoneNet > 0 )
continue;
}
if( aItem->GetBoundingBox().Intersects( zone->GetCachedBoundingBox() ) )
{
DRC_RTREE* zoneTree = m_board->m_CopperZoneRTrees[ zone ].get();
int clearance = m_board->GetDesignSettings().m_SolderMaskToCopperClearance;
int actual;
VECTOR2I pos;
std::shared_ptr<SHAPE> itemShape = aItem->GetEffectiveShape( aMaskLayer );
if( aItem->Type() == PCB_PAD_T )
{
PAD* pad = static_cast<PAD*>( aItem );
clearance += pad->GetSolderMaskExpansion();
}
else if( aItem->Type() == PCB_VIA_T )
{
PCB_VIA* via = static_cast<PCB_VIA*>( aItem );
clearance += via->GetSolderMaskExpansion();
}
if( zoneTree && zoneTree->QueryColliding( aItemBBox, itemShape.get(), aTargetLayer,
clearance, &actual, &pos ) )
{
if( isMaskAperture( aItem ) )
{
// Simple mask apertures aren't associated with copper items, so they only
// constitute a bridge when they expose other copper items having at least
// two distinct nets. We use a map to record the first net exposed by each
// mask aperture.
std::pair<BOARD_ITEM*, PCB_LAYER_ID> key = { aItem, aMaskLayer };
if( m_maskApertureNetMap.count( key ) == 0 )
{
m_maskApertureNetMap[ key ] = zoneNet;
// First net; no bridge yet....
continue;
}
if( m_maskApertureNetMap.at( key ) == zoneNet && zoneNet > 0 )
continue;
}
auto drce = DRC_ITEM::Create( DRCE_SOLDERMASK_BRIDGE );
if( aMaskLayer == F_Mask )
{
drce->SetErrorMessage( _( "Front solder mask aperture bridges items with "
"different nets" ) );
}
else
{
drce->SetErrorMessage( _( "Rear solder mask aperture bridges items with "
"different nets" ) );
}
drce->SetItems( aItem, zone );
drce->SetViolatingRule( &m_bridgeRule );
reportViolation( drce, pos, aTargetLayer );
}
}
if( m_drcEngine->IsCancelled() )
return;
}
}
void DRC_TEST_PROVIDER_SOLDER_MASK::testMaskBridges()
{
LSET copperAndMaskLayers = { 4, F_Mask, B_Mask, F_Cu, B_Cu };
size_t delta = 50; // Number of tests between 2 calls to the progress bar
int count = 0;
int ii = 0;
forEachGeometryItem( s_allBasicItemsButZones, copperAndMaskLayers,
[&]( BOARD_ITEM* item ) -> bool
{
++count;
return true;
} );
forEachGeometryItem( s_allBasicItemsButZones, copperAndMaskLayers,
[&]( BOARD_ITEM* item ) -> bool
{
if( m_drcEngine->IsErrorLimitExceeded( DRCE_SOLDERMASK_BRIDGE ) )
return false;
if( !reportProgress( ii++, count, delta ) )
return false;
EDA_RECT itemBBox = item->GetBoundingBox();
if( item->IsOnLayer( F_Mask ) && !isNullAperture( item ) )
{
// Test for aperture-to-aperture collisions
testItemAgainstItems( item, itemBBox, F_Mask, F_Mask );
// Test for aperture-to-zone collisions
testMaskItemAgainstZones( item, itemBBox, F_Mask, F_Cu );
}
else if( item->IsOnLayer( F_Cu ) )
{
// Test for copper-item-to-aperture collisions
testItemAgainstItems( item, itemBBox, F_Cu, F_Mask );
}
if( item->IsOnLayer( B_Mask ) && !isNullAperture( item ) )
{
// Test for aperture-to-aperture collisions
testItemAgainstItems( item, itemBBox, B_Mask, B_Mask );
// Test for aperture-to-zone collisions
testMaskItemAgainstZones( item, itemBBox, B_Mask, B_Cu );
}
else if( item->IsOnLayer( B_Cu ) )
{
// Test for copper-item-to-aperture collisions
testItemAgainstItems( item, itemBBox, B_Cu, B_Mask );
}
return true;
} );
}
bool DRC_TEST_PROVIDER_SOLDER_MASK::Run()
{
if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_CLEARANCE )
&& m_drcEngine->IsErrorLimitExceeded( DRCE_SOLDERMASK_BRIDGE ) )
{
reportAux( wxT( "Solder mask violations ignored. Tests not run." ) );
return true; // continue with other tests
}
m_board = m_drcEngine->GetBoard();
m_webWidth = m_board->GetDesignSettings().m_SolderMaskMinWidth;
m_maxError = m_board->GetDesignSettings().m_MaxError;
m_largestClearance = 0;
for( FOOTPRINT* footprint : m_board->Footprints() )
{
for( PAD* pad : footprint->Pads() )
m_largestClearance = std::max( m_largestClearance, pad->GetSolderMaskExpansion() );
}
// Order is important here: m_webWidth must be added in before m_largestClearance is maxed
// with the various SILK_CLEARANCE_CONSTRAINTS.
m_largestClearance += m_largestClearance + m_webWidth;
DRC_CONSTRAINT worstClearanceConstraint;
if( m_drcEngine->QueryWorstConstraint( SILK_CLEARANCE_CONSTRAINT, worstClearanceConstraint ) )
m_largestClearance = std::max( m_largestClearance, worstClearanceConstraint.m_Value.Min() );
reportAux( wxT( "Worst clearance : %d nm" ), m_largestClearance );
if( !reportPhase( _( "Building solder mask..." ) ) )
return false; // DRC cancelled
m_checkedPairs.clear();
m_maskApertureNetMap.clear();
buildRTrees();
if( !reportPhase( _( "Checking solder mask to silk clearance..." ) ) )
return false; // DRC cancelled
testSilkToMaskClearance();
if( !reportPhase( _( "Checking solder mask web integrity..." ) ) )
return false; // DRC cancelled
testMaskBridges();
reportRuleStatistics();
return !m_drcEngine->IsCancelled();
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_SOLDER_MASK> dummy;
}

319
pcbnew/drc/drc_test_provider_text_dims.cpp
View File

@ -1,319 +0,0 @@
/*
* This program source code file is part of KiCad, a free EDA CAD application.
*
* Copyright (C) 2021-2022 KiCad Developers.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you may find one here:
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
* or you may search the http://www.gnu.org website for the version 2 license,
* or you may write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
#include <macros.h>
#include <pcb_text.h>
#include <pcb_textbox.h>
#include <fp_text.h>
#include <fp_textbox.h>
#include <drc/drc_engine.h>
#include <drc/drc_item.h>
#include <drc/drc_rule.h>
#include <drc/drc_test_provider.h>
#include <font/font.h>
/*
Text dimensions tests.
Errors generated:
- DRCE_TEXT_HEIGHT
- DRCE_TEXT_THICKNESS
*/
class DRC_TEST_PROVIDER_TEXT_DIMS : public DRC_TEST_PROVIDER
{
public:
DRC_TEST_PROVIDER_TEXT_DIMS()
{
}
virtual ~DRC_TEST_PROVIDER_TEXT_DIMS()
{
}
virtual bool Run() override;
virtual const wxString GetName() const override
{
return wxT( "text_dimensions" );
};
virtual const wxString GetDescription() const override
{
return wxT( "Tests text height and thickness" );
}
};
bool DRC_TEST_PROVIDER_TEXT_DIMS::Run()
{
const int delta = 100; // This is the number of tests between 2 calls to the progress bar
int count = 0;
int ii = 0;
if( m_drcEngine->IsErrorLimitExceeded( DRCE_TEXT_HEIGHT )
&& m_drcEngine->IsErrorLimitExceeded( DRCE_TEXT_THICKNESS ) )
{
reportAux( wxT( "Text dimension violations ignored. Tests not run." ) );
return true; // continue with other tests
}
if( !m_drcEngine->HasRulesForConstraintType( TEXT_HEIGHT_CONSTRAINT )
&& !m_drcEngine->HasRulesForConstraintType( TEXT_THICKNESS_CONSTRAINT ) )
{
reportAux( wxT( "No text height or text thickness constraints found. Tests not run." ) );
return true; // continue with other tests
}
if( !reportPhase( _( "Checking text dimensions..." ) ) )
return false; // DRC cancelled
auto checkTextHeight =
[&]( BOARD_ITEM* item, EDA_TEXT* text ) -> bool
{
if( m_drcEngine->IsErrorLimitExceeded( DRCE_TEXT_HEIGHT ) )
return false;
DRC_CONSTRAINT constraint = m_drcEngine->EvalRules( TEXT_HEIGHT_CONSTRAINT, item,
nullptr, item->GetLayer() );
if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
return true;
int actualHeight = text->GetTextSize().y;
if( constraint.Value().HasMin() && actualHeight < constraint.Value().Min() )
{
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_TEXT_HEIGHT );
wxString msg;
msg.Printf( _( "(%s min height %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), constraint.Value().Min() ),
MessageTextFromValue( userUnits(), actualHeight ) );
drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + msg );
drcItem->SetItems( item );
drcItem->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drcItem, item->GetPosition(), item->GetLayer() );
}
if( constraint.Value().HasMax() && actualHeight > constraint.Value().Max() )
{
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_TEXT_HEIGHT );
wxString msg;
msg.Printf( _( "(%s max height %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), constraint.Value().Max() ),
MessageTextFromValue( userUnits(), actualHeight ) );
drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + msg );
drcItem->SetItems( item );
drcItem->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drcItem, item->GetPosition(), item->GetLayer() );
}
return true;
};
auto checkTextThickness =
[&]( BOARD_ITEM* item, EDA_TEXT* text ) -> bool
{
DRC_CONSTRAINT constraint = m_drcEngine->EvalRules( TEXT_THICKNESS_CONSTRAINT, item,
nullptr, item->GetLayer() );
if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
return true;
KIFONT::FONT* font = text->GetDrawFont();
if( font->IsOutline() )
{
if( !constraint.Value().HasMin() )
return true;
auto* glyphs = text->GetRenderCache( text->GetShownText() );
bool collapsedStroke = false;
bool collapsedArea = false;
for( const std::unique_ptr<KIFONT::GLYPH>& glyph : *glyphs )
{
auto outlineGlyph = static_cast<KIFONT::OUTLINE_GLYPH*>( glyph.get() );
int outlineCount = outlineGlyph->OutlineCount();
int holeCount = 0;
if( outlineCount == 0 )
continue; // ignore spaces
for( ii = 0; ii < outlineCount; ++ii )
holeCount += outlineGlyph->HoleCount( ii );
SHAPE_POLY_SET poly = outlineGlyph->CloneDropTriangulation();
poly.Deflate( constraint.Value().Min() / 2, 16 );
poly.Simplify( SHAPE_POLY_SET::PM_FAST );
int resultingOutlineCount = poly.OutlineCount();
int resultingHoleCount = 0;
for( ii = 0; ii < resultingOutlineCount; ++ii )
resultingHoleCount += poly.HoleCount( ii );
if( ( resultingOutlineCount != outlineCount )
|| ( resultingHoleCount != holeCount ) )
{
collapsedStroke = true;
break;
}
double glyphArea = outlineGlyph->Area();
if( glyphArea == 0 )
continue;
poly.Inflate( constraint.Value().Min() / 2, 16 );
poly.Simplify( SHAPE_POLY_SET::PM_FAST );
double resultingGlyphArea = poly.Area();
if( ( std::abs( resultingGlyphArea - glyphArea ) / glyphArea ) > 0.1 )
{
collapsedArea = true;
break;
}
}
if( collapsedStroke || collapsedArea )
{
auto drcItem = DRC_ITEM::Create( DRCE_TEXT_THICKNESS );
wxString msg;
msg = _( "(TrueType font characters with insufficient stroke weight)" );
drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + msg );
drcItem->SetItems( item );
drcItem->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drcItem, item->GetPosition(), item->GetLayer() );
}
}
else
{
int actualThickness = text->GetEffectiveTextPenWidth();
if( constraint.Value().HasMin() && actualThickness < constraint.Value().Min() )
{
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_TEXT_THICKNESS );
wxString msg;
msg.Printf( _( "(%s min thickness %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), constraint.Value().Min() ),
MessageTextFromValue( userUnits(), actualThickness ) );
drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + msg );
drcItem->SetItems( item );
drcItem->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drcItem, item->GetPosition(), item->GetLayer() );
}
if( constraint.Value().HasMax() && actualThickness > constraint.Value().Max() )
{
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_TEXT_THICKNESS );
wxString msg;
msg.Printf( _( "(%s max thickness %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), constraint.Value().Max() ),
MessageTextFromValue( userUnits(), actualThickness ) );
drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + msg );
drcItem->SetItems( item );
drcItem->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drcItem, item->GetPosition(), item->GetLayer() );
}
}
return true;
};
static const std::vector<KICAD_T> itemTypes = { PCB_TEXT_T, PCB_FP_TEXT_T,
PCB_TEXTBOX_T, PCB_FP_TEXTBOX_T };
forEachGeometryItem( itemTypes, LSET::AllLayersMask(),
[&]( BOARD_ITEM* item ) -> bool
{
++count;
return true;
} );
forEachGeometryItem( itemTypes, LSET::AllLayersMask(),
[&]( BOARD_ITEM* item ) -> bool
{
if( !reportProgress( ii++, count, delta ) )
return false;
EDA_TEXT* text = nullptr;
int strikes = 0;
switch( item->Type() )
{
case PCB_TEXT_T: text = static_cast<PCB_TEXT*>( item ); break;
case PCB_TEXTBOX_T: text = static_cast<PCB_TEXTBOX*>( item ); break;
case PCB_FP_TEXT_T: text = static_cast<FP_TEXT*>( item ); break;
case PCB_FP_TEXTBOX_T: text = static_cast<FP_TEXTBOX*>( item ); break;
default: UNIMPLEMENTED_FOR( item->GetClass() ); break;
}
if( !text || !text->IsVisible() )
return true;
if( m_drcEngine->IsErrorLimitExceeded( DRCE_TEXT_THICKNESS ) )
strikes++;
else
checkTextThickness( item, text );
if( m_drcEngine->IsErrorLimitExceeded( DRCE_TEXT_HEIGHT ) )
strikes++;
else
checkTextHeight( item, text );
if( strikes >= 2 )
return false;
return true;
} );
reportRuleStatistics();
return !m_drcEngine->IsCancelled();
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_TEXT_DIMS> dummy;
}

203
pcbnew/drc/drc_test_provider_zone_connections.cpp
View File

@ -1,203 +0,0 @@
/*
* This program source code file is part of KiCad, a free EDA CAD application.
*
* Copyright (C) 2021-2022 KiCad Developers.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you may find one here:
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
* or you may search the http://www.gnu.org website for the version 2 license,
* or you may write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
#include <board.h>
#include <board_design_settings.h>
#include <connectivity/connectivity_data.h>
#include <zone.h>
#include <footprint.h>
#include <pad.h>
#include <pcb_track.h>
#include <geometry/shape_line_chain.h>
#include <geometry/shape_poly_set.h>
#include <drc/drc_rule.h>
#include <drc/drc_item.h>
#include <drc/drc_test_provider.h>
/*
This loads some rule resolvers for the ZONE_FILLER, and checks that pad thermal relief
connections have at least the required number of spokes.
Errors generated:
- DRCE_STARVED_THERMAL
*/
class DRC_TEST_PROVIDER_ZONE_CONNECTIONS : public DRC_TEST_PROVIDER
{
public:
DRC_TEST_PROVIDER_ZONE_CONNECTIONS()
{
}
virtual ~DRC_TEST_PROVIDER_ZONE_CONNECTIONS()
{
}
virtual bool Run() override;
virtual const wxString GetName() const override
{
return wxT( "zone connections" );
};
virtual const wxString GetDescription() const override
{
return wxT( "Checks thermal reliefs for a sufficient number of connecting spokes" );
}
};
bool DRC_TEST_PROVIDER_ZONE_CONNECTIONS::Run()
{
const int delta = 5; // This is the number of tests between 2 calls to the progress bar
int ii = 0;
BOARD* board = m_drcEngine->GetBoard();
BOARD_DESIGN_SETTINGS& bds = board->GetDesignSettings();
std::shared_ptr<CONNECTIVITY_DATA> connectivity = board->GetConnectivity();
DRC_CONSTRAINT constraint;
std::vector<ZONE*> zones;
if( !reportPhase( _( "Checking thermal reliefs..." ) ) )
return false; // DRC cancelled
for( ZONE* zone : board->Zones() )
zones.push_back( zone );
for( FOOTPRINT* footprint : board->Footprints() )
{
for( ZONE* zone : footprint->Zones() )
zones.push_back( zone );
}
for( ZONE* zone : zones )
{
if( !reportProgress( ii++, zones.size(), delta ) )
return false;
for( PCB_LAYER_ID layer : zone->GetLayerSet().Seq() )
{
const std::shared_ptr<SHAPE_POLY_SET>& zoneFill = zone->GetFilledPolysList( layer );
for( FOOTPRINT* footprint : board->Footprints() )
{
for( PAD* pad : footprint->Pads() )
{
if( m_drcEngine->IsErrorLimitExceeded( DRCE_STARVED_THERMAL ) )
return true;
if( m_drcEngine->IsCancelled() )
return false;
// Quick tests for "connected":
//
if( !pad->FlashLayer( layer ) )
continue;
if( pad->GetNetCode() != zone->GetNetCode() || pad->GetNetCode() <= 0 )
continue;
EDA_RECT item_boundingbox = pad->GetBoundingBox();
if( !item_boundingbox.Intersects( zone->GetCachedBoundingBox() ) )
continue;
// If those passed, do a thorough test:
//
constraint = bds.m_DRCEngine->EvalZoneConnection( pad, zone, layer );
ZONE_CONNECTION conn = constraint.m_ZoneConnection;
if( conn != ZONE_CONNECTION::THERMAL )
continue;
constraint = bds.m_DRCEngine->EvalRules( MIN_RESOLVED_SPOKES_CONSTRAINT,
pad, zone, layer );
int minCount = constraint.m_Value.Min();
if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE || minCount <= 0 )
continue;
SHAPE_POLY_SET padPoly;
pad->TransformShapeWithClearanceToPolygon( padPoly, layer, 0, ARC_LOW_DEF,
ERROR_OUTSIDE );
SHAPE_LINE_CHAIN& padOutline = padPoly.Outline( 0 );
std::vector<SHAPE_LINE_CHAIN::INTERSECTION> intersections;
int spokes = 0;
for( int jj = 0; jj < zoneFill->OutlineCount(); ++jj )
padOutline.Intersect( zoneFill->Outline( jj ), intersections, true );
spokes += intersections.size() / 2;
if( spokes <= 0 )
continue;
// Now we know we're connected, so see if there are any other manual spokes
// added:
//
for( PCB_TRACK* track : connectivity->GetConnectedTracks( pad ) )
{
if( padOutline.PointInside( track->GetStart() ) )
{
if( zone->GetFilledPolysList( layer )->Collide( track->GetEnd() ) )
spokes++;
}
else if( padOutline.PointInside( track->GetEnd() ) )
{
if( zone->GetFilledPolysList( layer )->Collide( track->GetStart() ) )
spokes++;
}
}
// And finally report it if there aren't enough:
//
if( spokes < minCount )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_STARVED_THERMAL );
wxString msg;
msg.Printf( _( "(%s min spoke count %d; actual %d)" ),
constraint.GetName(),
minCount,
spokes );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
drce->SetItems( zone, pad );
drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, pad->GetPosition(), UNDEFINED_LAYER );
}
}
}
}
}
return !m_drcEngine->IsCancelled();
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_ZONE_CONNECTIONS> dummy;
}