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CADSTAR PCB: Don't create zero width tracks 

Fixes a bug in the route offsetting part of the import
that was resulting in zero-width tracks being imported.
This commit is contained in:
Roberto Fernandez Bautista 2021-10-08 20:07:21 +01:00
parent 16b61e47cd
commit 58fc4f512d
1 changed files with 18 additions and 1 deletions
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19
pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp
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@ -2187,7 +2187,8 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadNets()
// For junction points we need to find out the biggest size of the other routes connecting
// at the junction in order to correctly apply the same "route offset" operation that the
// CADSTAR post processor applies when generating Manufacturing output
// CADSTAR post processor applies when generating Manufacturing output. The only exception
// is if there is just a single route at the junction point, we use that route width
auto getJunctionSize =
[&]( NETELEMENT_ID aJptNetElemId, const NET_PCB::CONNECTION_PCB& aConnectionToIgnore ) -> int
{
@ -2200,7 +2201,9 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadNets()
if( connection.StartNode == aConnectionToIgnore.StartNode
&& connection.EndNode == aConnectionToIgnore.EndNode )
{
continue;
}
if( connection.StartNode == aJptNetElemId )
{
@ -2214,6 +2217,18 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadNets()
}
}
if( jptsize == 0 )
{
// aConnectionToIgnore is actually the only one that has a route, so lets use that
// to determine junction size
NET_PCB::ROUTE_VERTEX vertex = aConnectionToIgnore.Route.RouteVertices.front();
if( aConnectionToIgnore.EndNode == aJptNetElemId )
vertex = aConnectionToIgnore.Route.RouteVertices.back();
jptsize = getKiCadLength( vertex.RouteWidth );
}
return jptsize;
};
@ -3743,7 +3758,9 @@ double CADSTAR_PCB_ARCHIVE_LOADER::getPolarAngle( const wxPoint& aPoint )
NETINFO_ITEM* CADSTAR_PCB_ARCHIVE_LOADER::getKiCadNet( const NET_ID& aCadstarNetID )
{
if( aCadstarNetID.IsEmpty() )
{
return nullptr;
}
else if( m_netMap.find( aCadstarNetID ) != m_netMap.end() )
{
return m_netMap.at( aCadstarNetID );