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Custom rule severities. 

ADDED severity token to custom rule syntax.  Each rule can now define
its own severity.

Fixes https://gitlab.com/kicad/code/kicad/issues/6148
This commit is contained in:
Jeff Young 2021-09-05 16:06:12 +01:00
parent fcb013e5d7
commit 5f37c2b247
51 changed files with 4624 additions and 590 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
common/drc_rules.keywords
View File

@ -9,12 +9,15 @@ diff_pair_gap
diff_pair_uncoupled
disallow
edge_clearance
error
exclusion
footprint
graphic
hole
hole_clearance
hole_size
hole_to_hole
ignore
inner
layer
length
@ -31,6 +34,7 @@ outer
pad
pth
rule
severity
silk_clearance
skew
solid
@ -46,5 +50,6 @@ version
via
via_count
via_diameter
warning
zone
zone_connection

46
common/rc_item.cpp
View File

@ -83,10 +83,11 @@ wxString RC_ITEM::ShowReport( EDA_UNITS aUnits, SEVERITY aSeverity,
switch( aSeverity )
{
case RPT_SEVERITY_ERROR: severity = wxT( "Severity: error" ); break;
case RPT_SEVERITY_WARNING: severity = wxT( "Severity: warning" ); break;
case RPT_SEVERITY_ACTION: severity = wxT( "Severity: action" ); break;
case RPT_SEVERITY_INFO: severity = wxT( "Severity: info" ); break;
case RPT_SEVERITY_ERROR: severity = wxT( "Severity: error" ); break;
case RPT_SEVERITY_WARNING: severity = wxT( "Severity: warning" ); break;
case RPT_SEVERITY_ACTION: severity = wxT( "Severity: action" ); break;
case RPT_SEVERITY_INFO: severity = wxT( "Severity: info" ); break;
case RPT_SEVERITY_EXCLUSION: severity = wxT( "Severity: exclusion" ); break;
default: ;
};
@ -349,20 +350,25 @@ void RC_TREE_MODEL::GetValue( wxVariant& aVariant,
{
wxString prefix;
if( rcItem->GetParent() && rcItem->GetParent()->IsExcluded() )
prefix = _( "Excluded " );
switch( m_editFrame->GetSeverity( rcItem->GetErrorCode() ) )
if( rcItem->GetParent() )
{
case RPT_SEVERITY_ERROR: prefix += _( "Error: " ); break;
case RPT_SEVERITY_WARNING: prefix += _( "Warning: " ); break;
SEVERITY severity = rcItem->GetParent()->GetSeverity();
case RPT_SEVERITY_EXCLUSION:
case RPT_SEVERITY_UNDEFINED:
case RPT_SEVERITY_INFO:
case RPT_SEVERITY_ACTION:
case RPT_SEVERITY_IGNORE:
break;
if( severity == RPT_SEVERITY_EXCLUSION )
{
if( m_editFrame->GetSeverity( rcItem->GetErrorCode() ) == RPT_SEVERITY_WARNING )
prefix = _( "Excluded warning: " );
else
prefix = _( "Excluded error: " );
}
else if( severity == RPT_SEVERITY_WARNING )
{
prefix = _( "Warning: " );
}
else
{
prefix = _( "Error: " );
}
}
aVariant = prefix + rcItem->GetErrorMessage();
@ -416,7 +422,8 @@ bool RC_TREE_MODEL::GetAttr( wxDataViewItem const& aItem,
ret = true;
}
if( node->m_RcItem->GetParent() && node->m_RcItem->GetParent()->IsExcluded() )
if( node->m_RcItem->GetParent()
&& node->m_RcItem->GetParent()->GetSeverity() == RPT_SEVERITY_EXCLUSION )
{
wxColour textColour = wxSystemSettings::GetColour( wxSYS_COLOUR_LISTBOXTEXT );
double brightness = KIGFX::COLOR4D( textColour ).GetBrightness();
@ -493,7 +500,10 @@ void RC_TREE_MODEL::DeleteItems( bool aCurrentOnly, bool aIncludeExclusions, boo
{
std::shared_ptr<RC_ITEM> rcItem = m_rcItemsProvider->GetItem( i );
MARKER_BASE* marker = rcItem->GetParent();
bool excluded = marker ? marker->IsExcluded() : false;
bool excluded = false;
if( marker && marker->GetSeverity() == RPT_SEVERITY_EXCLUSION )
excluded = true;
if( aCurrentOnly && itemDeleted && lastGood >= 0 )
break;

2
include/marker_base.h
View File

@ -95,6 +95,8 @@ public:
bool IsExcluded() const { return m_excluded; }
void SetExcluded( bool aExcluded ) { m_excluded = aExcluded; }
virtual SEVERITY GetSeverity() const { return RPT_SEVERITY_UNDEFINED; }
/**
* @return the #RC_ITEM held within this marker so that its interface may be used.
*/

8
include/widgets/report_severity.h
View File

@ -18,11 +18,11 @@
*/
#ifndef _REPORT_SEVERITY_H_
#define _REPORT_SEVERITY_H_
#ifndef REPORT_SEVERITY_H
#define REPORT_SEVERITY_H
// Note: On windows, SEVERITY_ERROR collides with a system declaration,
// so we used RPT_SEVERITY _xxx instead of SEVERITY _xxx
// so we used RPT_SEVERITY_xxx instead of SEVERITY_xxx
enum SEVERITY {
RPT_SEVERITY_UNDEFINED = 0x00,
RPT_SEVERITY_INFO = 0x01,
@ -33,4 +33,4 @@ enum SEVERITY {
RPT_SEVERITY_IGNORE = 0x20
};
#endif // _REPORT_SEVERITY_H_
#endif // REPORT_SEVERITY_H

4
pcbnew/board.cpp
View File

@ -823,8 +823,8 @@ void BOARD::DeleteMARKERs( bool aWarningsAndErrors, bool aExclusions )
for( PCB_MARKER* marker : m_markers )
{
if( ( marker->IsExcluded() && aExclusions )
|| ( !marker->IsExcluded() && aWarningsAndErrors ) )
if( ( marker->GetSeverity() == RPT_SEVERITY_EXCLUSION && aExclusions )
|| ( marker->GetSeverity() != RPT_SEVERITY_EXCLUSION && aWarningsAndErrors ) )
{
delete marker;
}

7
pcbnew/dialogs/dialog_drc.cpp
View File

@ -822,7 +822,7 @@ void DIALOG_DRC::ExcludeMarker()
RC_TREE_NODE* node = RC_TREE_MODEL::ToNode( m_markerDataView->GetCurrentItem() );
PCB_MARKER* marker = dynamic_cast<PCB_MARKER*>( node->m_RcItem->GetParent() );
if( marker && !marker->IsExcluded() )
if( marker && !marker->GetSeverity() == RPT_SEVERITY_EXCLUSION )
{
marker->SetExcluded( true );
m_frame->GetCanvas()->GetView()->Update( marker );
@ -876,7 +876,10 @@ bool DIALOG_DRC::writeReport( const wxString& aFullFileName )
for( int i = 0; i < count; ++i )
{
const std::shared_ptr<RC_ITEM>& item = m_markersProvider->GetItem( i );
SEVERITY severity = bds.GetSeverity( item->GetErrorCode() );
SEVERITY severity = item->GetParent()->GetSeverity();
if( severity == RPT_SEVERITY_EXCLUSION )
severity = bds.GetSeverity( item->GetErrorCode() );
fprintf( fp, "%s", TO_UTF8( item->ShowReport( units, severity, itemMap ) ) );
}

2
pcbnew/dialogs/dialog_plot.cpp
View File

@ -240,7 +240,7 @@ void DIALOG_PLOT::reInitDialog()
for( PCB_MARKER* marker : m_parent->GetBoard()->Markers() )
{
if( marker->IsExcluded() )
if( marker->GetSeverity() == RPT_SEVERITY_EXCLUSION )
exclusions++;
else
knownViolations++;

10
pcbnew/dialogs/panel_setup_rules.cpp
View File

@ -275,7 +275,8 @@ void PANEL_SETUP_RULES::onScintillaCharAdded( wxStyledTextEvent &aEvent )
{
tokens = "condition|"
"constraint|"
"layer";
"layer|"
"severity";
}
else if( sexprs.top() == "constraint" )
{
@ -345,6 +346,13 @@ void PANEL_SETUP_RULES::onScintillaCharAdded( wxStyledTextEvent &aEvent )
{
tokens = "warning|error|ignore|exclusion";
}
else if( sexprs.top() == "severity" )
{
tokens = "error "
"exclusion "
"ignore "
"warning";
}
}
else if( context == STRING && !sexprs.empty() && sexprs.top() == "condition" )
{

11
pcbnew/dialogs/panel_setup_rules_help.md
View File

@ -15,6 +15,8 @@
(layer "<layer_name>")
(severity <severity_name>)
<br>
@ -69,6 +71,15 @@ Note: `clearance` and `hole_clearance` rules are not run against items of the sa
<br>
### Severity Names
* warning
* error
* exclusion
* ignore
<br>
### Examples
(version 1)

72
pcbnew/drc/drc_engine.cpp
View File

@ -42,6 +42,11 @@
#include <geometry/shape_null.h>
// wxListBox's performance degrades horrifically with very large datasets. It's not clear
// they're useful to the user anyway.
#define ERROR_LIMIT_MAX 199
void drcPrintDebugMessage( int level, const wxString& msg, const char *function, int line )
{
wxString valueStr;
@ -73,7 +78,7 @@ DRC_ENGINE::DRC_ENGINE( BOARD* aBoard, BOARD_DESIGN_SETTINGS *aSettings ) :
m_errorLimits.resize( DRCE_LAST + 1 );
for( int ii = DRCE_FIRST; ii <= DRCE_LAST; ++ii )
m_errorLimits[ ii ] = INT_MAX;
m_errorLimits[ ii ] = ERROR_LIMIT_MAX;
}
@ -502,43 +507,28 @@ void DRC_ENGINE::compileRules()
{
ReportAux( wxString::Format( "Compiling Rules (%d rules): ", (int) m_rules.size() ) );
std::set<DRC_CONSTRAINT_T> constraintTypes;
for( DRC_TEST_PROVIDER* provider : m_testProviders )
for( DRC_RULE* rule : m_rules )
{
for( DRC_CONSTRAINT_T constraintType : provider->GetConstraintTypes() )
constraintTypes.insert( constraintType );
}
DRC_RULE_CONDITION* condition = nullptr;
for( DRC_CONSTRAINT_T constraintType : constraintTypes )
{
if( m_constraintMap.find( constraintType ) == m_constraintMap.end() )
m_constraintMap[ constraintType ] = new std::vector<DRC_ENGINE_CONSTRAINT*>();
for( DRC_RULE* rule : m_rules )
if( rule->m_Condition && !rule->m_Condition->GetExpression().IsEmpty() )
{
DRC_RULE_CONDITION* condition = nullptr;
condition = rule->m_Condition;
condition->Compile( nullptr );
}
if( rule->m_Condition && !rule->m_Condition->GetExpression().IsEmpty() )
{
condition = rule->m_Condition;
condition->Compile( nullptr, 0, 0 ); // fixme
}
for( const DRC_CONSTRAINT& constraint : rule->m_Constraints )
{
if( !m_constraintMap.count( constraint.m_Type ) )
m_constraintMap[ constraint.m_Type ] = new std::vector<DRC_ENGINE_CONSTRAINT*>();
for( const DRC_CONSTRAINT& constraint : rule->m_Constraints )
{
if( constraint.m_Type == constraintType )
{
DRC_ENGINE_CONSTRAINT* engineConstraint = new DRC_ENGINE_CONSTRAINT;
DRC_ENGINE_CONSTRAINT* engineConstraint = new DRC_ENGINE_CONSTRAINT;
engineConstraint->layerTest = rule->m_LayerCondition;
engineConstraint->condition = condition;
engineConstraint->constraint = constraint;
engineConstraint->parentRule = rule;
m_constraintMap[ constraintType ]->push_back( engineConstraint );
}
}
engineConstraint->layerTest = rule->m_LayerCondition;
engineConstraint->condition = condition;
engineConstraint->constraint = constraint;
engineConstraint->parentRule = rule;
m_constraintMap[ constraint.m_Type ]->push_back( engineConstraint );
}
}
}
@ -594,7 +584,7 @@ void DRC_ENGINE::InitEngine( const wxFileName& aRulePath )
}
for( int ii = DRCE_FIRST; ii < DRCE_LAST; ++ii )
m_errorLimits[ ii ] = INT_MAX;
m_errorLimits[ ii ] = ERROR_LIMIT_MAX;
m_rulesValid = true;
}
@ -612,7 +602,7 @@ void DRC_ENGINE::RunTests( EDA_UNITS aUnits, bool aReportAllTrackErrors, bool aT
if( m_designSettings->Ignore( ii ) )
m_errorLimits[ ii ] = 0;
else
m_errorLimits[ ii ] = INT_MAX;
m_errorLimits[ ii ] = ERROR_LIMIT_MAX;
}
m_board->IncrementTimeStamp(); // Invalidate all caches
@ -670,15 +660,13 @@ void DRC_ENGINE::RunTests( EDA_UNITS aUnits, bool aReportAllTrackErrors, bool aT
for( DRC_TEST_PROVIDER* provider : m_testProviders )
{
if( !provider->IsEnabled() )
continue;
if( provider->IsEnabled() )
{
ReportAux( wxString::Format( "Run DRC provider: '%s'", provider->GetName() ) );
drc_dbg( 0, "Running test provider: '%s'\n", provider->GetName() );
ReportAux( wxString::Format( "Run DRC provider: '%s'", provider->GetName() ) );
if( !provider->Run() )
break;
if( !provider->Run() )
break;
}
}
}

3
pcbnew/drc/drc_engine.h
View File

@ -143,7 +143,6 @@ public:
*/
void RunTests( EDA_UNITS aUnits, bool aReportAllTrackErrors, bool aTestFootprints );
bool IsErrorLimitExceeded( int error_code );
DRC_CONSTRAINT EvalRules( DRC_CONSTRAINT_T aConstraintType, const BOARD_ITEM* a,
@ -168,7 +167,7 @@ public:
bool QueryWorstConstraint( DRC_CONSTRAINT_T aRuleId, DRC_CONSTRAINT& aConstraint );
std::vector<DRC_TEST_PROVIDER* > GetTestProviders() const { return m_testProviders; };
std::vector<DRC_TEST_PROVIDER*> GetTestProviders() const { return m_testProviders; };
DRC_TEST_PROVIDER* GetTestProvider( const wxString& name ) const;

22
pcbnew/drc/drc_results_provider.cpp
View File

@ -28,20 +28,11 @@ void BOARD_DRC_ITEMS_PROVIDER::SetSeverities( int aSeverities )
{
m_severities = aSeverities;
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
m_filteredMarkers.clear();
for( PCB_MARKER* marker : m_board->Markers() )
{
SEVERITY markerSeverity;
if( marker->IsExcluded() )
markerSeverity = RPT_SEVERITY_EXCLUSION;
else
markerSeverity = bds.GetSeverity( marker->GetRCItem()->GetErrorCode() );
if( markerSeverity & m_severities )
if( marker->GetSeverity() & m_severities )
m_filteredMarkers.push_back( marker );
}
}
@ -52,20 +43,11 @@ int BOARD_DRC_ITEMS_PROVIDER::GetCount( int aSeverity ) const
if( aSeverity < 0 )
return m_filteredMarkers.size();
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
int count = 0;
for( PCB_MARKER* marker : m_board->Markers() )
{
SEVERITY markerSeverity;
if( marker->IsExcluded() )
markerSeverity = RPT_SEVERITY_EXCLUSION;
else
markerSeverity = bds.GetSeverity( marker->GetRCItem()->GetErrorCode() );
if( markerSeverity == aSeverity )
if( marker->GetSeverity() == aSeverity )
count++;
}

6
pcbnew/drc/drc_rule.cpp
View File

@ -32,7 +32,8 @@ DRC_RULE::DRC_RULE() :
m_Unary( false ),
m_Implicit( false ),
m_LayerCondition( LSET::AllLayersMask() ),
m_Condition( nullptr )
m_Condition( nullptr ),
m_Severity( RPT_SEVERITY_UNDEFINED )
{
}
@ -42,7 +43,8 @@ DRC_RULE::DRC_RULE( const wxString& aName ) :
m_Implicit( false ),
m_Name( aName ),
m_LayerCondition( LSET::AllLayersMask() ),
m_Condition( nullptr )
m_Condition( nullptr ),
m_Severity( RPT_SEVERITY_UNDEFINED )
{
}

10
pcbnew/drc/drc_rule.h
View File

@ -32,6 +32,7 @@
#include <zones.h>
#include <libeval_compiler/libeval_compiler.h>
#include <wx/intl.h>
#include <widgets/report_severity.h>
class BOARD_ITEM;
class PCB_EXPR_UCODE;
@ -109,6 +110,7 @@ public:
LSET m_LayerCondition;
DRC_RULE_CONDITION* m_Condition;
std::vector<DRC_CONSTRAINT> m_Constraints;
SEVERITY m_Severity;
};
@ -152,6 +154,14 @@ class DRC_CONSTRAINT
return m_name;
}
SEVERITY GetSeverity() const
{
if( m_parentRule )
return m_parentRule->m_Severity;
else
return RPT_SEVERITY_UNDEFINED;
}
public:
DRC_CONSTRAINT_T m_Type;
MINOPTMAX<int> m_Value;

39
pcbnew/drc/drc_rule_parser.cpp
View File

@ -226,6 +226,10 @@ DRC_RULE* DRC_RULES_PARSER::parseDRC_RULE()
rule->m_LayerCondition = parseLayer();
break;
case T_severity:
rule->m_Severity = parseSeverity();
break;
case T_EOF:
reportError( _( "Incomplete statement." ) );
return rule;
@ -575,3 +579,38 @@ LSET DRC_RULES_PARSER::parseLayer()
return retVal;
}
SEVERITY DRC_RULES_PARSER::parseSeverity()
{
SEVERITY retVal = RPT_SEVERITY_UNDEFINED;
wxString msg;
T token = NextTok();
if( (int) token == DSN_RIGHT || token == T_EOF )
{
reportError( _( "Missing severity name." ) );
return RPT_SEVERITY_UNDEFINED;
}
switch( token )
{
case T_ignore: retVal = RPT_SEVERITY_IGNORE; break;
case T_warning: retVal = RPT_SEVERITY_WARNING; break;
case T_error: retVal = RPT_SEVERITY_ERROR; break;
case T_exclusion: retVal = RPT_SEVERITY_EXCLUSION; break;
default:
msg.Printf( _( "Unrecognized item '%s'.| Expected %s." ),
FromUTF8(),
"ignore, warning, error or exclusion" );
reportError( msg );
parseUnknown();
}
if( (int) NextTok() != DSN_RIGHT )
reportError( _( "Missing ')'." ) );
return retVal;
}

1
pcbnew/drc/drc_rule_parser.h
View File

@ -51,6 +51,7 @@ private:
void parseConstraint( DRC_RULE* aRule );
void parseValueWithUnits( const wxString& aExpr, int& aResult );
LSET parseLayer();
SEVERITY parseSeverity();
void parseUnknown();
void reportError( const wxString& aMessage );

2
pcbnew/drc/drc_test_provider.h
View File

@ -89,8 +89,6 @@ public:
virtual const wxString GetName() const;
virtual const wxString GetDescription() const;
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const = 0;
bool IsEnabled() const
{
return m_enabled;

11
pcbnew/drc/drc_test_provider_annular_width.cpp
View File

@ -61,8 +61,6 @@ public:
{
return "Tests pad/via annular rings";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
};
@ -106,6 +104,9 @@ bool DRC_TEST_PROVIDER_ANNULAR_WIDTH::Run()
bool fail_min = false;
bool fail_max = false;
if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
return true;
if( constraint.Value().HasMin() )
{
v_min = constraint.Value().Min();
@ -162,12 +163,6 @@ bool DRC_TEST_PROVIDER_ANNULAR_WIDTH::Run()
}
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_ANNULAR_WIDTH::GetConstraintTypes() const
{
return { ANNULAR_WIDTH_CONSTRAINT };
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_ANNULAR_WIDTH> dummy;

8
pcbnew/drc/drc_test_provider_connectivity.cpp
View File

@ -63,8 +63,6 @@ public:
{
return "Tests board connectivity";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
};
@ -173,12 +171,6 @@ bool DRC_TEST_PROVIDER_CONNECTIVITY::Run()
}
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_CONNECTIVITY::GetConstraintTypes() const
{
return {};
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_CONNECTIVITY> dummy;

330
pcbnew/drc/drc_test_provider_copper_clearance.cpp
View File

@ -78,8 +78,6 @@ public:
return "Tests copper item clearance";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
private:
bool testTrackAgainstItem( PCB_TRACK* track, SHAPE* trackShape, PCB_LAYER_ID layer,
BOARD_ITEM* other );
@ -92,7 +90,7 @@ private:
void testZonesToZones();
void testItemAgainstZones( BOARD_ITEM* aItem, PCB_LAYER_ID aLayer );
void testItemAgainstZone( BOARD_ITEM* aItem, ZONE* aZone, PCB_LAYER_ID aLayer );
private:
DRC_RTREE m_copperTree;
@ -280,7 +278,7 @@ bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackAgainstItem( PCB_TRACK* track,
clearance = constraint.GetValue().Min();
}
if( clearance >= 0 )
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance >= 0 )
{
// Special processing for track:track intersections
if( track->Type() == PCB_TRACE_T && other->Type() == PCB_TRACE_T )
@ -347,25 +345,27 @@ bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackAgainstItem( PCB_TRACK* track,
constraint = m_drcEngine->EvalRules( HOLE_CLEARANCE_CONSTRAINT, other, track, layer );
clearance = constraint.GetValue().Min();
if( clearance > 0 && trackShape->Collide( holeShape.get(),
std::max( 0, clearance - m_drcEpsilon ),
&actual, &pos ) )
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance > 0 )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
if( trackShape->Collide( holeShape.get(), std::max( 0, clearance - m_drcEpsilon ),
&actual, &pos ) )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
drce->SetItems( track, other );
drce->SetViolatingRule( constraint.GetParentRule() );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
drce->SetItems( track, other );
drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, (wxPoint) pos );
reportViolation( drce, (wxPoint) pos );
if( !m_drcEngine->GetReportAllTrackErrors() )
return false;
if( !m_drcEngine->GetReportAllTrackErrors() )
return false;
}
}
}
}
@ -374,71 +374,115 @@ bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackAgainstItem( PCB_TRACK* track,
}
void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testItemAgainstZones( BOARD_ITEM* aItem,
void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testItemAgainstZone( BOARD_ITEM* aItem, ZONE* aZone,
PCB_LAYER_ID aLayer )
{
for( ZONE* zone : m_copperZones )
{
if( !zone->GetLayerSet().test( aLayer ) )
continue;
if( !aZone->GetLayerSet().test( aLayer ) )
return;
if( zone->GetNetCode() && aItem->IsConnected() )
if( aZone->GetNetCode() && aItem->IsConnected() )
{
if( aZone->GetNetCode() == static_cast<BOARD_CONNECTED_ITEM*>( aItem )->GetNetCode() )
return;
}
if( !aItem->GetBoundingBox().Intersects( aZone->GetCachedBoundingBox() ) )
return;
bool testClearance = !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE );
bool testHoles = !m_drcEngine->IsErrorLimitExceeded( DRCE_HOLE_CLEARANCE );
if( !testClearance && !testHoles )
return;
DRC_RTREE* zoneTree = m_board->m_CopperZoneRTrees[ aZone ].get();
EDA_RECT itemBBox = aItem->GetBoundingBox();
DRC_CONSTRAINT constraint;
int clearance = -1;
int actual;
VECTOR2I pos;
if( zoneTree && testClearance )
{
constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, aItem, aZone, aLayer );
clearance = constraint.GetValue().Min();
}
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance >= 0 )
{
std::shared_ptr<SHAPE> itemShape = aItem->GetEffectiveShape( aLayer );
if( aItem->Type() == PCB_PAD_T )
{
if( zone->GetNetCode() == static_cast<BOARD_CONNECTED_ITEM*>( aItem )->GetNetCode() )
continue;
PAD* pad = static_cast<PAD*>( aItem );
if( !pad->FlashLayer( aLayer ) )
{
if( pad->GetDrillSize().x == 0 && pad->GetDrillSize().y == 0 )
return;
const SHAPE_SEGMENT* hole = pad->GetEffectiveHoleShape();
int size = hole->GetWidth();
// Note: drill size represents finish size, which means the actual hole
// size is the plating thickness larger.
if( pad->GetAttribute() == PAD_ATTRIB::PTH )
size += m_board->GetDesignSettings().GetHolePlatingThickness();
itemShape = std::make_shared<SHAPE_SEGMENT>( hole->GetSeg(), size );
}
}
if( aItem->GetBoundingBox().Intersects( zone->GetCachedBoundingBox() ) )
if( zoneTree->QueryColliding( itemBBox, itemShape.get(), aLayer,
std::max( 0, clearance - m_drcEpsilon ), &actual, &pos ) )
{
bool testClearance = !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE );
bool testHoles = !m_drcEngine->IsErrorLimitExceeded( DRCE_HOLE_CLEARANCE );
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_CLEARANCE );
if( !testClearance && !testHoles )
return;
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
DRC_RTREE* zoneTree = m_board->m_CopperZoneRTrees[ zone ].get();
EDA_RECT itemBBox = aItem->GetBoundingBox();
DRC_CONSTRAINT constraint;
int clearance = -1;
int actual;
VECTOR2I pos;
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
drce->SetItems( aItem, aZone );
drce->SetViolatingRule( constraint.GetParentRule() );
if( zoneTree && testClearance )
reportViolation( drce, (wxPoint) pos );
}
}
if( zoneTree && testHoles && ( aItem->Type() == PCB_VIA_T || aItem->Type() == PCB_PAD_T ) )
{
std::unique_ptr<SHAPE_SEGMENT> holeShape;
if( aItem->Type() == PCB_VIA_T )
{
PCB_VIA* via = static_cast<PCB_VIA*>( aItem );
pos = via->GetPosition();
if( via->GetLayerSet().Contains( aLayer ) )
holeShape.reset( new SHAPE_SEGMENT( pos, pos, via->GetDrill() ) );
}
else if( aItem->Type() == PCB_PAD_T )
{
PAD* pad = static_cast<PAD*>( aItem );
if( pad->GetDrillSize().x )
holeShape.reset( new SHAPE_SEGMENT( *pad->GetEffectiveHoleShape() ) );
}
if( holeShape )
{
constraint = m_drcEngine->EvalRules( HOLE_CLEARANCE_CONSTRAINT, aItem, aZone, aLayer );
clearance = constraint.GetValue().Min();
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance >= 0 )
{
constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, aItem, zone, aLayer );
clearance = constraint.GetValue().Min();
}
if( clearance >= 0 )
{
std::shared_ptr<SHAPE> itemShape = aItem->GetEffectiveShape( aLayer );
if( aItem->Type() == PCB_PAD_T )
if( zoneTree->QueryColliding( itemBBox, holeShape.get(), aLayer,
std::max( 0, clearance - m_drcEpsilon ),
&actual, &pos ) )
{
PAD* pad = static_cast<PAD*>( aItem );
if( !pad->FlashLayer( aLayer ) )
{
if( pad->GetDrillSize().x == 0 && pad->GetDrillSize().y == 0 )
continue;
const SHAPE_SEGMENT* hole = pad->GetEffectiveHoleShape();
int size = hole->GetWidth();
// Note: drill size represents finish size, which means the actual hole
// size is the plating thickness larger.
if( pad->GetAttribute() == PAD_ATTRIB::PTH )
size += m_board->GetDesignSettings().GetHolePlatingThickness();
itemShape = std::make_shared<SHAPE_SEGMENT>( hole->GetSeg(), size );
}
}
if( zoneTree && zoneTree->QueryColliding( itemBBox, itemShape.get(), aLayer,
std::max( 0, clearance - m_drcEpsilon ),
&actual, &pos ) )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_CLEARANCE );
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
@ -446,58 +490,12 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testItemAgainstZones( BOARD_ITEM* aItem
MessageTextFromValue( userUnits(), actual ) );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
drce->SetItems( aItem, zone );
drce->SetItems( aItem, aZone );
drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, (wxPoint) pos );
}
}
if( testHoles && ( aItem->Type() == PCB_VIA_T || aItem->Type() == PCB_PAD_T ) )
{
std::unique_ptr<SHAPE_SEGMENT> holeShape;
if( aItem->Type() == PCB_VIA_T )
{
PCB_VIA* via = static_cast<PCB_VIA*>( aItem );
pos = via->GetPosition();
if( via->GetLayerSet().Contains( aLayer ) )
holeShape.reset( new SHAPE_SEGMENT( pos, pos, via->GetDrill() ) );
}
else if( aItem->Type() == PCB_PAD_T )
{
PAD* pad = static_cast<PAD*>( aItem );
if( pad->GetDrillSize().x )
holeShape.reset( new SHAPE_SEGMENT( *pad->GetEffectiveHoleShape() ) );
}
if( holeShape )
{
constraint = m_drcEngine->EvalRules( HOLE_CLEARANCE_CONSTRAINT, aItem, zone,
aLayer );
clearance = constraint.GetValue().Min();
if( zoneTree && zoneTree->QueryColliding( itemBBox, holeShape.get(), aLayer,
std::max( 0, clearance - m_drcEpsilon ),
&actual, &pos ) )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
drce->SetItems( aItem, zone );
drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, (wxPoint) pos );
}
}
}
}
}
}
@ -561,7 +559,8 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackClearances()
},
m_largestClearance );
testItemAgainstZones( track, layer );
for( ZONE* zone : m_copperZones )
testItemAgainstZone( track, zone, layer );
}
}
}
@ -667,23 +666,25 @@ bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadAgainstItem( PAD* pad, SHAPE* pa
constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, pad, other, layer );
clearance = constraint.GetValue().Min();
if( clearance > 0 && padShape->Collide( otherShape.get(),
std::max( 0, clearance - m_drcEpsilon ),
&actual, &pos ) )
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance > 0 )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_CLEARANCE );
if( padShape->Collide( otherShape.get(), std::max( 0, clearance - m_drcEpsilon ),
&actual, &pos ) )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_CLEARANCE );
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
drce->SetItems( pad, other );
drce->SetViolatingRule( constraint.GetParentRule() );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
drce->SetItems( pad, other );
drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, (wxPoint) pos );
testHoles = false; // No need for multiple violations
reportViolation( drce, (wxPoint) pos );
testHoles = false; // No need for multiple violations
}
}
}
@ -691,6 +692,9 @@ bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadAgainstItem( PAD* pad, SHAPE* pa
{
constraint = m_drcEngine->EvalRules( HOLE_CLEARANCE_CONSTRAINT, pad, other, layer );
clearance = constraint.GetValue().Min();
if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
testHoles = false;
}
if( testHoles && otherPad && pad->FlashLayer( layer ) && otherPad->GetDrillSize().x )
@ -819,7 +823,8 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadClearances( )
},
m_largestClearance );
testItemAgainstZones( pad, layer );
for( ZONE* zone : m_copperZones )
testItemAgainstZone( pad, zone, layer );
}
}
}
@ -832,6 +837,8 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZonesToZones()
SHAPE_POLY_SET buffer;
SHAPE_POLY_SET* boardOutline = nullptr;
DRC_CONSTRAINT constraint;
int zone2zoneClearance;
if( m_board->GetBoardPolygonOutlines( buffer ) )
boardOutline = &buffer;
@ -858,45 +865,41 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZonesToZones()
if( !reportProgress( layer_id * m_copperZones.size() + ia, B_Cu * m_copperZones.size(), delta ) )
break;
ZONE* zoneRef = m_copperZones[ia];
ZONE* zoneA = m_copperZones[ia];
if( !zoneRef->IsOnLayer( layer ) )
if( !zoneA->IsOnLayer( layer ) )
continue;
// If we are testing a single zone, then iterate through all other zones
// Otherwise, we have already tested the zone combination
for( size_t ia2 = ia + 1; ia2 < m_copperZones.size(); ia2++ )
{
ZONE* zoneToTest = m_copperZones[ia2];
if( zoneRef == zoneToTest )
continue;
ZONE* zoneB = m_copperZones[ia2];
// test for same layer
if( !zoneToTest->IsOnLayer( layer ) )
if( !zoneB->IsOnLayer( layer ) )
continue;
// Test for same net
if( zoneRef->GetNetCode() == zoneToTest->GetNetCode()
&& zoneRef->GetNetCode() >= 0 )
if( zoneA->GetNetCode() == zoneB->GetNetCode() && zoneA->GetNetCode() >= 0 )
continue;
// test for different priorities
if( zoneRef->GetPriority() != zoneToTest->GetPriority() )
if( zoneA->GetPriority() != zoneB->GetPriority() )
continue;
// rule areas may overlap at will
if( zoneRef->GetIsRuleArea() || zoneToTest->GetIsRuleArea() )
if( zoneA->GetIsRuleArea() || zoneB->GetIsRuleArea() )
continue;
// Examine a candidate zone: compare zoneToTest to zoneRef
// Examine a candidate zone: compare zoneB to zoneA
// Get clearance used in zone to zone test.
auto constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, zoneRef, zoneToTest,
layer );
int zone2zoneClearance = constraint.GetValue().Min();
constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, zoneA, zoneB, layer );
zone2zoneClearance = constraint.GetValue().Min();
// test for some corners of zoneRef inside zoneToTest
if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
continue;
// test for some corners of zoneA inside zoneB
for( auto iterator = smoothed_polys[ia].IterateWithHoles(); iterator; iterator++ )
{
VECTOR2I currentVertex = *iterator;
@ -905,14 +908,14 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZonesToZones()
if( smoothed_polys[ia2].Contains( currentVertex ) )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_ZONES_INTERSECT );
drce->SetItems( zoneRef, zoneToTest );
drce->SetItems( zoneA, zoneB );
drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, pt );
}
}
// test for some corners of zoneToTest inside zoneRef
// test for some corners of zoneB inside zoneA
for( auto iterator = smoothed_polys[ia2].IterateWithHoles(); iterator; iterator++ )
{
VECTOR2I currentVertex = *iterator;
@ -921,7 +924,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZonesToZones()
if( smoothed_polys[ia].Contains( currentVertex ) )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_ZONES_INTERSECT );
drce->SetItems( zoneToTest, zoneRef );
drce->SetItems( zoneB, zoneA );
drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, pt );
@ -955,12 +958,9 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZonesToZones()
bx2 = testSegment.B.x;
by2 = testSegment.B.y;
int d = GetClearanceBetweenSegments( bx1, by1, bx2, by2,
0,
ax1, ay1, ax2, ay2,
0,
zone2zoneClearance,
&pt.x, &pt.y );
int d = GetClearanceBetweenSegments( bx1, by1, bx2, by2, 0,
ax1, ay1, ax2, ay2, 0,
zone2zoneClearance, &pt.x, &pt.y );
if( d < zone2zoneClearance )
{
@ -974,7 +974,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZonesToZones()
for( const std::pair<const wxPoint, int>& conflict : conflictPoints )
{
int actual = conflict.second;
int actual = conflict.second;
std::shared_ptr<DRC_ITEM> drce;
if( actual <= 0 )
@ -993,7 +993,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZonesToZones()
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
}
drce->SetItems( zoneRef, zoneToTest );
drce->SetItems( zoneA, zoneB );
drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, conflict.first );
@ -1004,12 +1004,6 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZonesToZones()
}
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_COPPER_CLEARANCE::GetConstraintTypes() const
{
return { CLEARANCE_CONSTRAINT, HOLE_CLEARANCE_CONSTRAINT };
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_COPPER_CLEARANCE> dummy;

72
pcbnew/drc/drc_test_provider_courtyard_clearance.cpp
View File

@ -67,8 +67,6 @@ public:
return "Tests footprints' courtyard clearance";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
private:
bool testFootprintCourtyardDefinitions();
@ -198,54 +196,58 @@ bool DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testCourtyardClearances()
if( frontA.OutlineCount() > 0 && frontB.OutlineCount() > 0
&& frontBBox.Intersects( frontB.BBoxFromCaches() ) )
{
constraint = m_drcEngine->EvalRules( COURTYARD_CLEARANCE_CONSTRAINT, fpA, fpB,
F_Cu );
constraint = m_drcEngine->EvalRules( COURTYARD_CLEARANCE_CONSTRAINT, fpA, fpB, F_Cu );
clearance = constraint.GetValue().Min();
if( clearance >= 0 && frontA.Collide( &frontB, clearance, &actual, &pos ) )
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance >= 0 )
{
auto drce = DRC_ITEM::Create( DRCE_OVERLAPPING_FOOTPRINTS );
if( clearance > 0 )
if( frontA.Collide( &frontB, clearance, &actual, &pos ) )
{
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
auto drce = DRC_ITEM::Create( DRCE_OVERLAPPING_FOOTPRINTS );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
drce->SetViolatingRule( constraint.GetParentRule() );
if( clearance > 0 )
{
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
drce->SetViolatingRule( constraint.GetParentRule() );
}
drce->SetItems( fpA, fpB );
reportViolation( drce, (wxPoint) pos );
}
drce->SetItems( fpA, fpB );
reportViolation( drce, (wxPoint) pos );
}
}
if( backA.OutlineCount() > 0 && backB.OutlineCount() > 0
&& backBBox.Intersects( backB.BBoxFromCaches() ) )
{
constraint = m_drcEngine->EvalRules( COURTYARD_CLEARANCE_CONSTRAINT, fpA, fpB,
B_Cu );
constraint = m_drcEngine->EvalRules( COURTYARD_CLEARANCE_CONSTRAINT, fpA, fpB, B_Cu );
clearance = constraint.GetValue().Min();
if( clearance >= 0 && backA.Collide( &backB, clearance, &actual, &pos ) )
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance >= 0 )
{
auto drce = DRC_ITEM::Create( DRCE_OVERLAPPING_FOOTPRINTS );
if( clearance > 0 )
if( backA.Collide( &backB, clearance, &actual, &pos ) )
{
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
auto drce = DRC_ITEM::Create( DRCE_OVERLAPPING_FOOTPRINTS );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
drce->SetViolatingRule( constraint.GetParentRule() );
if( clearance > 0 )
{
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
drce->SetViolatingRule( constraint.GetParentRule() );
}
drce->SetItems( fpA, fpB );
reportViolation( drce, (wxPoint) pos );
}
drce->SetItems( fpA, fpB );
reportViolation( drce, (wxPoint) pos );
}
}
@ -317,12 +319,6 @@ bool DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::Run()
}
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::GetConstraintTypes() const
{
return { COURTYARD_CLEARANCE_CONSTRAINT };
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_COURTYARD_CLEARANCE> dummy;

18
pcbnew/drc/drc_test_provider_diff_pair_coupling.cpp
View File

@ -74,10 +74,7 @@ public:
return "Tests differential pair coupling";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
private:
BOARD* m_board;
};
@ -297,7 +294,7 @@ bool test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run()
auto constraint = m_drcEngine->EvalRules( constraintsToCheck[ i ], item,
nullptr, item->GetLayer() );
if( constraint.IsNull() )
if( constraint.IsNull() || constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
continue;
drc_dbg( 10, "cns %d item %p\n", constraintsToCheck[i], item );
@ -316,8 +313,8 @@ bool test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run()
m_board->GetConnectivity()->GetFromToCache()->Rebuild( m_board );
forEachGeometryItem( { PCB_TRACE_T, PCB_VIA_T, PCB_ARC_T },
LSET::AllCuMask(), evaluateDpConstraints );
forEachGeometryItem( { PCB_TRACE_T, PCB_VIA_T, PCB_ARC_T }, LSET::AllCuMask(),
evaluateDpConstraints );
drc_dbg( 10, "dp rule matches %d\n", (int) dpRuleMatches.size() );
@ -420,9 +417,6 @@ bool test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run()
if( val.HasMax() && gap > val.Max() )
insideRange = false;
// if(val.HasMin() && val.HasMax() )
// drc_dbg(10, "Vmin %d vmax %d\n", val.Min(), val.Max() );
cpair.couplingOK = insideRange;
}
else
@ -515,12 +509,6 @@ bool test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run()
}
std::set<DRC_CONSTRAINT_T> test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::GetConstraintTypes() const
{
return { DIFF_PAIR_GAP_CONSTRAINT, DIFF_PAIR_MAX_UNCOUPLED_CONSTRAINT };
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING> dummy;

10
pcbnew/drc/drc_test_provider_disallow.cpp
View File

@ -58,8 +58,6 @@ public:
{
return "Tests for disallowed items (e.g. keepouts)";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
};
@ -80,7 +78,7 @@ bool DRC_TEST_PROVIDER_DISALLOW::Run()
auto constraint = m_drcEngine->EvalRules( DISALLOW_CONSTRAINT, item, nullptr,
UNDEFINED_LAYER );
if( constraint.m_DisallowFlags )
if( constraint.m_DisallowFlags && constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
{
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ALLOWED_ITEMS );
@ -168,12 +166,6 @@ bool DRC_TEST_PROVIDER_DISALLOW::Run()
}
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_DISALLOW::GetConstraintTypes() const
{
return { DISALLOW_CONSTRAINT };
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_DISALLOW> dummy;

43
pcbnew/drc/drc_test_provider_edge_clearance.cpp
View File

@ -68,8 +68,6 @@ public:
return "Tests items vs board edge clearance";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
private:
bool testAgainstEdge( BOARD_ITEM* item, SHAPE* itemShape, BOARD_ITEM* other,
DRC_CONSTRAINT_T aConstraintType, PCB_DRC_CODE aErrorCode );
@ -88,26 +86,29 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::testAgainstEdge( BOARD_ITEM* item, SHAPE*
int actual;
VECTOR2I pos;
if( minClearance >= 0 && itemShape->Collide( edgeShape.get(), minClearance, &actual, &pos ) )
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && minClearance >= 0 )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( aErrorCode );
// Only report clearance info if there is any; otherwise it's just a straight collision
if( minClearance > 0 )
if( itemShape->Collide( edgeShape.get(), minClearance, &actual, &pos ) )
{
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), minClearance ),
MessageTextFromValue( userUnits(), actual ) );
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( aErrorCode );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
// Only report clearance info if there is any; otherwise it's just a straight collision
if( minClearance > 0 )
{
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), minClearance ),
MessageTextFromValue( userUnits(), actual ) );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
}
drce->SetItems( edge->m_Uuid, item->m_Uuid );
drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, (wxPoint) pos );
return false; // don't report violations with multiple edges; one is enough
}
drce->SetItems( edge->m_Uuid, item->m_Uuid );
drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, (wxPoint) pos );
return false; // don't report violations with multiple edges; one is enough
}
return true;
@ -281,12 +282,6 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
}
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_EDGE_CLEARANCE::GetConstraintTypes() const
{
return { EDGE_CLEARANCE_CONSTRAINT, SILK_CLEARANCE_CONSTRAINT };
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_EDGE_CLEARANCE> dummy;

14
pcbnew/drc/drc_test_provider_hole_size.cpp
View File

@ -60,8 +60,6 @@ public:
return "Tests sizes of drilled holes (via/pad drills)";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
private:
void checkVia( PCB_VIA* via, bool aExceedMicro, bool aExceedStd );
void checkPad( PAD* aPad );
@ -144,6 +142,9 @@ void DRC_TEST_PROVIDER_HOLE_SIZE::checkPad( PAD* aPad )
bool fail_max = false;
int constraintValue;
if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
return;
if( constraint.Value().HasMin() && holeMinor < constraint.Value().Min() )
{
fail_min = true;
@ -209,6 +210,9 @@ void DRC_TEST_PROVIDER_HOLE_SIZE::checkVia( PCB_VIA* via, bool aExceedMicro, boo
bool fail_max = false;
int constraintValue;
if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
return;
if( constraint.Value().HasMin() && via->GetDrillValue() < constraint.Value().Min() )
{
fail_min = true;
@ -249,12 +253,6 @@ void DRC_TEST_PROVIDER_HOLE_SIZE::checkVia( PCB_VIA* via, bool aExceedMicro, boo
}
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_HOLE_SIZE::GetConstraintTypes() const
{
return { HOLE_SIZE_CONSTRAINT };
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_HOLE_SIZE> dummy;

12
pcbnew/drc/drc_test_provider_hole_to_hole.cpp
View File

@ -68,8 +68,6 @@ public:
return "Tests hole to hole spacing";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
private:
bool testHoleAgainstHole( BOARD_ITEM* aItem, SHAPE_CIRCLE* aHole, BOARD_ITEM* aOther );
@ -304,7 +302,9 @@ bool DRC_TEST_PROVIDER_HOLE_TO_HOLE::testHoleAgainstHole( BOARD_ITEM* aItem, SHA
UNDEFINED_LAYER /* holes pierce all layers */ );
int minClearance = constraint.GetValue().Min() - epsilon;
if( minClearance >= 0 && actual < minClearance )
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE
&& minClearance >= 0
&& actual < minClearance )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_DRILLED_HOLES_TOO_CLOSE );
@ -325,12 +325,6 @@ bool DRC_TEST_PROVIDER_HOLE_TO_HOLE::testHoleAgainstHole( BOARD_ITEM* aItem, SHA
}
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_HOLE_TO_HOLE::GetConstraintTypes() const
{
return { HOLE_TO_HOLE_CONSTRAINT };
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_HOLE_TO_HOLE> dummy;

8
pcbnew/drc/drc_test_provider_library_parity.cpp
View File

@ -65,8 +65,6 @@ public:
{
return "Performs board footprint vs library integity checks";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
};
@ -508,12 +506,6 @@ bool DRC_TEST_PROVIDER_LIBRARY_PARITY::Run()
}
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_LIBRARY_PARITY::GetConstraintTypes() const
{
return {};
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_LIBRARY_PARITY> dummy;

14
pcbnew/drc/drc_test_provider_matched_length.cpp
View File

@ -66,8 +66,6 @@ public:
return "Tests matched track lengths.";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
DRC_LENGTH_REPORT BuildLengthReport() const;
private:
@ -361,17 +359,17 @@ bool DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal( bool aDelayReportMode )
OPT<DRC_CONSTRAINT> lengthConstraint = rule->FindConstraint( LENGTH_CONSTRAINT );
if( lengthConstraint )
if( lengthConstraint && lengthConstraint->GetSeverity() != RPT_SEVERITY_IGNORE )
checkLengths( *lengthConstraint, matchedConnections );
OPT<DRC_CONSTRAINT> skewConstraint = rule->FindConstraint( SKEW_CONSTRAINT );
if( skewConstraint )
if( skewConstraint && skewConstraint->GetSeverity() != RPT_SEVERITY_IGNORE )
checkSkews( *skewConstraint, matchedConnections );
OPT<DRC_CONSTRAINT> viaCountConstraint = rule->FindConstraint( VIA_COUNT_CONSTRAINT );
if( viaCountConstraint )
if( viaCountConstraint && viaCountConstraint->GetSeverity() != RPT_SEVERITY_IGNORE )
checkViaCounts( *viaCountConstraint, matchedConnections );
}
@ -382,12 +380,6 @@ bool DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal( bool aDelayReportMode )
}
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_MATCHED_LENGTH::GetConstraintTypes() const
{
return { LENGTH_CONSTRAINT, SKEW_CONSTRAINT, VIA_COUNT_CONSTRAINT };
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_MATCHED_LENGTH> dummy;

72
pcbnew/drc/drc_test_provider_mechanical_clearance.cpp
View File

@ -70,8 +70,6 @@ public:
return "Tests item clearances irrespective of nets";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
private:
bool testItemAgainstItem( BOARD_ITEM* item, SHAPE* itemShape, PCB_LAYER_ID layer,
BOARD_ITEM* other );
@ -510,7 +508,7 @@ void DRC_TEST_PROVIDER_MECHANICAL_CLEARANCE::testZoneLayer( ZONE* aZone, PCB_LAY
int clearance = aConstraint.GetValue().Min();
SHAPE_POLY_SET fill = aZone->GetFilledPolysList( aLayer );
if( clearance - epsilon <= 0 )
if( aConstraint.GetSeverity() == RPT_SEVERITY_IGNORE || clearance - epsilon <= 0 )
return;
// Turn fractured fill into outlines and holes
@ -580,7 +578,7 @@ bool DRC_TEST_PROVIDER_MECHANICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* it
clearance = constraint.GetValue().Min();
}
if( clearance > 0 )
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance > 0 )
{
if( itemShape->Collide( otherShape.get(), clearance, &actual, &pos ) )
{
@ -644,38 +642,39 @@ bool DRC_TEST_PROVIDER_MECHANICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* it
clearance = constraint.GetValue().Min();
}
if( clearance > 0 && itemHoleShape && itemHoleShape->Collide( otherShape.get(), clearance,
&actual, &pos ) )
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance > 0 )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
if( itemHoleShape && itemHoleShape->Collide( otherShape.get(), clearance, &actual, &pos ) )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
drce->SetItems( item, other );
drce->SetViolatingRule( constraint.GetParentRule() );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
drce->SetItems( item, other );
drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, (wxPoint) pos );
}
reportViolation( drce, (wxPoint) pos );
}
if( clearance > 0 && otherHoleShape && otherHoleShape->Collide( itemShape, clearance,
&actual, &pos ) )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
if( otherHoleShape && otherHoleShape->Collide( itemShape, clearance, &actual, &pos ) )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
MessageTextFromValue( userUnits(), clearance ),
MessageTextFromValue( userUnits(), actual ) );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
drce->SetItems( item, other );
drce->SetViolatingRule( constraint.GetParentRule() );
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
drce->SetItems( item, other );
drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, (wxPoint) pos );
reportViolation( drce, (wxPoint) pos );
}
}
}
@ -714,7 +713,7 @@ void DRC_TEST_PROVIDER_MECHANICAL_CLEARANCE::testItemAgainstZones( BOARD_ITEM* a
clearance = constraint.GetValue().Min();
}
if( clearance > 0 )
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance > 0 )
{
std::shared_ptr<SHAPE> itemShape = aItem->GetEffectiveShape( aLayer );
@ -793,9 +792,10 @@ void DRC_TEST_PROVIDER_MECHANICAL_CLEARANCE::testItemAgainstZones( BOARD_ITEM* a
aItem, zone, aLayer );
clearance = constraint.GetValue().Min();
if( clearance > 0 && zoneTree->QueryColliding( itemBBox, holeShape.get(),
aLayer, clearance, &actual,
&pos ) )
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE
&& clearance > 0
&& zoneTree->QueryColliding( itemBBox, holeShape.get(), aLayer,
clearance, &actual, &pos ) )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
@ -817,14 +817,6 @@ void DRC_TEST_PROVIDER_MECHANICAL_CLEARANCE::testItemAgainstZones( BOARD_ITEM* a
}
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_MECHANICAL_CLEARANCE::GetConstraintTypes() const
{
return { MECHANICAL_CLEARANCE_CONSTRAINT, MECHANICAL_HOLE_CLEARANCE_CONSTRAINT };
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_MECHANICAL_CLEARANCE> dummy;

8
pcbnew/drc/drc_test_provider_misc.cpp
View File

@ -68,8 +68,6 @@ public:
return "Misc checks (board outline, missing textvars)";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
private:
void testOutline();
void testDisabledLayers();
@ -282,12 +280,6 @@ bool DRC_TEST_PROVIDER_MISC::Run()
}
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_MISC::GetConstraintTypes() const
{
return {};
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_MISC> dummy;

8
pcbnew/drc/drc_test_provider_schematic_parity.cpp
View File

@ -68,8 +68,6 @@ public:
return "Performs layout-vs-schematics integity check";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
private:
void testNetlist( NETLIST& aNetlist );
};
@ -233,12 +231,6 @@ bool DRC_TEST_PROVIDER_SCHEMATIC_PARITY::Run()
}
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_SCHEMATIC_PARITY::GetConstraintTypes() const
{
return {};
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_SCHEMATIC_PARITY> dummy;

10
pcbnew/drc/drc_test_provider_silk_clearance.cpp
View File

@ -68,8 +68,6 @@ public:
return "Tests for overlapping silkscreen features.";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
private:
BOARD* m_board;
@ -193,7 +191,7 @@ bool DRC_TEST_PROVIDER_SILK_CLEARANCE::Run()
aTestItem->parent,
aLayers.second );
if( constraint.IsNull() )
if( constraint.IsNull() || constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
return true;
int minClearance = constraint.GetValue().Min();
@ -254,12 +252,6 @@ bool DRC_TEST_PROVIDER_SILK_CLEARANCE::Run()
}
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_SILK_CLEARANCE::GetConstraintTypes() const
{
return { SILK_CLEARANCE_CONSTRAINT };
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_SILK_CLEARANCE> dummy;

5
pcbnew/drc/drc_test_provider_sliver_checker.cpp
View File

@ -61,11 +61,6 @@ public:
return "Checks copper layers for slivers";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override
{
return {};
}
private:
wxString layerDesc( PCB_LAYER_ID aLayer );
};

10
pcbnew/drc/drc_test_provider_solder_mask.cpp
View File

@ -69,8 +69,6 @@ public:
"mask apertures of other nets";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
private:
void addItemToRTrees( BOARD_ITEM* item );
void buildRTrees();
@ -261,7 +259,7 @@ void DRC_TEST_PROVIDER_SOLDER_MASK::testSilkToMaskClearance()
int actual;
VECTOR2I pos;
if( clearance <= 0 )
if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE || clearance <= 0 )
return true;
std::shared_ptr<SHAPE> itemShape = item->GetEffectiveShape( layer );
@ -573,12 +571,6 @@ bool DRC_TEST_PROVIDER_SOLDER_MASK::Run()
}
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_SOLDER_MASK::GetConstraintTypes() const
{
return { SILK_CLEARANCE_CONSTRAINT };
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_SOLDER_MASK> dummy;

46
pcbnew/drc/drc_test_provider_text_dims.cpp
View File

@ -58,8 +58,6 @@ public:
{
return "Tests text height and thickness";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
};
@ -120,16 +118,19 @@ bool DRC_TEST_PROVIDER_TEXT_DIMS::Run()
int constraintHeight;
int actual = textItem->GetTextHeight();
if( constraint.Value().HasMin() && actual < constraint.Value().Min() )
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
{
fail_min = true;
constraintHeight = constraint.Value().Min();
}
if( constraint.Value().HasMin() && actual < constraint.Value().Min() )
{
fail_min = true;
constraintHeight = constraint.Value().Min();
}
if( constraint.Value().HasMax() && actual > constraint.Value().Max() )
{
fail_max = true;
constraintHeight = constraint.Value().Max();
if( constraint.Value().HasMax() && actual > constraint.Value().Max() )
{
fail_max = true;
constraintHeight = constraint.Value().Max();
}
}
if( fail_min || fail_max )
@ -168,16 +169,19 @@ bool DRC_TEST_PROVIDER_TEXT_DIMS::Run()
int constraintThickness;
int actual = textItem->GetTextThickness();
if( constraint.Value().HasMin() && actual < constraint.Value().Min() )
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
{
fail_min = true;
constraintThickness = constraint.Value().Min();
}
if( constraint.Value().HasMin() && actual < constraint.Value().Min() )
{
fail_min = true;
constraintThickness = constraint.Value().Min();
}
if( constraint.Value().HasMax() && actual > constraint.Value().Max() )
{
fail_max = true;
constraintThickness = constraint.Value().Max();
if( constraint.Value().HasMax() && actual > constraint.Value().Max() )
{
fail_max = true;
constraintThickness = constraint.Value().Max();
}
}
if( fail_min || fail_max )
@ -221,12 +225,6 @@ bool DRC_TEST_PROVIDER_TEXT_DIMS::Run()
}
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_TEXT_DIMS::GetConstraintTypes() const
{
return { TEXT_HEIGHT_CONSTRAINT, TEXT_THICKNESS_CONSTRAINT };
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_TEXT_DIMS> dummy;

27
pcbnew/drc/drc_test_provider_track_width.cpp
View File

@ -56,8 +56,6 @@ public:
{
return "Tests track widths";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
};
@ -110,16 +108,19 @@ bool DRC_TEST_PROVIDER_TRACK_WIDTH::Run()
bool fail_max = false;
int constraintWidth;
if( constraint.Value().HasMin() && actual < constraint.Value().Min() )
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
{
fail_min = true;
constraintWidth = constraint.Value().Min();
}
if( constraint.Value().HasMin() && actual < constraint.Value().Min() )
{
fail_min = true;
constraintWidth = constraint.Value().Min();
}
if( constraint.Value().HasMax() && actual > constraint.Value().Max() )
{
fail_max = true;
constraintWidth = constraint.Value().Max();
if( constraint.Value().HasMax() && actual > constraint.Value().Max() )
{
fail_max = true;
constraintWidth = constraint.Value().Max();
}
}
if( fail_min || fail_max )
@ -168,12 +169,6 @@ bool DRC_TEST_PROVIDER_TRACK_WIDTH::Run()
}
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_TRACK_WIDTH::GetConstraintTypes() const
{
return { TRACK_WIDTH_CONSTRAINT };
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_TRACK_WIDTH> dummy;

27
pcbnew/drc/drc_test_provider_via_diameter.cpp
View File

@ -56,8 +56,6 @@ public:
{
return "Tests via diameters";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
};
@ -100,16 +98,19 @@ bool DRC_TEST_PROVIDER_VIA_DIAMETER::Run()
int constraintDiameter = 0;
int actual = via->GetWidth();
if( constraint.Value().HasMin() && actual < constraint.Value().Min() )
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
{
fail_min = true;
constraintDiameter = constraint.Value().Min();
}
if( constraint.Value().HasMin() && actual < constraint.Value().Min() )
{
fail_min = true;
constraintDiameter = constraint.Value().Min();
}
if( constraint.Value().HasMax() && actual > constraint.Value().Max() )
{
fail_max = true;
constraintDiameter = constraint.Value().Max();
if( constraint.Value().HasMax() && actual > constraint.Value().Max() )
{
fail_max = true;
constraintDiameter = constraint.Value().Max();
}
}
if( fail_min )
@ -158,12 +159,6 @@ bool DRC_TEST_PROVIDER_VIA_DIAMETER::Run()
}
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_VIA_DIAMETER::GetConstraintTypes() const
{
return { VIA_DIAMETER_CONSTRAINT };
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_VIA_DIAMETER> dummy;

8
pcbnew/drc/drc_test_provider_zone_connections.cpp
View File

@ -64,12 +64,6 @@ public:
{
return "Checks thermal reliefs for a sufficient number of connecting spokes";
}
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override
{
return { ZONE_CONNECTION_CONSTRAINT, THERMAL_RELIEF_GAP_CONSTRAINT,
THERMAL_SPOKE_WIDTH_CONSTRAINT, MIN_RESOLVED_SPOKES_CONSTRAINT };
}
};
bool DRC_TEST_PROVIDER_ZONE_CONNECTIONS::Run()
@ -132,7 +126,7 @@ bool DRC_TEST_PROVIDER_ZONE_CONNECTIONS::Run()
pad, zone, layer );
int minCount = constraint.m_Value.Min();
if( minCount <= 0 )
if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE || minCount <= 0 )
continue;
SHAPE_POLY_SET padPoly;

5
pcbnew/pcb_display_options.cpp
View File

@ -24,11 +24,6 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
#include <common.h>
#include <pcbnew.h>
#include <pad.h>
#include <board_design_settings.h>
#include <layer_ids.h>
#include <pcb_display_options.h>
#include <eda_text.h>

4
pcbnew/pcb_edit_frame.cpp
View File

@ -809,7 +809,7 @@ void PCB_EDIT_FRAME::RecordDRCExclusions()
for( PCB_MARKER* marker : GetBoard()->Markers() )
{
if( marker->IsExcluded() )
if( marker->GetSeverity() == RPT_SEVERITY_EXCLUSION )
bds.m_DrcExclusions.insert( marker->Serialize() );
}
}
@ -826,7 +826,7 @@ void PCB_EDIT_FRAME::ResolveDRCExclusions()
for( PCB_MARKER* marker : GetBoard()->Markers() )
{
if( marker->IsExcluded() )
if( marker->GetSeverity() == RPT_SEVERITY_EXCLUSION )
{
GetCanvas()->GetView()->Remove( marker );
GetCanvas()->GetView()->Add( marker );

54
pcbnew/pcb_marker.cpp
View File

@ -93,6 +93,8 @@ void PCB_MARKER::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_
{
aList.emplace_back( _( "Type" ), _( "Marker" ) );
aList.emplace_back( _( "Violation" ), m_rcItem->GetErrorMessage() );
aList.emplace_back( _( "Severity" ), GetSeverity() == RPT_SEVERITY_ERROR ? _( "Error" )
: _( "Warning" ) );
wxString mainText;
wxString auxText;
@ -149,51 +151,45 @@ BITMAPS PCB_MARKER::GetMenuImage() const
}
SEVERITY PCB_MARKER::GetSeverity() const
{
if( IsExcluded() )
return RPT_SEVERITY_EXCLUSION;
DRC_ITEM* item = static_cast<DRC_ITEM*>( m_rcItem.get() );
DRC_RULE* rule = item->GetViolatingRule();
if( rule && rule->m_Severity != RPT_SEVERITY_UNDEFINED )
return rule->m_Severity;
return GetBoard()->GetDesignSettings().GetSeverity( item->GetErrorCode() );
}
void PCB_MARKER::ViewGetLayers( int aLayers[], int& aCount ) const
{
aCount = 2;
aLayers[1] = LAYER_MARKER_SHADOWS;
if( IsExcluded() )
{
aLayers[0] = LAYER_DRC_EXCLUSION;
return;
}
BOARD_ITEM_CONTAINER* ancestor = GetParent();
while( ancestor->GetParent() )
ancestor = ancestor->GetParent();
BOARD* board = static_cast<BOARD*>( ancestor );
switch( board->GetDesignSettings().GetSeverity( m_rcItem->GetErrorCode() ) )
switch( GetSeverity() )
{
default:
case SEVERITY::RPT_SEVERITY_ERROR: aLayers[0] = LAYER_DRC_ERROR; break;
case SEVERITY::RPT_SEVERITY_WARNING: aLayers[0] = LAYER_DRC_WARNING; break;
case SEVERITY::RPT_SEVERITY_ERROR: aLayers[0] = LAYER_DRC_ERROR; break;
case SEVERITY::RPT_SEVERITY_WARNING: aLayers[0] = LAYER_DRC_WARNING; break;
case SEVERITY::RPT_SEVERITY_EXCLUSION: aLayers[0] = LAYER_DRC_EXCLUSION; break;
}
}
GAL_LAYER_ID PCB_MARKER::GetColorLayer() const
{
if( IsExcluded() )
return LAYER_DRC_EXCLUSION;
BOARD_ITEM_CONTAINER* ancestor = GetParent();
while( ancestor->GetParent() )
ancestor = ancestor->GetParent();
BOARD* board = static_cast<BOARD*>( ancestor );
switch( board->GetDesignSettings().GetSeverity( m_rcItem->GetErrorCode() ) )
switch( GetSeverity() )
{
default:
case SEVERITY::RPT_SEVERITY_ERROR: return LAYER_DRC_ERROR;
case SEVERITY::RPT_SEVERITY_WARNING: return LAYER_DRC_WARNING;
case SEVERITY::RPT_SEVERITY_ERROR: return LAYER_DRC_ERROR;
case SEVERITY::RPT_SEVERITY_WARNING: return LAYER_DRC_WARNING;
case SEVERITY::RPT_SEVERITY_EXCLUSION: return LAYER_DRC_EXCLUSION;
}
}

2
pcbnew/pcb_marker.h
View File

@ -105,6 +105,8 @@ public:
void ViewGetLayers( int aLayers[], int& aCount ) const override;
SEVERITY GetSeverity() const override;
#if defined(DEBUG)
void Show( int nestLevel, std::ostream& os ) const override { ShowDummy( os ); }
#endif

2
pcbnew/python/scripting/pcbnew_scripting_helpers.cpp
View File

@ -517,7 +517,7 @@ bool WriteDRCReport( BOARD* aBoard, const wxString& aFileName, EDA_UNITS aUnits,
for( const std::shared_ptr<DRC_ITEM>& item : violations )
{
SEVERITY severity = bds.GetSeverity( item->GetErrorCode() );
SEVERITY severity = item->GetParent()->GetSeverity();
fprintf( fp, "%s", TO_UTF8( item->ShowReport( aUnits, severity, itemMap ) ) );
}

128
qa/data/custom_pads.kicad_pro
View File

@ -1,5 +1,128 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.12,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.508
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "error",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.01,
"min_hole_clearance": 0.0,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.12,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"track_widths": [],
"via_dimensions": [],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
@ -35,7 +158,7 @@
}
],
"meta": {
"version": 0
"version": 1
},
"net_colors": null
},
@ -46,7 +169,8 @@
"netlist": "",
"specctra_dsn": "",
"step": "",
"vmrl": ""
"vmrl": "",
"vrml": ""
},
"page_layout_descr_file": ""
},

14
qa/data/issue1358.kicad_pro
View File

@ -48,7 +48,13 @@
"min_clearance": 0.254
}
},
"diff_pair_dimensions": [],
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"filename": "board_design_settings.json",
@ -56,9 +62,9 @@
},
"rule_severities": {
"annular_width": "error",
"aperture_clearance": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
@ -84,6 +90,7 @@
"silk_over_copper": "ignore",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
@ -103,7 +110,7 @@
"max_error": 0.005,
"min_aperture_clearance": 0.049999999999999996,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.024999999999999998,
"min_copper_edge_clearance": 0.25,
"min_hole_clearance": 0.0,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
@ -116,6 +123,7 @@
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"track_widths": [

5
qa/data/severities.kicad_dru Normal file
View File

@ -0,0 +1,5 @@
(version 1)
(rule board_edge
(constraint edge_clearance (min 1mm))
(condition "A.memberOf('board_edge')")
(severity ignore))

3482
qa/data/severities.kicad_pcb Normal file
View File

File diff suppressed because it is too large Load Diff

417
qa/data/severities.kicad_pro Normal file
View File

@ -0,0 +1,417 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.0,
"height": 0.4,
"width": 1.35
},
"silk_line_width": 0.12,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.254
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"filename": "board_design_settings.json",
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "ignore",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "ignore",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"too_many_vias": "error",
"track_dangling": "ignore",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_aperture_clearance": 0.049999999999999996,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.25,
"min_hole_clearance": 0.0,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.12,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"track_widths": [
0.0,
0.3,
0.35,
0.4
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 1.0,
"drill": 0.5
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_sheet_names": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "error",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "issue1358.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
}
],
"meta": {
"version": 1
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"drawing": {
"default_bus_thickness": 12.0,
"default_junction_size": 36.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"default_wire_thickness": 6.0,
"field_names": [],
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.3
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 0
},
"net_format_name": "",
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"155f8eea-0e5f-4cd4-af54-d2a6a7cc5844",
"AM2315 sensors I2C interface"
],
[
"3171c8e1-e8bd-4b55-9726-8c0ea0490320",
"230V & general interface"
],
[
"155f8eea-0e5f-4cd4-af54-d2a6a7cc5844",
""
]
],
"text_variables": {}
}

1
qa/pcbnew/CMakeLists.txt
View File

@ -41,6 +41,7 @@ set( QA_PCBNEW_SRCS
test_tracks_cleaner.cpp
test_zone_filler.cpp
drc/test_custom_rule_severities.cpp
drc/test_drc_courtyard_invalid.cpp
drc/test_drc_courtyard_overlap.cpp
drc/test_drc_regressions.cpp

84
qa/pcbnew/drc/test_custom_rule_severities.cpp Normal file
View File

@ -0,0 +1,84 @@
/*
* This program source code file is part of KiCad, a free EDA CAD application.
*
* Copyright (C) 2021 KiCad Developers, see AUTHORS.txt for contributors.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you may find one here:
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
* or you may search the http://www.gnu.org website for the version 2 license,
* or you may write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
#include <qa_utils/wx_utils/unit_test_utils.h>
#include <qa/pcbnew/board_test_utils.h>
#include <board.h>
#include <board_design_settings.h>
#include <pcb_marker.h>
#include <drc/drc_item.h>
#include <settings/settings_manager.h>
struct DRC_REGRESSION_TEST_FIXTURE
{
DRC_REGRESSION_TEST_FIXTURE() :
m_settingsManager( true /* headless */ )
{ }
SETTINGS_MANAGER m_settingsManager;
std::unique_ptr<BOARD> m_board;
};
BOOST_FIXTURE_TEST_CASE( DRCCustomRuleSeverityTest, DRC_REGRESSION_TEST_FIXTURE )
{
// This board has two edge-connectors. There is a custom DRC rule which conditionally
// applies to one of them and sets the edge-clearance severity to "ignore". It should
// therefore only generate edge-clearance violations for the other edge connector.
KI_TEST::LoadBoard( m_settingsManager, "severities", m_board );
KI_TEST::FillZones( m_board.get(), 6 );
std::vector<DRC_ITEM> violations;
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
bds.m_DRCEngine->SetViolationHandler(
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
{
PCB_MARKER temp( aItem, aPos );
if( bds.m_DrcExclusions.find( temp.Serialize() ) == bds.m_DrcExclusions.end() )
violations.push_back( *aItem );
} );
bds.m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
if( violations.size() == 8 )
{
BOOST_CHECK_EQUAL( 1, 1 ); // quiet "did not check any assertions" warning
BOOST_TEST_MESSAGE( "Custom rule severity test passed" );
}
else
{
BOOST_CHECK_EQUAL( violations.size(), 8 );
std::map<KIID, EDA_ITEM*> itemMap;
m_board->FillItemMap( itemMap );
for( const DRC_ITEM& item : violations )
BOOST_TEST_MESSAGE( item.ShowReport( EDA_UNITS::INCHES, RPT_SEVERITY_ERROR, itemMap ) );
BOOST_ERROR( "Custom rule severity test failed" );
}
}

5
qa/pcbnew/drc/test_solder_mask_bridging.cpp
View File

@ -73,10 +73,7 @@ BOOST_FIXTURE_TEST_CASE( DRCSolderMaskBridgingTest, DRC_REGRESSION_TEST_FIXTURE
m_board->FillItemMap( itemMap );
for( const DRC_ITEM& item : violations )
{
BOOST_TEST_MESSAGE( item.ShowReport( EDA_UNITS::INCHES, RPT_SEVERITY_ERROR,
itemMap ) );
}
BOOST_TEST_MESSAGE( item.ShowReport( EDA_UNITS::INCHES, RPT_SEVERITY_ERROR, itemMap ) );
BOOST_ERROR( "DRC solder mask bridge test failed" );
}