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Add DRC testing for copper graphic to zone fill collisions.

This commit is contained in:
Jeff Young 2023-06-30 11:56:36 +01:00
parent 8b26f50003
commit 60696a895c
8 changed files with 1223 additions and 19 deletions
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29
libs/kimath/src/geometry/shape_collisions.cpp
View File

@ -785,6 +785,21 @@ inline bool CollCaseReversed ( const SHAPE* aA, const SHAPE* aB, int aClearance,
static bool collideSingleShapes( const SHAPE* aA, const SHAPE* aB, int aClearance, int* aActual,
VECTOR2I* aLocation, VECTOR2I* aMTV )
{
if( aA->Type() == SH_POLY_SET )
{
const SHAPE_POLY_SET* polySetA = static_cast<const SHAPE_POLY_SET*>( aA );
wxASSERT( !aMTV );
return polySetA->Collide( aB, aClearance, aActual, aLocation );
}
else if( aB->Type() == SH_POLY_SET )
{
const SHAPE_POLY_SET* polySetB = static_cast<const SHAPE_POLY_SET*>( aB );
wxASSERT( !aMTV );
return polySetB->Collide( aA, aClearance, aActual, aLocation );
}
switch( aA->Type() )
{
case SH_NULL:
@ -1086,20 +1101,6 @@ static bool collideShapes( const SHAPE* aA, const SHAPE* aB, int aClearance, int
}
}
}
else if( aA->Type() == SH_POLY_SET )
{
const SHAPE_POLY_SET* polySetA = static_cast<const SHAPE_POLY_SET*>( aA );
wxASSERT( !aMTV );
return polySetA->Collide( aB, aClearance, aActual, aLocation );
}
else if( aB->Type() == SH_POLY_SET )
{
const SHAPE_POLY_SET* polySetB = static_cast<const SHAPE_POLY_SET*>( aB );
wxASSERT( !aMTV );
return polySetB->Collide( aA, aClearance, aActual, aLocation );
}
else
{
return collideSingleShapes( aA, aB, aClearance, aActual, aLocation, aMTV );

163
pcbnew/drc/drc_test_provider_copper_clearance.cpp
View File

@ -96,10 +96,14 @@ private:
void testPadClearances();
void testGraphicClearances();
void testZonesToZones();
void testItemAgainstZone( BOARD_ITEM* aItem, ZONE* aZone, PCB_LAYER_ID aLayer );
void testKnockoutTextAgainstZone( BOARD_ITEM* aText, NETINFO_ITEM** aInheritedNet, ZONE* aZone );
typedef struct checked
{
checked()
@ -160,6 +164,14 @@ bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::Run()
testPadClearances();
}
if( !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE ) )
{
if( !reportPhase( _( "Checking copper graphic clearances..." ) ) )
return false; // DRC cancelled
testGraphicClearances();
}
if( !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE ) )
{
if( !reportPhase( _( "Checking copper zone clearances..." ) ) )
@ -431,6 +443,89 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testItemAgainstZone( BOARD_ITEM* aItem,
}
/*
* We have to special-case knockout text as it's most often knocked-out of a zone, so it's
* presumed to collide with one. However, if it collides with more than one, and they have
* different nets, then we have a short.
*/
void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testKnockoutTextAgainstZone( BOARD_ITEM* aText,
NETINFO_ITEM** aInheritedNet,
ZONE* aZone )
{
bool testClearance = !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE );
bool testShorts = !m_drcEngine->IsErrorLimitExceeded( DRCE_SHORTING_ITEMS );
if( !testClearance && !testShorts )
return;
PCB_LAYER_ID layer = aText->GetLayer();
if( !aZone->GetLayerSet().test( layer ) )
return;
BOX2I itemBBox = aText->GetBoundingBox();
BOX2I worstCaseBBox = itemBBox;
worstCaseBBox.Inflate( m_board->m_DRCMaxClearance );
if( !worstCaseBBox.Intersects( aZone->GetBoundingBox() ) )
return;
DRC_RTREE* zoneTree = m_board->m_CopperZoneRTreeCache[ aZone ].get();
if( !zoneTree )
return;
std::shared_ptr<SHAPE> itemShape = aText->GetEffectiveShape( layer, FLASHING::DEFAULT );
if( *aInheritedNet == nullptr )
{
if( zoneTree->QueryColliding( itemBBox, itemShape.get(), layer ) )
*aInheritedNet = aZone->GetNet();
}
if( *aInheritedNet == aZone->GetNet() )
return;
DRC_CONSTRAINT constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, aText, aZone, layer );
int clearance = constraint.GetValue().Min();
int actual;
VECTOR2I pos;
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance >= 0 )
{
if( zoneTree->QueryColliding( itemBBox, itemShape.get(), layer,
std::max( 0, clearance - m_drcEpsilon ), &actual, &pos ) )
{
std::shared_ptr<DRC_ITEM> drce;
wxString msg;
if( testShorts && actual == 0 && *aInheritedNet )
{
drce = DRC_ITEM::Create( DRCE_SHORTING_ITEMS );
msg.Printf( _( "(nets %s and %s)" ),
( *aInheritedNet )->GetNetname(),
aZone->GetNetname() );
}
else
{
drce = DRC_ITEM::Create( DRCE_CLEARANCE );
msg = formatMsg( _( "(%s clearance %s; actual %s)" ),
constraint.GetName(),
clearance,
actual );
}
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
drce->SetItems( aText, aZone );
drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, pos, layer );
}
}
}
void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackClearances()
{
// This is the number of tests between 2 calls to the progress bar
@ -815,7 +910,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadClearances( )
}
}
if( !reportProgress( ii++, count, progressDelta ) )
if( !reportProgress( ii++, (int) count, progressDelta ) )
return;
}
@ -825,6 +920,72 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadClearances( )
}
void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testGraphicClearances( )
{
const int progressDelta = 100;
size_t count = m_board->Drawings().size();
int ii = 0;
for( FOOTPRINT* footprint : m_board->Footprints() )
count += footprint->GraphicalItems().size();
reportAux( wxT( "Testing %d graphics..." ), count );
auto isKnockoutText =
[]( BOARD_ITEM* item )
{
if( item->Type() == PCB_TEXT_T )
return static_cast<PCB_TEXT*>( item )->IsKnockout();
else if( item->Type() == PCB_FP_TEXT_T )
return static_cast<FP_TEXT*>( item )->IsKnockout();
else
return false;
};
auto testGraphicAgainstZone =
[&]( BOARD_ITEM* item )
{
if( !IsCopperLayer( item->GetLayer() ) )
return;
// Knockout text is most often knocked-out of a zone, so it's presumed to
// collide with one. However, if it collides with more than one, and they
// have different nets, then we have a short.
NETINFO_ITEM* inheritedNet = nullptr;
for( ZONE* zone : m_board->m_DRCCopperZones )
{
if( isKnockoutText( item ) )
testKnockoutTextAgainstZone( item, &inheritedNet, zone );
else
testItemAgainstZone( item, zone, item->GetLayer() );
if( m_drcEngine->IsCancelled() )
return;
}
};
for( BOARD_ITEM* item : m_board->Drawings() )
{
testGraphicAgainstZone( item );
if( !reportProgress( ii++, (int) count, progressDelta ) )
return;
}
for( FOOTPRINT* footprint : m_board->Footprints() )
{
for( BOARD_ITEM* item : footprint->GraphicalItems() )
{
testGraphicAgainstZone( item );
if( !reportProgress( ii++, (int) count, progressDelta ) )
return;
}
}
}
void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZonesToZones()
{
const int progressDelta = 50;

2
pcbnew/pcb_text.cpp
View File

@ -365,7 +365,7 @@ void PCB_TEXT::TransformShapeToPolygon( SHAPE_POLY_SET& aBuffer, PCB_LAYER_ID aL
{
SHAPE_POLY_SET poly;
TransformTextToPolySet( poly, 0, GetBoard()->GetDesignSettings().m_MaxError, ERROR_INSIDE );
TransformTextToPolySet( poly, 0, GetBoard()->GetDesignSettings().m_MaxError, aErrorLoc );
buildBoundingHull( &aBuffer, poly, aClearance );
}

410
qa/data/pcbnew/test_copper_graphics.kicad_pcb Normal file
View File

@ -0,0 +1,410 @@
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)
(paper "A4")
(layers
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(32 "B.Adhes" user "B.Adhesive")
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(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
(50 "User.1" user)
(51 "User.2" user)
(52 "User.3" user)
(53 "User.4" user)
(54 "User.5" user)
(55 "User.6" user)
(56 "User.7" user)
(57 "User.8" user)
(58 "User.9" user)
)
(setup
(pad_to_mask_clearance 0)
(pcbplotparams
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(plot_on_all_layers_selection 0x0000000_00000000)
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)
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)
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(xy 154.000001 83.8)
(xy 154 83.800001)
(xy 154 85.049998)
(xy 153.5 85.049998)
(xy 153.5 83.399)
(xy 153.518907 83.340809)
(xy 153.568407 83.304845)
(xy 153.599 83.3)
(xy 154.749998 83.3)
(xy 154.749999 83.299999)
(xy 154.749999 82.750013)
(xy 154.739507 82.647312)
(xy 154.739504 82.6473)
(xy 154.684356 82.480875)
(xy 154.592319 82.331659)
(xy 154.479664 82.219004)
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(xy 154.504723 82.06079)
(xy 154.549668 82.05)
(xy 157.301 82.05)
)
)
)
(zone (net 3) (net_name "Test3") (layer "B.Cu") (tstamp e7fb42af-8060-4e89-b56c-5293c80f1b68) (hatch edge 0.5)
(priority 1)
(connect_pads (clearance 0.5))
(min_thickness 0.25) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 159.385 89.154)
(xy 150.241 89.154)
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(xy 159.385 91.313)
)
)
(filled_polygon
(layer "B.Cu")
(pts
(xy 159.328039 89.173685)
(xy 159.373794 89.226489)
(xy 159.385 89.278)
(xy 159.385 91.189)
(xy 159.365315 91.256039)
(xy 159.312511 91.301794)
(xy 159.261 91.313)
(xy 150.365 91.313)
(xy 150.297961 91.293315)
(xy 150.252206 91.240511)
(xy 150.241 91.189)
(xy 150.241 89.565405)
(xy 150.260685 89.498366)
(xy 150.313489 89.452611)
(xy 150.365 89.441405)
(xy 155.065513 89.441405)
(xy 155.065513 89.278)
(xy 155.085198 89.210961)
(xy 155.138002 89.165206)
(xy 155.189513 89.154)
(xy 159.261 89.154)
)
)
)
)

533
qa/data/pcbnew/test_copper_graphics.kicad_pro Normal file
View File

@ -0,0 +1,533 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.09999999999999999,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.15,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.5
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "warning",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.0,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.0,
"min_via_annular_width": 0.09999999999999999,
"min_via_diameter": 0.5,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [],
"via_dimensions": [],
"zones_allow_external_fillets": false
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
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0,
0,
0,
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0,
0,
0,
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],
[
1,
1,
1,
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1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
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0,
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2,
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],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "test_copper_graphics.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.127,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"bom_fmt_presets": [],
"bom_fmt_settings": {
"field_delimiter": ",",
"keep_line_breaks": false,
"keep_tabs": false,
"name": "CSV",
"ref_delimiter": ",",
"ref_range_delimiter": "",
"string_delimiter": "\""
},
"bom_presets": [],
"bom_settings": {
"exclude_dnp": false,
"fields_ordered": [
{
"group_by": false,
"label": "Reference",
"name": "Reference",
"show": true
},
{
"group_by": true,
"label": "Value",
"name": "Value",
"show": true
},
{
"group_by": false,
"label": "Datasheet",
"name": "Datasheet",
"show": true
},
{
"group_by": false,
"label": "Footprint",
"name": "Footprint",
"show": true
},
{
"group_by": false,
"label": "Qty",
"name": "Quantity",
"show": true
}
],
"filter_string": "",
"group_symbols": true,
"name": "Grouped By Value",
"sort_asc": true,
"sort_field": "Reference"
},
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"operating_point_overlay_i_precision": 3,
"operating_point_overlay_i_range": "~A",
"operating_point_overlay_v_precision": 3,
"operating_point_overlay_v_range": "~V",
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"page_layout_descr_file": "",
"plot_directory": "",
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_dissipations": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"fa34e893-36fd-4808-a15f-a0155a635056",
""
]
],
"text_variables": {}
}

1
qa/unittests/pcbnew/CMakeLists.txt
View File

@ -47,6 +47,7 @@ set( QA_PCBNEW_SRCS
drc/test_drc_courtyard_overlap.cpp
drc/test_drc_regressions.cpp
drc/test_drc_copper_conn.cpp
drc/test_drc_copper_graphics.cpp
drc/test_drc_copper_sliver.cpp
drc/test_solder_mask_bridging.cpp

98
qa/unittests/pcbnew/drc/test_drc_copper_graphics.cpp Normal file
View File

@ -0,0 +1,98 @@
/*
* This program source code file is part of KiCad, a free EDA CAD application.
*
* Copyright (C) 2023 KiCad Developers, see AUTHORS.txt for contributors.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you may find one here:
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
* or you may search the http://www.gnu.org website for the version 2 license,
* or you may write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
#include <qa_utils/wx_utils/unit_test_utils.h>
#include <pcbnew_utils/board_test_utils.h>
#include <board.h>
#include <board_design_settings.h>
#include <pcb_marker.h>
#include <drc/drc_item.h>
#include <settings/settings_manager.h>
struct DRC_COPPER_GRAPHICS_TEST_FIXTURE
{
DRC_COPPER_GRAPHICS_TEST_FIXTURE() :
m_settingsManager( true /* headless */ )
{ }
SETTINGS_MANAGER m_settingsManager;
std::unique_ptr<BOARD> m_board;
};
BOOST_FIXTURE_TEST_CASE( DRCCopperGraphicsTest, DRC_COPPER_GRAPHICS_TEST_FIXTURE )
{
wxString brd_name( wxT( "test_copper_graphics" ) );
KI_TEST::LoadBoard( m_settingsManager, brd_name, m_board );
// Do NOT refill zones; this will prevent some of the items from being tested.
// KI_TEST::FillZones( m_board.get() );
std::vector<DRC_ITEM> violations;
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
// Disable some DRC tests not useful in this testcase (and time consuming)
bds.m_DRCSeverities[ DRCE_LIB_FOOTPRINT_ISSUES ] = SEVERITY::RPT_SEVERITY_IGNORE;
bds.m_DRCSeverities[ DRCE_LIB_FOOTPRINT_MISMATCH ] = SEVERITY::RPT_SEVERITY_IGNORE;
bds.m_DRCSeverities[ DRCE_COPPER_SLIVER ] = SEVERITY::RPT_SEVERITY_IGNORE;
bds.m_DRCSeverities[ DRCE_STARVED_THERMAL ] = SEVERITY::RPT_SEVERITY_IGNORE;
bds.m_DRCSeverities[ DRCE_SILK_CLEARANCE ] = SEVERITY::RPT_SEVERITY_IGNORE;
bds.m_DRCSeverities[ DRCE_ISOLATED_COPPER ] = SEVERITY::RPT_SEVERITY_IGNORE;
bds.m_DRCEngine->SetViolationHandler(
[&]( const std::shared_ptr<DRC_ITEM>& aItem, VECTOR2I aPos, int aLayer )
{
PCB_MARKER temp( aItem, aPos );
if( bds.m_DrcExclusions.find( temp.Serialize() ) == bds.m_DrcExclusions.end() )
violations.push_back( *aItem );
} );
bds.m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
const int expected_err_cnt = 4; // "What" copper text shorting zone
// Copper knockout text shorting two zones twice (but not
// three times as the two vertical zones are the same net)
// Net-tie rectangle shorting zone
if( violations.size() == expected_err_cnt )
{
BOOST_CHECK_EQUAL( 1, 1 ); // quiet "did not check any assertions" warning
BOOST_TEST_MESSAGE( "DRC copper graphics test passed" );
}
else
{
BOOST_CHECK_EQUAL( violations.size(), expected_err_cnt );
UNITS_PROVIDER unitsProvider( pcbIUScale, EDA_UNITS::INCHES );
std::map<KIID, EDA_ITEM*> itemMap;
m_board->FillItemMap( itemMap );
for( const DRC_ITEM& item : violations )
BOOST_TEST_MESSAGE( item.ShowReport( &unitsProvider, RPT_SEVERITY_ERROR, itemMap ) );
BOOST_ERROR( wxString::Format( "DRC copper graphics test failed board <%s>", brd_name ) );
}
}

6
qa/unittests/pcbnew/drc/test_solder_mask_bridging.cpp
View File

@ -30,9 +30,9 @@
#include <settings/settings_manager.h>
struct DRC_REGRESSION_TEST_FIXTURE
struct DRC_SOLDER_MASK_BRIDGING_TEST_FIXTURE
{
DRC_REGRESSION_TEST_FIXTURE() :
DRC_SOLDER_MASK_BRIDGING_TEST_FIXTURE() :
m_settingsManager( true /* headless */ )
{ }
@ -41,7 +41,7 @@ struct DRC_REGRESSION_TEST_FIXTURE
};
BOOST_FIXTURE_TEST_CASE( DRCSolderMaskBridgingTest, DRC_REGRESSION_TEST_FIXTURE )
BOOST_FIXTURE_TEST_CASE( DRCSolderMaskBridgingTest, DRC_SOLDER_MASK_BRIDGING_TEST_FIXTURE )
{
wxString brd_name( wxT( "solder_mask_bridge_test" ) );
KI_TEST::LoadBoard( m_settingsManager, brd_name, m_board );