haskal
/
kicad
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

CADSTAR PCB: Rule Areas have zero width 

Cadstar areas have a line width but this is only for display purposes.
Instead CADSTAR uses the center line when determining whether a DRC
violation occurred.
This commit is contained in:
Roberto Fernandez Bautista 2021-10-08 21:27:32 +01:00
parent 2dfbd42be6
commit 677166f0b8
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp
View File

@ -821,8 +821,8 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadLibraryAreas( const SYMDEF_PCB& aComponent,
if( area.NoVias || area.NoTracks )
{
ZONE* zone = getZoneFromCadstarShape( area.Shape, getLineThickness( area.LineCodeID ),
aFootprint );
int lineThickness = 0; // CADSTAR areas only use the line width for display purpose
ZONE* zone = getZoneFromCadstarShape( area.Shape, lineThickness, aFootprint );
aFootprint->Add( zone, ADD_MODE::APPEND );
@ -1522,8 +1522,8 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadAreas()
if( area.NoVias || area.NoTracks || area.Keepout || area.Routing )
{
ZONE* zone = getZoneFromCadstarShape( area.Shape, getLineThickness( area.LineCodeID ),
m_board );
int lineThickness = 0; // CADSTAR areas only use the line width for display purpose
ZONE* zone = getZoneFromCadstarShape( area.Shape, lineThickness, m_board );
m_board->Add( zone, ADD_MODE::APPEND );