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Import a few more rules from Altium board files. 

Fixes https://gitlab.com/kicad/code/kicad/-/issues/15585
This commit is contained in:
Jeff Young 2023-10-25 16:06:26 +01:00
parent fc4bc10d27
commit 6a2aeeeae2
3 changed files with 65 additions and 3 deletions
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21
pcbnew/plugins/altium/altium_parser_pcb.cpp
View File

@ -531,15 +531,31 @@ ARULE6::ARULE6( ALTIUM_PARSER& aReader )
else if( rulekind == wxT( "HoleSize" ) )
{
kind = ALTIUM_RULE_KIND::HOLE_SIZE;
minLimit = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "MINLIMIT" ), wxT( "1mil" ) );
maxLimit = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "MAXLIMIT" ), wxT( "150mil" ) );
}
else if( rulekind == wxT( "HoleToHoleClearance" ) )
{
kind = ALTIUM_RULE_KIND::HOLE_TO_HOLE_CLEARANCE;
clearanceGap = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "GAP" ), wxT( "10mil" ) );
}
else if( rulekind == wxT( "RoutingVias" ) )
{
kind = ALTIUM_RULE_KIND::ROUTING_VIAS;
width = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "WIDTH" ), wxT( "20mil" ) );
minWidth = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "MINWIDTH" ), wxT( "20mil" ) );
maxWidth = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "MAXWIDTH" ), wxT( "50mil" ) );
holeWidth = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "HOLEWIDTH" ), wxT( "10mil" ) );
minHoleWidth = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "MINHOLEWIDTH" ), wxT( "10mil" ) );
maxHoleWidth = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "MAXHOLEWIDTH" ), wxT( "28mil" ) );
}
else if( rulekind == wxT( "Width" ) )
{
kind = ALTIUM_RULE_KIND::WIDTH;
}
minLimit = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "MINLIMIT" ), wxT( "6mil" ) );
maxLimit = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "MAXLIMIT" ), wxT( "40mil" ) );
preferredWidth = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "PREFERREDWIDTH" ), wxT( "6mil" ) );
}
else if( rulekind == wxT( "PasteMaskExpansion" ) )
{
kind = ALTIUM_RULE_KIND::PASTE_MASK_EXPANSION;
@ -548,8 +564,7 @@ ARULE6::ARULE6( ALTIUM_PARSER& aReader )
else if( rulekind == wxT( "SolderMaskExpansion" ) )
{
kind = ALTIUM_RULE_KIND::SOLDER_MASK_EXPANSION;
soldermaskExpansion =
ALTIUM_PARSER::ReadKicadUnit( props, wxT( "EXPANSION" ), wxT( "4mil" ) );
soldermaskExpansion = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "EXPANSION" ), wxT( "4mil" ) );
}
else if( rulekind == wxT( "PlaneClearance" ) )
{

18
pcbnew/plugins/altium/altium_parser_pcb.h
View File

@ -108,6 +108,7 @@ enum class ALTIUM_RULE_KIND
SOLDER_MASK_EXPANSION = 8,
PLANE_CLEARANCE = 9,
POLYGON_CONNECT = 10,
ROUTING_VIAS = 11
};
enum class ALTIUM_CONNECT_STYLE
@ -499,8 +500,25 @@ struct ARULE6
wxString scope2expr;
// ALTIUM_RULE_KIND::CLEARANCE
// ALTIUM_RULE_KIND::HOLE_TO_HOLE_CLEARANCE
int clearanceGap;
// ALTIUM_RULE_KIND::WIDTH
// ALTIUM_RULE_KIND::HOLE_SIZE
int minLimit;
int maxLimit;
// ALTIUM_RULE_KIND::WIDTH
int preferredWidth;
// ALTIUM_RULE_KIND::ROUTING_VIAS
int width;
int minWidth;
int maxWidth;
int holeWidth;
int minHoleWidth;
int maxHoleWidth;
// ALTIUM_RULE_KIND::PLANE_CLEARANCE
int planeclearanceClearance;

29
pcbnew/plugins/altium/altium_pcb.cpp
View File

@ -1841,6 +1841,35 @@ void ALTIUM_PCB::ParseRules6Data( const ALTIUM_COMPOUND_FILE& aAltiumPcbFile
} );
}
const ARULE6* clearanceRule = GetRuleDefault( ALTIUM_RULE_KIND::CLEARANCE );
const ARULE6* trackWidthRule = GetRuleDefault( ALTIUM_RULE_KIND::WIDTH );
const ARULE6* routingViasRule = GetRuleDefault( ALTIUM_RULE_KIND::ROUTING_VIAS );
const ARULE6* holeSizeRule = GetRuleDefault( ALTIUM_RULE_KIND::HOLE_SIZE );
const ARULE6* holeToHoleRule = GetRuleDefault( ALTIUM_RULE_KIND::HOLE_TO_HOLE_CLEARANCE );
if( clearanceRule )
m_board->GetDesignSettings().m_MinClearance = clearanceRule->clearanceGap;
if( trackWidthRule )
{
m_board->GetDesignSettings().m_TrackMinWidth = trackWidthRule->minLimit;
// TODO: construct a custom rule for preferredWidth and maxLimit values
}
if( routingViasRule )
{
m_board->GetDesignSettings().m_ViasMinSize = routingViasRule->minWidth;
m_board->GetDesignSettings().m_MinThroughDrill = routingViasRule->minHoleWidth;
}
if( holeSizeRule )
{
// TODO: construct a custom rule for minLimit / maxLimit values
}
if( holeToHoleRule )
m_board->GetDesignSettings().m_HoleToHoleMin = holeToHoleRule->clearanceGap;
const ARULE6* soldermaskRule = GetRuleDefault( ALTIUM_RULE_KIND::SOLDER_MASK_EXPANSION );
const ARULE6* pastemaskRule = GetRuleDefault( ALTIUM_RULE_KIND::PASTE_MASK_EXPANSION );