ADDED properties passed between eescema and pcbnew.
And referencable from textVars. Fixes https://gitlab.com/kicad/code/kicad/issues/5079
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32a7d00256
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@ -28,6 +28,7 @@ part
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pin
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pins
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pinfunction
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property
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ref
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sheetpath
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source
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@ -205,9 +205,9 @@ XNODE* NETLIST_EXPORTER_GENERIC::makeComponents( unsigned aCtl )
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// Output is xml, so there is no reason to remove spaces from the field values.
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// And XML element names need not be translated to various languages.
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for( unsigned i = 0; i < sheetList.size(); i++ )
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for( unsigned ii = 0; ii < sheetList.size(); ii++ )
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{
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SCH_SHEET_PATH sheet = sheetList[i];
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SCH_SHEET_PATH sheet = sheetList[ii];
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auto cmp =
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[sheet]( SCH_COMPONENT* a, SCH_COMPONENT* b )
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@ -218,9 +218,9 @@ XNODE* NETLIST_EXPORTER_GENERIC::makeComponents( unsigned aCtl )
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std::set<SCH_COMPONENT*, decltype( cmp )> ordered_components( cmp );
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for( auto item : sheetList[i].LastScreen()->Items().OfType( SCH_COMPONENT_T ) )
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for( SCH_ITEM* item : sheetList[ii].LastScreen()->Items().OfType( SCH_COMPONENT_T ) )
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{
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auto comp = static_cast<SCH_COMPONENT*>( item );
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SCH_COMPONENT* comp = static_cast<SCH_COMPONENT*>( item );
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auto test = ordered_components.insert( comp );
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if( !test.second )
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@ -233,7 +233,7 @@ XNODE* NETLIST_EXPORTER_GENERIC::makeComponents( unsigned aCtl )
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}
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}
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for( auto item : ordered_components )
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for( EDA_ITEM* item : ordered_components )
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{
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SCH_COMPONENT* comp = findNextComponent( item, &sheet );
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@ -242,17 +242,16 @@ XNODE* NETLIST_EXPORTER_GENERIC::makeComponents( unsigned aCtl )
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|| ( ( aCtl & GNL_OPT_KICAD ) && !comp->GetIncludeOnBoard() ) )
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continue;
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XNODE* xcomp; // current component being constructed
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// Output the component's elements in order of expected access frequency.
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// This may not always look best, but it will allow faster execution
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// under XSL processing systems which do sequential searching within
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// an element.
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XNODE* xcomp; // current component being constructed
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xcomps->AddChild( xcomp = node( "comp" ) );
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xcomp->AddAttribute( "ref", comp->GetRef( &sheet ) );
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addComponentFields( xcomp, comp, &sheetList[i] );
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xcomp->AddAttribute( "ref", comp->GetRef( &sheet ) );
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addComponentFields( xcomp, comp, &sheetList[ii] );
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XNODE* xlibsource;
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xcomp->AddChild( xlibsource = node( "libsource" ) );
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@ -268,9 +267,20 @@ XNODE* NETLIST_EXPORTER_GENERIC::makeComponents( unsigned aCtl )
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xlibsource->AddAttribute( "description", comp->GetDescription() );
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XNODE* xsheetpath;
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std::vector<SCH_FIELD>& fields = comp->GetFields();
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for( size_t jj = MANDATORY_FIELDS; jj < fields.size(); ++jj )
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{
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XNODE* xproperty;
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xcomp->AddChild( xproperty = node( "property" ) );
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xproperty->AddAttribute( "name", fields[jj].GetName() );
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xproperty->AddAttribute( "value", fields[jj].GetText() );
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}
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XNODE* xsheetpath;
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xcomp->AddChild( xsheetpath = node( "sheetpath" ) );
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xsheetpath->AddAttribute( "names", sheet.PathHumanReadable() );
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xsheetpath->AddAttribute( "tstamps", sheet.PathAsString() );
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xcomp->AddChild( node( "tstamp", comp->m_Uuid.AsString() ) );
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@ -373,6 +373,11 @@ bool MODULE::ResolveTextVar( wxString* token, int aDepth ) const
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*token = GetLayerName();
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return true;
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}
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else if( m_properties.count( *token ) )
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{
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*token = m_properties.at( *token );
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return true;
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}
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return false;
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}
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@ -488,6 +488,9 @@ public:
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TEXTE_MODULE& Value() const { return *m_Value; }
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TEXTE_MODULE& Reference() const { return *m_Reference; }
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const std::map<wxString, wxString>& GetProperties() const { return m_properties; }
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void SetProperties( const std::map<wxString, wxString>& aProps ) { m_properties = aProps; }
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/**
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* Function FindPadByName
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* returns a D_PAD* with a matching name. Note that names may not be
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@ -699,7 +702,6 @@ private:
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DRAWINGS m_drawings; // BOARD_ITEMs for drawings on the board, owned by pointer.
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PADS m_pads; // D_PAD items, owned by pointer
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MODULE_ZONE_CONTAINERS m_fp_zones; // MODULE_ZONE_CONTAINER items, owned by pointer
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std::list<MODULE_3D_SETTINGS> m_3D_Drawings; // Linked list of 3D models.
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double m_Orient; // Orientation in tenths of a degree, 900=90.0 degrees.
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wxPoint m_Pos; // Position of module on the board in internal units.
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@ -727,13 +729,13 @@ private:
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int m_CntRot90; // Horizontal automatic placement cost ( 0..10 ).
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int m_CntRot180; // Vertical automatic placement cost ( 0..10 ).
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wxArrayString* m_initial_comments; ///< leading s-expression comments in the module,
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///< lazily allocated only if needed for speed
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std::list<MODULE_3D_SETTINGS> m_3D_Drawings; // Linked list of 3D models.
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std::map<wxString, wxString> m_properties;
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wxArrayString* m_initial_comments; // s-expression comments in the module,
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// lazily allocated only if needed for speed
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/// Used in DRC to test the courtyard area (a polygon which can be not basic
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/// Note also a footprint can have courtyards on both board sides
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SHAPE_POLY_SET m_poly_courtyard_front;
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SHAPE_POLY_SET m_poly_courtyard_back;
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SHAPE_POLY_SET m_poly_courtyard_front; // Note that a module can have both front and back
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SHAPE_POLY_SET m_poly_courtyard_back; // courtyards populated.
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};
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#endif // MODULE_H_
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@ -954,6 +954,15 @@ void PCB_IO::format( MODULE* aModule, int aNestLevel ) const
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m_out->Print( aNestLevel+1, "(tags %s)\n",
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m_out->Quotew( aModule->GetKeywords() ).c_str() );
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const std::map<wxString, wxString>& props = aModule->GetProperties();
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for( const std::pair<const wxString, wxString>& prop : props )
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{
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m_out->Print( aNestLevel+1, "(property %s %s)\n",
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m_out->Quotew( prop.first ).c_str(),
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m_out->Quotew( prop.second ).c_str() );
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}
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if( !( m_ctl & CTL_OMIT_PATH ) && !aModule->GetPath().empty() )
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m_out->Print( aNestLevel+1, "(path %s)\n",
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m_out->Quotew( aModule->GetPath().AsString() ).c_str() );
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@ -73,7 +73,8 @@ class TEXTE_PCB;
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//#define SEXPR_BOARD_FILE_VERSION 20200625 // Multilayer zones, zone names, island controls
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//#define SEXPR_BOARD_FILE_VERSION 20200628 // remove visibility settings
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//#define SEXPR_BOARD_FILE_VERSION 20200724 // Add KIID to module components
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#define SEXPR_BOARD_FILE_VERSION 20200807 // Add zone hatch advanced settings
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//#define SEXPR_BOARD_FILE_VERSION 20200807 // Add zone hatch advanced settings
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#define SEXPR_BOARD_FILE_VERSION 20200808 // Add properties to modules
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#define CTL_STD_LAYER_NAMES (1 << 0) ///< Use English Standard layer names
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#define CTL_OMIT_NETS (1 << 1) ///< Omit pads net names (useless in library)
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@ -285,7 +285,7 @@ bool BOARD_NETLIST_UPDATER::updateComponentParameters( MODULE* aPcbComponent,
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aPcbComponent->GetReference(),
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aPcbComponent->GetPath().AsString(),
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aNewComponent->GetPath().AsString() );
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m_reporter->Report( msg, RPT_SEVERITY_INFO );
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m_reporter->Report( msg, RPT_SEVERITY_ACTION );
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if( !m_isDryRun )
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{
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@ -294,6 +294,19 @@ bool BOARD_NETLIST_UPDATER::updateComponentParameters( MODULE* aPcbComponent,
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}
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}
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if( aPcbComponent->GetProperties() != aNewComponent->GetProperties() )
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{
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msg.Printf( _( "Update %s properties." ),
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aPcbComponent->GetReference() );
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m_reporter->Report( msg, RPT_SEVERITY_ACTION );
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if( !m_isDryRun )
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{
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changed = true;
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aPcbComponent->SetProperties( aNewComponent->GetProperties() );
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}
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}
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if( changed && copy )
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m_commit.Modified( aPcbComponent, copy );
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else
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@ -285,6 +285,7 @@ void KICAD_NETLIST_PARSER::parseComponent()
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* (value DB25FEMALE)
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* (footprint DB25FC)
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* (libsource (lib conn) (part DB25))
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* (property (name PINCOUNT) (value 25))
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* (sheetpath (names /) (tstamps /))
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* (tstamp 68183921-93a5-49ac-91b0-49d05a0e1647))
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*
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@ -300,6 +301,7 @@ void KICAD_NETLIST_PARSER::parseComponent()
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wxString name;
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KIID_PATH path;
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KIID uuid;
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std::map<wxString, wxString> properties;
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// The token comp was read, so the next data is (ref P1)
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while( (token = NextTok()) != T_RIGHT )
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}
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break;
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case T_property:
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{
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wxString propName;
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wxString propValue;
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while( (token = NextTok() ) != T_RIGHT )
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{
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if( token == T_LEFT )
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token = NextTok();
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if( token == T_name )
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{
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NeedSYMBOLorNUMBER();
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propName = FROM_UTF8( CurText() );
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NeedRIGHT();
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}
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else if( token == T_value )
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{
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NeedSYMBOLorNUMBER();
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propValue = FROM_UTF8( CurText() );
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NeedRIGHT();
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}
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else
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{
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Expecting( "name or value" );
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}
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}
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if( !propName.IsEmpty() )
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properties[ propName ] = propValue;
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}
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break;
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case T_sheetpath:
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while( ( token = NextTok() ) != T_EOF )
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{
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@ -397,6 +432,7 @@ void KICAD_NETLIST_PARSER::parseComponent()
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COMPONENT* component = new COMPONENT( fpid, ref, value, path );
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component->SetName( name );
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component->SetLibrary( library );
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component->SetProperties( properties );
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m_netlist->AddComponent( component );
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}
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@ -312,6 +312,7 @@ private:
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* (value DB25FEMELLE)
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* (footprint DB25FC)
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* (libsource (lib conn) (part DB25))
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* (property (name PINCOUNT) (value 25))
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* (sheetpath (names /) (tstamps /))
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* (tstamp 3256759C))
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*/
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@ -48,6 +48,7 @@ void COMPONENT::SetModule( MODULE* aModule )
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aModule->SetValue( m_value );
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aModule->SetFPID( m_fpid );
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aModule->SetPath( m_path );
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aModule->SetProperties( m_properties );
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}
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@ -56,10 +57,10 @@ COMPONENT_NET COMPONENT::m_emptyNet;
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const COMPONENT_NET& COMPONENT::GetNet( const wxString& aPinName ) const
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{
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for( unsigned i = 0; i < m_nets.size(); i++ )
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for( const COMPONENT_NET& net : m_nets )
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{
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if( m_nets[i].GetPinName() == aPinName )
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return m_nets[i];
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if( net.GetPinName() == aPinName )
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return net;
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}
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return m_emptyNet;
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@ -105,6 +105,9 @@ class COMPONENT
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/// The #MODULE loaded for #m_fpid.
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std::unique_ptr< MODULE > m_footprint;
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/// Component-specific properties found in the netlist.
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std::map<wxString, wxString> m_properties;
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static COMPONENT_NET m_emptyNet;
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public:
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const wxString& GetLibrary() const { return m_library; }
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const wxString& GetReference() const { return m_reference; }
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const wxString& GetValue() const { return m_value; }
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void SetProperties( std::map<wxString, wxString>& aProps )
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{
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m_properties = std::move( aProps );
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}
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const std::map<wxString, wxString>& GetProperties() const { return m_properties; }
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void SetFPID( const LIB_ID& aFPID ) { m_fpid = aFPID; }
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const LIB_ID& GetFPID() const { return m_fpid; }
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@ -2454,6 +2454,8 @@ MODULE* PCB_PARSER::parseMODULE_unchecked( wxArrayString* aInitialComments )
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std::unique_ptr<MODULE> module( new MODULE( m_board ) );
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std::map<wxString, wxString> properties;
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module->SetInitialComments( aInitialComments );
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token = NextTok();
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@ -2550,6 +2552,14 @@ MODULE* PCB_PARSER::parseMODULE_unchecked( wxArrayString* aInitialComments )
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NeedRIGHT();
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break;
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case T_property:
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NeedSYMBOL();
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name = FromUTF8();
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NeedSYMBOL();
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properties[ name ] = FromUTF8();
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NeedRIGHT();
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break;
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case T_path:
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NeedSYMBOLorNUMBER(); // Paths can be numerical so a number is also a symbol here
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module->SetPath( KIID_PATH( FromUTF8() ) );
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@ -2717,6 +2727,7 @@ MODULE* PCB_PARSER::parseMODULE_unchecked( wxArrayString* aInitialComments )
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}
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module->SetFPID( fpid );
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module->SetProperties( properties );
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module->CalculateBoundingBox();
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return module.release();
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