Vias, creation and editon: fix a bug in legacy mode when creating a micro-via (the drill diameter was the standard vias drill, not the micro-via drill).
Also in global vas edition, always set the via drill to the actual current netclass value (do not use anymore the 0 value as default), to avoid unwanted invisible drill change for existing vias when the netclass value is modified. This is consistent with the via creation, in GAL mode
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commit
6ff03b41fd
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@ -837,8 +837,24 @@ void VIA::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, const w
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if( displ_opts->m_DisplayViaMode != VIA_HOLE_NOT_SHOW )
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{
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// Display all drill holes requested or Display non default holes requested
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if( (displ_opts->m_DisplayViaMode == ALL_VIA_HOLE_SHOW)
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|| ( (drill_radius > 0 ) && !IsDrillDefault() ) )
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bool show_hole = displ_opts->m_DisplayViaMode == ALL_VIA_HOLE_SHOW;
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if( !show_hole )
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{
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NETINFO_ITEM* net = GetNet();
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int drill_class_value = 0;
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if( net )
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{
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if( GetViaType() == VIA_MICROVIA )
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drill_class_value = net->GetMicroViaDrillSize();
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else
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drill_class_value = net->GetViaDrillSize();
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}
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show_hole = GetDrillValue() != drill_class_value;
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}
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if( show_hole )
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{
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if( fillvia )
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{
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@ -1208,6 +1224,7 @@ void VIA::GetMsgPanelInfoBase( std::vector< MSG_PANEL_ITEM >& aList )
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LAYER_ID top_layer, bottom_layer;
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LayerPair( &top_layer, &bottom_layer );
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if( board )
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msg = board->GetLayerName( top_layer ) + wxT( "/" )
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+ board->GetLayerName( bottom_layer );
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@ -1230,10 +1247,29 @@ void VIA::GetMsgPanelInfoBase( std::vector< MSG_PANEL_ITEM >& aList )
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wxString title = _( "Drill" );
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title += wxT( " " );
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if( m_Drill >= 0 )
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bool drl_specific = true;
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if( GetBoard() )
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{
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NETINFO_ITEM* net = GetNet();
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int drill_class_value = 0;
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if( net )
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{
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if( GetViaType() == VIA_MICROVIA )
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drill_class_value = net->GetMicroViaDrillSize();
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else
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drill_class_value = net->GetViaDrillSize();
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}
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drl_specific = drill_value != drill_class_value;
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}
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if( drl_specific )
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title += _( "(Specific)" );
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else
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title += _( "(Default)" );
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title += _( "(NetClass)" );
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aList.push_back( MSG_PANEL_ITEM( title, msg, RED ) );
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}
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@ -29,7 +29,7 @@
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/* Methods of class DRC to initialize drc markers with messages
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* according to items and error ode
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* according to items and error code
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*/
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#include <fctsys.h>
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@ -73,12 +73,14 @@ bool PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK* aTrackItem,
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{
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const VIA *via = static_cast<const VIA *>( aTrackItem );
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if( !via->IsDrillDefault() )
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initial_drill = via->GetDrillValue();
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// Get the draill value, regardless it is default or specific
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initial_drill = via->GetDrillValue();
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if( net )
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{
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new_width = net->GetViaSize();
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new_drill = GetDesignSettings().GetCurrentViaDrill();
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new_drill = net->GetViaDrillSize();
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}
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else
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{
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@ -89,10 +91,22 @@ bool PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK* aTrackItem,
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if( via->GetViaType() == VIA_MICROVIA )
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{
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if( net )
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{
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new_width = net->GetMicroViaSize();
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new_drill = net->GetMicroViaDrillSize();
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}
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else
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new_width = GetDesignSettings().GetCurrentMicroViaSize();
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}
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// Old versions set a drill value <= 0, when the default netclass it used
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// but it could be better to set the drill value to the actual value
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// to avoid issues for existing vias, if the default drill value is modified
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// in the netclass, and not in current vias.
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if( via->GetDrill() <= 0 ) // means default netclass drill value used
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{
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initial_drill = -1; // Force drill vias re-initialization
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}
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}
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aTrackItem->SetWidth( new_width );
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@ -112,10 +126,11 @@ bool PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK* aTrackItem,
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{
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change_ok = true;
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}
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else if( (aTrackItem->Type() == PCB_VIA_T) && (initial_drill != new_drill) )
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else if( (aTrackItem->Type() == PCB_VIA_T) )
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{
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// if new width == initial_width: do nothing, unless a via has its drill value changed
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change_ok = true;
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// if a via has its drill value changed, force change
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if( initial_drill != new_drill )
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change_ok = true;
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}
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if( change_ok )
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@ -1,10 +1,10 @@
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/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2012 Jean-Pierre Charras, jean-pierre.charras@ujf-grenoble.fr
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* Copyright (C) 2015 Jean-Pierre Charras, jean-pierre.charras@ujf-grenoble.fr
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* Copyright (C) 2012 SoftPLC Corporation, Dick Hollenbeck <dick@softplc.com>
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* Copyright (C) 2012 Wayne Stambaugh <stambaughw@verizon.net>
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* Copyright (C) 1992-2012 KiCad Developers, see AUTHORS.txt for contributors.
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* Copyright (C) 1992-2015 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -97,15 +97,16 @@ bool PCB_EDIT_FRAME::Other_Layer_Route( TRACK* aTrack, wxDC* DC )
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VIA* via = new VIA( GetBoard() );
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via->SetFlags( IS_NEW );
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via->SetViaType( GetDesignSettings().m_CurrentViaType );
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via->SetWidth( GetDesignSettings().GetCurrentViaSize());
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via->SetNetCode( GetBoard()->GetHighLightNetCode() );
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via->SetEnd( g_CurrentTrackSegment->GetEnd() );
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via->SetStart( g_CurrentTrackSegment->GetEnd() );
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via->SetPosition( g_CurrentTrackSegment->GetEnd() );
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// for microvias, the size and hole will be changed later.
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via->SetWidth( GetDesignSettings().GetCurrentViaSize());
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via->SetDrill( GetDesignSettings().GetCurrentViaDrill() );
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// Usual via is from copper to component.
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// layer pair is B_Cu and F_Cu.
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via->SetLayerPair( B_Cu, F_Cu );
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via->SetDrill( GetDesignSettings().GetCurrentViaDrill() );
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LAYER_ID first_layer = GetActiveLayer();
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LAYER_ID last_layer;
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@ -135,13 +136,14 @@ bool PCB_EDIT_FRAME::Other_Layer_Route( TRACK* aTrack, wxDC* DC )
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last_layer = B_Cu;
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else if( first_layer == In1_Cu )
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last_layer = F_Cu;
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// else error: will be removed later
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via->SetLayerPair( first_layer, last_layer );
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{
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NETINFO_ITEM* net = via->GetNet();
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via->SetWidth( net->GetMicroViaSize() );
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}
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// Update diameter and hole size, which where set previously
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// for normal vias
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NETINFO_ITEM* net = via->GetNet();
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via->SetWidth( net->GetMicroViaSize() );
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via->SetDrill( net->GetMicroViaDrillSize() );
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}
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break;
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