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Handle arcs dp coupling 

Calculate coupled arcs and spacing

Fixes https://gitlab.com/kicad/code/kicad/-/issues/17967
This commit is contained in:
Seth Hillbrand 2024-05-30 16:10:39 -07:00
parent bffbdad9c0
commit 75ab3d9e8b
6 changed files with 2191 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
libs/kimath/include/geometry/shape_arc.h
View File

@ -259,10 +259,7 @@ public:
return v1.Cross( v2 ) > 0;
}
bool IsClockwise() const
{
return !IsCCW();
}
bool IsClockwise() const { return !IsCCW(); }
private:
void update_values();

184
pcbnew/drc/drc_test_provider_diff_pair_coupling.cpp
View File

@ -122,6 +122,76 @@ static bool commonParallelProjection( SEG p, SEG n, SEG &pClip, SEG& nClip )
}
static bool commonParallelProjection( const PCB_ARC& p, const PCB_ARC& n, SHAPE_ARC &pClip, SHAPE_ARC& nClip )
{
VECTOR2I p_center = p.GetCenter();
VECTOR2I n_center = n.GetCenter();
double p_radius = p.GetRadius();
double n_radius = n.GetRadius();
VECTOR2I p_start( p.GetStart() );
VECTOR2I p_end( p.GetEnd() );
if( p.IsCCW() )
std::swap( p_start, p_end );
VECTOR2I n_start( n.GetStart() );
VECTOR2I n_end( n.GetEnd() );
if( n.IsCCW() )
std::swap( n_start, n_end );
SHAPE_ARC p_arc( p_start, p.GetMid(), p_end, 0 );
SHAPE_ARC n_arc( n_start, n.GetMid(), n_end, 0 );
EDA_ANGLE p_start_angle = p_arc.GetStartAngle();
// Rotate the arcs to a common 0 starting angle
p_arc.Rotate( -p_start_angle, p_center );
n_arc.Rotate( -p_start_angle, n_center );
EDA_ANGLE p_end_angle = p_arc.GetEndAngle();
EDA_ANGLE n_start_angle = n_arc.GetStartAngle();
EDA_ANGLE n_end_angle = n_arc.GetEndAngle();
EDA_ANGLE clip_total_angle;
EDA_ANGLE clip_start_angle;
if( n_start_angle > p_end_angle )
{
// n is fully outside of p
if( n_end_angle > p_end_angle )
return false;
// n starts before angle 0 and ends in the middle of p
clip_total_angle = n_end_angle + p_start_angle;
clip_start_angle = p_start_angle;
}
else
{
clip_start_angle = n_start_angle + p_start_angle;
// n is fully inside of p
if( n_end_angle < p_end_angle )
clip_total_angle = n_end_angle - n_start_angle;
else // n starts after 0 and ends after p
clip_total_angle = p_end_angle - n_start_angle;
}
VECTOR2I n_start_pt = n_center + VECTOR2I( KiROUND( n_radius ), 0 );
VECTOR2I p_start_pt = p_center + VECTOR2I( KiROUND( p_radius ), 0 );
RotatePoint( n_start_pt, n_center, clip_start_angle );
RotatePoint( p_start_pt, p_center, clip_start_angle );
pClip = SHAPE_ARC( p_center, p_start_pt, clip_start_angle );
nClip = SHAPE_ARC( n_center, n_start_pt, clip_start_angle );
return true;
}
struct DIFF_PAIR_KEY
{
bool operator<( const DIFF_PAIR_KEY& b ) const
@ -160,6 +230,9 @@ struct DIFF_PAIR_COUPLED_SEGMENTS
{
SEG coupledN;
SEG coupledP;
bool isArc;
SHAPE_ARC coupledArcN;
SHAPE_ARC coupledArcP;
PCB_TRACK* parentN;
PCB_TRACK* parentP;
int computedGap;
@ -168,6 +241,7 @@ struct DIFF_PAIR_COUPLED_SEGMENTS
bool couplingFailMax;
DIFF_PAIR_COUPLED_SEGMENTS() :
isArc( false ),
parentN( nullptr ),
parentP( nullptr ),
computedGap( 0 ),
@ -224,11 +298,95 @@ static void extractDiffPairCoupledItems( DIFF_PAIR_ITEMS& aDp )
cpair.parentP = sp;
cpair.parentN = sn;
cpair.layer = sp->GetLayer();
cpair.computedGap = (cpair.coupledP.A - cpair.coupledN.A).EuclideanNorm();
cpair.computedGap -= ( sp->GetWidth() + sn->GetWidth() ) / 2;
int gap = (cpair.coupledP.A - cpair.coupledN.A).EuclideanNorm();
if( gap < bestGap )
if( cpair.computedGap < bestGap )
{
bestGap = gap;
bestGap = cpair.computedGap;
bestCoupled = cpair;
}
}
}
}
if( bestCoupled )
{
auto excludeSelf = [&]( BOARD_ITEM* aItem )
{
if( aItem == bestCoupled->parentN || aItem == bestCoupled->parentP )
return false;
if( aItem->Type() == PCB_TRACE_T || aItem->Type() == PCB_VIA_T
|| aItem->Type() == PCB_ARC_T )
{
BOARD_CONNECTED_ITEM* bci = static_cast<BOARD_CONNECTED_ITEM*>( aItem );
if( bci->GetNetCode() == bestCoupled->parentN->GetNetCode()
|| bci->GetNetCode() == bestCoupled->parentP->GetNetCode() )
{
return false;
}
}
return true;
};
SHAPE_SEGMENT checkSegStart( bestCoupled->coupledP.A, bestCoupled->coupledN.A );
SHAPE_SEGMENT checkSegEnd( bestCoupled->coupledP.B, bestCoupled->coupledN.B );
DRC_RTREE* tree = bestCoupled->parentP->GetBoard()->m_CopperItemRTreeCache.get();
// check if there's anything in between the segments suspected to be coupled. If
// there's nothing, assume they are really coupled.
if( !tree->CheckColliding( &checkSegStart, sp->GetLayer(), 0, excludeSelf )
&& !tree->CheckColliding( &checkSegEnd, sp->GetLayer(), 0, excludeSelf ) )
{
aDp.coupled.push_back( *bestCoupled );
}
}
}
for( BOARD_CONNECTED_ITEM* itemP : aDp.itemsP )
{
PCB_ARC* sp = dyn_cast<PCB_ARC*>( itemP );
std::optional<DIFF_PAIR_COUPLED_SEGMENTS> bestCoupled;
int bestGap = std::numeric_limits<int>::max();
if( !sp )
continue;
for ( BOARD_CONNECTED_ITEM* itemN : aDp.itemsN )
{
PCB_ARC* sn = dyn_cast<PCB_ARC*> ( itemN );
if( !sn )
continue;
if( ( sn->GetLayerSet() & sp->GetLayerSet() ).none() )
continue;
// Segments that are ~ 1 IU in length per side are approximately parallel (tolerance is 1 IU)
// with everything and their parallel projection is < 1 IU, leading to bad distance calculations
if( sp->GetLength() > 2 && sn->GetLength() > 2 && ( sp->GetCenter() - sn->GetCenter() ).SquaredEuclideanNorm() < 4 )
{
DIFF_PAIR_COUPLED_SEGMENTS cpair;
cpair.isArc = true;
bool coupled = commonParallelProjection( *sp, *sn, cpair.coupledArcP, cpair.coupledArcN );
if( coupled )
{
cpair.parentP = sp;
cpair.parentN = sn;
cpair.layer = sp->GetLayer();
cpair.computedGap = KiROUND( std::abs( cpair.coupledArcP.GetRadius()
- cpair.coupledArcN.GetRadius() ) );
cpair.computedGap -= ( sp->GetWidth() + sn->GetWidth() ) / 2;
if( cpair.computedGap < bestGap )
{
bestGap = cpair.computedGap;
bestCoupled = cpair;
}
}
@ -244,7 +402,7 @@ static void extractDiffPairCoupledItems( DIFF_PAIR_ITEMS& aDp )
if( aItem == bestCoupled->parentN || aItem == bestCoupled->parentP )
return false;
if( aItem->Type() == PCB_TRACE_T || aItem->Type() == PCB_VIA_T )
if( aItem->Type() == PCB_TRACE_T || aItem->Type() == PCB_VIA_T || aItem->Type() == PCB_ARC_T )
{
BOARD_CONNECTED_ITEM* bci = static_cast<BOARD_CONNECTED_ITEM*>( aItem );
@ -375,30 +533,22 @@ bool test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run()
for( BOARD_CONNECTED_ITEM* item : itemSet.itemsN )
{
// fixme: include vias
if( PCB_TRACK* track = dyn_cast<PCB_TRACK*>( item ) )
if( PCB_TRACK* track = dynamic_cast<PCB_TRACK*>( item ) )
itemSet.totalLengthN += track->GetLength();
}
for( BOARD_CONNECTED_ITEM* item : itemSet.itemsP )
{
// fixme: include vias
if( PCB_TRACK* track = dyn_cast<PCB_TRACK*>( item ) )
if( PCB_TRACK* track = dynamic_cast<PCB_TRACK*>( item ) )
itemSet.totalLengthP += track->GetLength();
}
for( DIFF_PAIR_COUPLED_SEGMENTS& dp : itemSet.coupled )
{
int length = dp.coupledN.Length();
int gap = dp.coupledN.Distance( dp.coupledP );
wxCHECK2( dp.parentN && dp.parentP, continue );
gap -= dp.parentN->GetWidth() / 2;
gap -= dp.parentP->GetWidth() / 2;
dp.computedGap = gap;
std::shared_ptr<KIGFX::VIEW_OVERLAY> overlay = m_drcEngine->GetDebugOverlay();
if( overlay )
@ -414,21 +564,21 @@ bool test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run()
drc_dbg( 10, wxT( " len %d gap %d l %d\n" ),
length,
gap,
dp.computedGap,
dp.parentP->GetLayer() );
if( key.gapConstraint )
{
if( key.gapConstraint->HasMin()
&& key.gapConstraint->Min() >= 0
&& ( gap < key.gapConstraint->Min() - epsilon ) )
&& ( dp.computedGap < key.gapConstraint->Min() - epsilon ) )
{
dp.couplingFailMin = true;
}
if( key.gapConstraint->HasMax()
&& key.gapConstraint->Max() >= 0
&& ( gap > key.gapConstraint->Max() + epsilon ) )
&& ( dp.computedGap > key.gapConstraint->Max() + epsilon ) )
{
dp.couplingFailMax = true;
}

28
qa/data/pcbnew/issue17967/issue17967.kicad_dru Normal file
View File

@ -0,0 +1,28 @@
(version 1)
(rule "csi_outer"
(layer outer)
(condition "(A.NetClass == 'csi_diff100R')")
(constraint track_width (opt 0.065mm))
(constraint diff_pair_gap (min "0.065mm") (opt 0.15mm) (max "0.35mm"))
(constraint diff_pair_uncoupled (max 15mm))
)
(rule "csi_clearance"
(layer outer)
(condition "(A.NetClass == 'csi_diff100R' && !AB.isCoupledDiffPair() && A.Type == 'Track' && B.Type == 'Track')")
(constraint clearance (min 0.3mm))
)
(rule "csi_GND_clearance"
(layer outer)
(condition "A.NetClass == 'csi_diff100R' && B.NetName == 'GND'")
(constraint clearance (min 0.15mm))
)
(rule "connector_clearance"
(condition "(A.Type == 'Pad' || A.Type == 'Via') && ( A.insideCourtyard('J1') || A.insideCourtyard('J2') || A.insideCourtyard('J3')) ")
(constraint clearance (min 0.15mm))
)

1291
qa/data/pcbnew/issue17967/issue17967.kicad_pcb Normal file
View File

File diff suppressed because it is too large Load Diff

702
qa/data/pcbnew/issue17967/issue17967.kicad_pro Normal file
View File

@ -0,0 +1,702 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"apply_defaults_to_fp_fields": false,
"apply_defaults_to_fp_shapes": false,
"apply_defaults_to_fp_text": false,
"board_outline_line_width": 0.1,
"copper_line_width": 0.2,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.05,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.1,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.15,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.0,
"height": 0.4,
"width": 0.46
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.15
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_symbol_mismatch": "warning",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"hole_to_hole": "warning",
"holes_co_located": "warning",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "ignore",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.127,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.2,
"min_hole_clearance": 0.127,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.2,
"min_microvia_drill": 0.1,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.8,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.15,
"min_track_width": 0.052,
"min_via_annular_width": 0.1,
"min_via_diameter": 0.35,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": true,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 10,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 10,
"td_height_ratio": 1.0,
"td_length_ratio": 1.0,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0,
0.065,
0.072,
0.095,
0.101,
0.15,
0.2,
0.25,
0.3,
0.3556,
0.38,
0.4064,
0.51,
0.6,
0.8,
1.0,
1.5,
2.0
],
"tuning_pattern_settings": {
"diff_pair_defaults": {
"corner_radius_percentage": 100,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.1,
"single_sided": false,
"spacing": 0.6
},
"diff_pair_skew_defaults": {
"corner_radius_percentage": 100,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.1,
"single_sided": false,
"spacing": 0.6
},
"single_track_defaults": {
"corner_radius_percentage": 100,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.1,
"single_sided": false,
"spacing": 0.6
}
},
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.35,
"drill": 0.15
},
{
"diameter": 0.4,
"drill": 0.2
},
{
"diameter": 0.45,
"drill": 0.25
},
{
"diameter": 0.55,
"drill": 0.3
}
],
"zones_allow_external_fillets": true,
"zones_use_no_outline": true
},
"ipc2581": {
"dist": "",
"distpn": "",
"internal_id": "",
"mfg": "",
"mpn": ""
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
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],
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[
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],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "issue17967.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.15,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.072,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.076,
"via_diameter": 0.4,
"via_drill": 0.2,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.15,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.072,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "PWR",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.5,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.15,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.072,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Signal",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"via_diameter": 0.45,
"via_drill": 0.25,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.15,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.065,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "csi_diff100R",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.065,
"via_diameter": 0.45,
"via_drill": 0.25,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "csi_diff100R",
"pattern": ".*_[PN]"
}
]
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"plot": "",
"pos_files": "",
"specctra_dsn": "",
"step": "",
"svg": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"bom_fmt_presets": [],
"bom_fmt_settings": {
"field_delimiter": ",",
"keep_line_breaks": false,
"keep_tabs": false,
"name": "CSV",
"ref_delimiter": ",",
"ref_range_delimiter": "",
"string_delimiter": "\""
},
"bom_presets": [],
"bom_settings": {
"exclude_dnp": false,
"fields_ordered": [
{
"group_by": false,
"label": "Reference",
"name": "Reference",
"show": true
},
{
"group_by": true,
"label": "Value",
"name": "Value",
"show": true
},
{
"group_by": false,
"label": "Datasheet",
"name": "Datasheet",
"show": true
},
{
"group_by": false,
"label": "Footprint",
"name": "Footprint",
"show": true
},
{
"group_by": false,
"label": "Qty",
"name": "${QUANTITY}",
"show": true
},
{
"group_by": true,
"label": "DNP",
"name": "${DNP}",
"show": true
}
],
"filter_string": "",
"group_symbols": true,
"name": "Grouped By Value",
"sort_asc": true,
"sort_field": "位号"
},
"connection_grid_size": 50.0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"operating_point_overlay_i_precision": 3,
"operating_point_overlay_i_range": "~A",
"operating_point_overlay_v_precision": 3,
"operating_point_overlay_v_range": "~V",
"overbar_offset_ratio": 1.23,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_dissipations": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"811c9aa7-2999-4b11-a823-3df1e2e79d8b",
"根目录"
]
],
"text_variables": {}
}

3
qa/tests/pcbnew/drc/test_drc_regressions.cpp
View File

@ -141,7 +141,8 @@ BOOST_FIXTURE_TEST_CASE( DRCFalseNegativeRegressions, DRC_REGRESSION_TEST_FIXTUR
{ "issue16566", 6 }, // Pad_Shape vs Shape property
{ "reverse_via", 3 }, // Via/track ordering
{ "intersectingzones", 1 }, // zones are too close to each other
{ "fill_bad", 1 } // zone max BBox was too small
{ "fill_bad", 1 }, // zone max BBox was too small
{ "issue17967/issue17967", 1} // Arc dp coupling
};
for( const auto& [testName, expectedErrors] : tests )