MenuText() tweaks, beautification
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parent
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commit
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@ -26,10 +26,16 @@ email address.
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2007-Oct-10 UPDATE Dick Hollenbeck <dick@softplc.com>
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2007-Oct-10 UPDATE Dick Hollenbeck <dick@softplc.com>
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================================================================================
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================================================================================
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+ pcbnew
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+ pcbnew
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* prevent OnRightClick() from calling PcbGeneralLocateAndDisplay() when creating
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* bug fix: prevent OnRightClick() from calling PcbGeneralLocateAndDisplay()
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a new track.
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when creating a new track.
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* bug fix: popup menu was not handling Mires, because the collector was not
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* bug fix: popup menu was not handling Mires, because the collector was not
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being asked to find them.
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being asked to find them.
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* added TRACK::ShowWidth() and call it from BOARD_ITEM::MenuText(). There was
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not enough information in Selection Clarification at a busy junction to
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make a reasonable choice.
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* SEGVIA::MenuText() shows via width, rather than net_code.
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* Beautified ratsnets.cpp, I would like to understand it better. It would help
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if the comments were in English.
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+ all
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+ all
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* Changed English UI text "Mire" to "Target" according to this post:
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* Changed English UI text "Mire" to "Target" according to this post:
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http://tech.groups.yahoo.com/group/kicad-users/message/1380
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http://tech.groups.yahoo.com/group/kicad-users/message/1380
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@ -438,12 +438,10 @@ void valeur_param( int valeur, wxString& buf_texte )
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{
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{
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if( g_UnitMetric )
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if( g_UnitMetric )
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{
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{
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buf_texte.Printf( wxT( "%3.3f " ), (float) valeur * 0.00254 );
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buf_texte.Printf( wxT( "%3.3f mm" ), valeur * 0.00254 );
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buf_texte << wxT( "mm" );
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}
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}
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else
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else
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{
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{
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buf_texte.Printf( wxT( "%2.4f " ), (float) valeur * 0.0001 );
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buf_texte.Printf( wxT( "%2.4f \"" ), valeur * 0.0001 );
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buf_texte << wxT( "\" " );
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}
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}
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}
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}
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@ -1369,7 +1369,7 @@ private:
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/**
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/**
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* Struct MsgItem
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* Struct MsgItem
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* is used privately by WinEDA_MsgPanel as the item type its vector.
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* is used privately by WinEDA_MsgPanel as the item type of its vector.
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* These items are the pairs of text strings shown in the MsgPanel.
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* These items are the pairs of text strings shown in the MsgPanel.
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*/
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*/
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struct MsgItem
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struct MsgItem
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@ -124,8 +124,8 @@ wxString BOARD_ITEM::MenuText( const BOARD* aPcb ) const
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break;
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break;
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case TYPETRACK:
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case TYPETRACK:
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text << _( "Track" ) << wxT( " " );
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text << _( "Track" ) << wxT( " " ) << ((TRACK*)item)->ShowWidth();
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net = aPcb->FindNet( ( (TRACK*) item )->m_NetCode );
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net = aPcb->FindNet( ((TRACK*)item)->m_NetCode );
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if( net )
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if( net )
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{
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{
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text << wxT( " [" ) << net->m_Netname << wxT( "]" );
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text << wxT( " [" ) << net->m_Netname << wxT( "]" );
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@ -151,7 +151,7 @@ wxString BOARD_ITEM::MenuText( const BOARD* aPcb ) const
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case TYPEVIA:
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case TYPEVIA:
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{
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{
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SEGVIA* via = (SEGVIA*) item;
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SEGVIA* via = (SEGVIA*) item;
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text << _( "Via" ) << wxT( " " ) << via->m_NetCode;
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text << _( "Via" ) << wxT( " " ) << via->ShowWidth();
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int shape = via->Shape();
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int shape = via->Shape();
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if( shape == VIA_ENTERREE )
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if( shape == VIA_ENTERREE )
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@ -35,6 +35,26 @@ TRACK::TRACK( BOARD_ITEM* StructFather, KICAD_T idtype ) :
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}
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}
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wxString TRACK::ShowWidth()
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{
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wxString msg;
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#if 0
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double value = To_User_Unit( g_UnitMetric, m_Width, PCB_INTERNAL_UNIT );
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if( g_UnitMetric == INCHES ) // Affichage en mils
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msg.Printf( wxT( "%.1f" ), value * 1000 );
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else
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msg.Printf( wxT( "%.3f" ), value );
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#else
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valeur_param( m_Width, msg );
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#endif
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return msg;
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}
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SEGZONE::SEGZONE( BOARD_ITEM* StructFather ) :
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SEGZONE::SEGZONE( BOARD_ITEM* StructFather ) :
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TRACK( StructFather, TYPEZONE )
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TRACK( StructFather, TYPEZONE )
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@ -119,6 +119,12 @@ public:
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void Display_Infos( WinEDA_DrawFrame* frame );
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void Display_Infos( WinEDA_DrawFrame* frame );
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/**
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* Function ShowWidth
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* returns the width of the track in displayable user units.
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*/
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wxString ShowWidth();
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/**
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/**
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* Function Visit
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* Function Visit
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* is re-implemented here because TRACKs and SEGVIAs are in the same list
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* is re-implemented here because TRACKs and SEGVIAs are in the same list
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@ -132,12 +132,7 @@ void WinEDA_PcbFrame::OnLeftClick( wxDC* DC, const wxPoint& MousePos )
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break;
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break;
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case ID_PCB_SHOW_1_RATSNEST_BUTT:
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case ID_PCB_SHOW_1_RATSNEST_BUTT:
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#if 0
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DrawStruct = m_Pcb->FindPadOrModule( GetScreen()->RefPos(true),
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GetScreen()->m_Active_Layer );
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#else
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DrawStruct = PcbGeneralLocateAndDisplay();
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DrawStruct = PcbGeneralLocateAndDisplay();
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#endif
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Show_1_Ratsnest( DrawStruct, DC );
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Show_1_Ratsnest( DrawStruct, DC );
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if( DrawStruct )
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if( DrawStruct )
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@ -44,7 +44,9 @@ void WinEDA_BasePcbFrame::Compile_Ratsnest( wxDC* DC, bool display_status_pcb )
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/* construction de la liste des coordonnées des pastilles */
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/* construction de la liste des coordonnées des pastilles */
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m_Pcb->m_Status_Pcb = 0; /* réinit total du calcul */
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m_Pcb->m_Status_Pcb = 0; /* réinit total du calcul */
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build_liste_pads();
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build_liste_pads();
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MsgPanel->EraseMsgBox(); /* effacement du bas d'ecran */
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MsgPanel->EraseMsgBox(); /* effacement du bas d'ecran */
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msg.Printf( wxT( " %d" ), m_Pcb->m_NbPads );
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msg.Printf( wxT( " %d" ), m_Pcb->m_NbPads );
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Affiche_1_Parametre( this, 1, wxT( "pads" ), msg, RED );
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Affiche_1_Parametre( this, 1, wxT( "pads" ), msg, RED );
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@ -52,11 +54,13 @@ void WinEDA_BasePcbFrame::Compile_Ratsnest( wxDC* DC, bool display_status_pcb )
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Affiche_1_Parametre( this, 8, wxT( "Nets" ), msg, CYAN );
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Affiche_1_Parametre( this, 8, wxT( "Nets" ), msg, CYAN );
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reattribution_reference_piste( display_status_pcb );
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reattribution_reference_piste( display_status_pcb );
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Build_Board_Ratsnest( DC ); /* calcul du chevelu general */
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Build_Board_Ratsnest( DC ); /* calcul du chevelu general */
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test_connexions( DC ); /* determine les blocks de pads connectés par
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test_connexions( DC ); /* determine les blocks de pads connectés par
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* les pistes existantes */
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* les pistes existantes */
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Tst_Ratsnest( DC, 0 ); /* calcul du chevelu actif */
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Tst_Ratsnest( DC, 0 ); /* calcul du chevelu actif */
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// Reaffichage des chevelus actifs
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// Reaffichage des chevelus actifs
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if( g_Show_Ratsnest )
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if( g_Show_Ratsnest )
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@ -68,19 +72,25 @@ void WinEDA_BasePcbFrame::Compile_Ratsnest( wxDC* DC, bool display_status_pcb )
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/*****************************************************************/
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/*****************************************************************/
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static int tri_par_net( LISTE_PAD* pt_ref, LISTE_PAD* pt_compare )
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static int tri_par_net( const void* o1, const void* o2 )
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/****************************************************************/
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/****************************************************************/
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/* routine utilisee par la foncion QSORT */
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/* routine utilisee par la foncion QSORT */
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{
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{
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LISTE_PAD* pt_ref = (LISTE_PAD*) o1;
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LISTE_PAD* pt_compare = (LISTE_PAD*) o2;
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return (*pt_ref)->m_NetCode - (*pt_compare)->m_NetCode;
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return (*pt_ref)->m_NetCode - (*pt_compare)->m_NetCode;
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}
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}
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/********************************************************/
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/********************************************************/
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static int sort_by_length( CHEVELU* ref, CHEVELU* compare )
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static int sort_by_length( const void* o1, const void* o2 )
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/********************************************************/
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/********************************************************/
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/* routine de tri par longueur des chevelus utilisee par la foncion QSORT */
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/* routine de tri par longueur des chevelus utilisee par la foncion QSORT */
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{
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{
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CHEVELU* ref = (CHEVELU*) o1;
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CHEVELU* compare = (CHEVELU*) o2;
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return ref->dist - compare->dist;
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return ref->dist - compare->dist;
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}
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}
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@ -108,12 +118,15 @@ static int gen_rats_block_to_block( WinEDA_DrawPanel* DrawPanel, wxDC* DC,
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{
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{
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int dist_min, current_dist;
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int dist_min, current_dist;
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int current_num_block = 1;
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int current_num_block = 1;
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LISTE_PAD* pt_liste_pad_tmp,
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LISTE_PAD* pt_liste_pad_tmp;
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* pt_liste_pad_aux,
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LISTE_PAD* pt_liste_pad_aux;
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* pt_liste_pad_block1 = NULL,
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LISTE_PAD* pt_liste_pad_block1 = NULL;
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* pt_start_liste;
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LISTE_PAD* pt_start_liste;
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pt_liste_pad_tmp = NULL; dist_min = 0x7FFFFFFF;
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pt_liste_pad_tmp = NULL;
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dist_min = 0x7FFFFFFF;
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pt_start_liste = pt_liste_pad;
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pt_start_liste = pt_liste_pad;
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if( DC )
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if( DC )
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@ -123,14 +136,17 @@ static int gen_rats_block_to_block( WinEDA_DrawPanel* DrawPanel, wxDC* DC,
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for( ; pt_liste_pad < pt_limite; pt_liste_pad++ )
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for( ; pt_liste_pad < pt_limite; pt_liste_pad++ )
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{
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{
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D_PAD* ref_pad = *pt_liste_pad;
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D_PAD* ref_pad = *pt_liste_pad;
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if( ref_pad->m_logical_connexion != 1 )
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if( ref_pad->m_logical_connexion != 1 )
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continue;
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continue;
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for( pt_liste_pad_aux = pt_start_liste; ; pt_liste_pad_aux++ )
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for( pt_liste_pad_aux = pt_start_liste; ; pt_liste_pad_aux++ )
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{
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{
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D_PAD* curr_pad = *pt_liste_pad_aux;
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D_PAD* curr_pad = *pt_liste_pad_aux;
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if( pt_liste_pad_aux >= pt_limite )
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if( pt_liste_pad_aux >= pt_limite )
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break;
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break;
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if( curr_pad->m_logical_connexion == 1 )
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if( curr_pad->m_logical_connexion == 1 )
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continue;
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continue;
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@ -221,19 +237,23 @@ static int gen_rats_pad_to_pad( WinEDA_DrawPanel* DrawPanel, wxDC* DC,
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for( ; pt_liste_pad < pt_limite; pt_liste_pad++ )
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for( ; pt_liste_pad < pt_limite; pt_liste_pad++ )
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{
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{
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ref_pad = *pt_liste_pad;
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ref_pad = *pt_liste_pad;
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if( ref_pad->m_logical_connexion )
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if( ref_pad->m_logical_connexion )
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continue; // Pad deja connecte
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continue; // Pad deja connecte
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pt_liste_pad_tmp = NULL; dist_min = 0x7FFFFFFF;
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pt_liste_pad_tmp = NULL;
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dist_min = 0x7FFFFFFF;
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for( pt_liste_pad_aux = pt_start_liste; ; pt_liste_pad_aux++ )
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for( pt_liste_pad_aux = pt_start_liste; ; pt_liste_pad_aux++ )
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{
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{
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if( pt_liste_pad_aux >= pt_limite )
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if( pt_liste_pad_aux >= pt_limite )
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break;
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break;
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if( pt_liste_pad_aux == pt_liste_pad )
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if( pt_liste_pad_aux == pt_liste_pad )
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continue;
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continue;
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pad = *pt_liste_pad_aux;
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pad = *pt_liste_pad_aux;
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/* Comparaison des distances des pastilles (calcul simplifie) */
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/* Comparaison des distances des pastilles (calcul simplifie) */
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current_dist =
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current_dist =
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abs( pad->m_Pos.x - ref_pad->m_Pos.x )
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abs( pad->m_Pos.x - ref_pad->m_Pos.x )
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@ -263,6 +283,7 @@ static int gen_rats_pad_to_pad( WinEDA_DrawPanel* DrawPanel, wxDC* DC,
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{
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{
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ref_pad->m_logical_connexion = pad->m_logical_connexion;
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ref_pad->m_logical_connexion = pad->m_logical_connexion;
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}
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}
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(*nblinks)++;
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(*nblinks)++;
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g_pt_chevelu->m_NetCode = ref_pad->m_NetCode;
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g_pt_chevelu->m_NetCode = ref_pad->m_NetCode;
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g_pt_chevelu->status = CH_ACTIF | CH_VISIBLE;
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g_pt_chevelu->status = CH_ACTIF | CH_VISIBLE;
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@ -335,15 +356,14 @@ void WinEDA_BasePcbFrame::Build_Board_Ratsnest( wxDC* DC )
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recalcule_pad_net_code();
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recalcule_pad_net_code();
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pt_liste_pad = m_Pcb->m_Pads;
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pt_liste_pad = m_Pcb->m_Pads;
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for( ii = m_Pcb->m_NbPads; ii > 0; pt_liste_pad++, ii-- )
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for( ii = m_Pcb->m_NbPads; ii > 0; pt_liste_pad++, ii-- )
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{
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{
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pad = *pt_liste_pad;
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pad = *pt_liste_pad;
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pad->m_logical_connexion = 0;
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pad->m_logical_connexion = 0;
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}
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}
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/* classement des pointeurs sur pads par nets */
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/* classement des pointeurs sur pads par nets */
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qsort( m_Pcb->m_Pads, m_Pcb->m_NbPads, sizeof(LISTE_PAD),
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qsort( m_Pcb->m_Pads, m_Pcb->m_NbPads, sizeof(LISTE_PAD), tri_par_net );
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( int( * ) ( const void*, const void* ) )tri_par_net );
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/* Allocation memoire du buffer des chevelus: il y a nb_nodes - 1 chevelu
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/* Allocation memoire du buffer des chevelus: il y a nb_nodes - 1 chevelu
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* au maximum ( 1 node = 1 pad connecte ).
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* au maximum ( 1 node = 1 pad connecte ).
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@ -429,7 +449,7 @@ void WinEDA_BasePcbFrame::Build_Board_Ratsnest( wxDC* DC )
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qsort( equipot->m_RatsnestStart,
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qsort( equipot->m_RatsnestStart,
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equipot->m_RatsnestEnd - equipot->m_RatsnestStart,
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equipot->m_RatsnestEnd - equipot->m_RatsnestStart,
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sizeof(CHEVELU),
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sizeof(CHEVELU),
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( int( * ) ( const void*, const void* ) )sort_by_length );
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sort_by_length );
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}
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}
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pt_liste_pad = pt_start_liste = pt_end_liste;
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pt_liste_pad = pt_start_liste = pt_end_liste;
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pt_deb_liste_ch = g_pt_chevelu;
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pt_deb_liste_ch = g_pt_chevelu;
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@ -498,6 +518,7 @@ void WinEDA_BasePcbFrame::DrawGeneralRatsnest( wxDC* DC, int net_code )
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{
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{
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if( ( Chevelu->status & (CH_VISIBLE | CH_ACTIF) ) != (CH_VISIBLE | CH_ACTIF) )
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if( ( Chevelu->status & (CH_VISIBLE | CH_ACTIF) ) != (CH_VISIBLE | CH_ACTIF) )
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continue;
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continue;
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if( (net_code <= 0) || (net_code == Chevelu->m_NetCode) )
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if( (net_code <= 0) || (net_code == Chevelu->m_NetCode) )
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{
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{
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GRLine( &DrawPanel->m_ClipBox, DC,
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GRLine( &DrawPanel->m_ClipBox, DC,
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@ -545,6 +566,7 @@ static int tst_rats_block_to_block( WinEDA_DrawPanel* DrawPanel, wxDC* DC,
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{
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{
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if( chevelu->pad_start->m_logical_connexion == chevelu->pad_end->m_logical_connexion )
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if( chevelu->pad_start->m_logical_connexion == chevelu->pad_end->m_logical_connexion )
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continue;
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continue;
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if( min_chevelu == NULL )
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if( min_chevelu == NULL )
|
||||||
min_chevelu = chevelu;
|
min_chevelu = chevelu;
|
||||||
else if( min_chevelu->dist > chevelu->dist )
|
else if( min_chevelu->dist > chevelu->dist )
|
||||||
|
@ -557,6 +579,7 @@ static int tst_rats_block_to_block( WinEDA_DrawPanel* DrawPanel, wxDC* DC,
|
||||||
min_chevelu->status |= CH_ACTIF;
|
min_chevelu->status |= CH_ACTIF;
|
||||||
current_num_block = min_chevelu->pad_start->m_logical_connexion;
|
current_num_block = min_chevelu->pad_start->m_logical_connexion;
|
||||||
min_block = min_chevelu->pad_end->m_logical_connexion;
|
min_block = min_chevelu->pad_end->m_logical_connexion;
|
||||||
|
|
||||||
if( min_block > current_num_block )
|
if( min_block > current_num_block )
|
||||||
EXCHG( min_block, current_num_block );
|
EXCHG( min_block, current_num_block );
|
||||||
|
|
||||||
|
@ -657,6 +680,7 @@ void WinEDA_BasePcbFrame::Tst_Ratsnest( wxDC* DC, int ref_netcode )
|
||||||
equipot = m_Pcb->FindNet( net_code );
|
equipot = m_Pcb->FindNet( net_code );
|
||||||
if( equipot == NULL )
|
if( equipot == NULL )
|
||||||
break;
|
break;
|
||||||
|
|
||||||
if( ref_netcode && (net_code != ref_netcode) )
|
if( ref_netcode && (net_code != ref_netcode) )
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
|
@ -741,15 +765,19 @@ void WinEDA_BasePcbFrame::recalcule_pad_net_code()
|
||||||
{
|
{
|
||||||
if( (*pad_courant)->m_Netname.IsEmpty() ) // pad non connecte
|
if( (*pad_courant)->m_Netname.IsEmpty() ) // pad non connecte
|
||||||
{
|
{
|
||||||
(*pad_courant)->m_NetCode = 0; continue;
|
(*pad_courant)->m_NetCode = 0;
|
||||||
|
continue;
|
||||||
}
|
}
|
||||||
|
|
||||||
m_Pcb->m_NbNodes++;
|
m_Pcb->m_NbNodes++;
|
||||||
|
|
||||||
/* si le netname a deja ete rencontre: mise a jour , sinon nouveau net_code */
|
/* si le netname a deja ete rencontre: mise a jour , sinon nouveau net_code */
|
||||||
pad_ref = m_Pcb->m_Pads;
|
pad_ref = m_Pcb->m_Pads;
|
||||||
while( pad_ref < pad_courant )
|
while( pad_ref < pad_courant )
|
||||||
{
|
{
|
||||||
if( (*pad_ref)->m_Netname == (*pad_courant)->m_Netname )
|
if( (*pad_ref)->m_Netname == (*pad_courant)->m_Netname )
|
||||||
break; // sont du meme met
|
break; // sont du meme met
|
||||||
|
|
||||||
pad_ref++;
|
pad_ref++;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -770,7 +798,7 @@ void WinEDA_BasePcbFrame::recalcule_pad_net_code()
|
||||||
PtStruct = (EDA_BaseStruct*) m_Pcb;
|
PtStruct = (EDA_BaseStruct*) m_Pcb;
|
||||||
for( ii = 0; ii <= m_Pcb->m_NbNets; ii++ )
|
for( ii = 0; ii <= m_Pcb->m_NbNets; ii++ )
|
||||||
{
|
{
|
||||||
if( pt_equipot == NULL ) /* Creation d'une nouvelle equipot */
|
if( pt_equipot == NULL ) /* Creation d'une nouvelle equipot */
|
||||||
{
|
{
|
||||||
pt_equipot = new EQUIPOT( m_Pcb );
|
pt_equipot = new EQUIPOT( m_Pcb );
|
||||||
|
|
||||||
|
@ -864,11 +892,14 @@ void WinEDA_BasePcbFrame::build_liste_pads()
|
||||||
|
|
||||||
/* construction de la liste des pointeurs sur les structures D_PAD */
|
/* construction de la liste des pointeurs sur les structures D_PAD */
|
||||||
if( m_Pcb->m_Pads )
|
if( m_Pcb->m_Pads )
|
||||||
|
{
|
||||||
MyFree( m_Pcb->m_Pads );
|
MyFree( m_Pcb->m_Pads );
|
||||||
m_Pcb->m_Pads = NULL;
|
m_Pcb->m_Pads = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
/* Calcul du nombre de pads */
|
/* Calcul du nombre de pads */
|
||||||
Module = m_Pcb->m_Modules; m_Pcb->m_NbPads = 0;
|
m_Pcb->m_NbPads = 0;
|
||||||
|
Module = m_Pcb->m_Modules;
|
||||||
for( ; Module != NULL; Module = (MODULE*) Module->Pnext )
|
for( ; Module != NULL; Module = (MODULE*) Module->Pnext )
|
||||||
{
|
{
|
||||||
PtPad = (D_PAD*) Module->m_Pads;
|
PtPad = (D_PAD*) Module->m_Pads;
|
||||||
|
@ -880,8 +911,8 @@ void WinEDA_BasePcbFrame::build_liste_pads()
|
||||||
return;
|
return;
|
||||||
|
|
||||||
/* Allocation memoire du buffer */
|
/* Allocation memoire du buffer */
|
||||||
pt_liste_pad = m_Pcb->m_Pads
|
pt_liste_pad = m_Pcb->m_Pads
|
||||||
= (D_PAD**) MyZMalloc( (m_Pcb->m_NbPads + 1) * sizeof(D_PAD *) );
|
= (D_PAD**) MyZMalloc( (m_Pcb->m_NbPads + 1) * sizeof(D_PAD *) );
|
||||||
m_Pcb->m_NbNodes = 0;
|
m_Pcb->m_NbNodes = 0;
|
||||||
|
|
||||||
/* Initialisation du buffer et des variables de travail */
|
/* Initialisation du buffer et des variables de travail */
|
||||||
|
@ -894,8 +925,10 @@ void WinEDA_BasePcbFrame::build_liste_pads()
|
||||||
*pt_liste_pad = PtPad;
|
*pt_liste_pad = PtPad;
|
||||||
PtPad->m_logical_connexion = 0;
|
PtPad->m_logical_connexion = 0;
|
||||||
PtPad->m_Parent = Module;
|
PtPad->m_Parent = Module;
|
||||||
|
|
||||||
if( PtPad->m_NetCode )
|
if( PtPad->m_NetCode )
|
||||||
m_Pcb->m_NbNodes++;
|
m_Pcb->m_NbNodes++;
|
||||||
|
|
||||||
pt_liste_pad++;
|
pt_liste_pad++;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -903,9 +936,13 @@ void WinEDA_BasePcbFrame::build_liste_pads()
|
||||||
*pt_liste_pad = NULL; // fin de liste
|
*pt_liste_pad = NULL; // fin de liste
|
||||||
|
|
||||||
adr_lowmem = buf_work;
|
adr_lowmem = buf_work;
|
||||||
|
|
||||||
if( m_Pcb->m_Ratsnest )
|
if( m_Pcb->m_Ratsnest )
|
||||||
|
{
|
||||||
MyFree( m_Pcb->m_Ratsnest );
|
MyFree( m_Pcb->m_Ratsnest );
|
||||||
m_Pcb->m_Ratsnest = NULL;
|
m_Pcb->m_Ratsnest = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
m_Pcb->m_Status_Pcb = LISTE_PAD_OK;
|
m_Pcb->m_Status_Pcb = LISTE_PAD_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -929,14 +966,14 @@ char* WinEDA_BasePcbFrame::build_ratsnest_module( wxDC* DC, MODULE* Module )
|
||||||
* Ce chevelu est recalcule a chaque deplacement
|
* Ce chevelu est recalcule a chaque deplacement
|
||||||
*/
|
*/
|
||||||
{
|
{
|
||||||
LISTE_PAD* pt_liste_pad,
|
LISTE_PAD* pt_liste_pad;
|
||||||
* pt_liste_ref,
|
LISTE_PAD* pt_liste_ref;
|
||||||
* pt_liste_generale;
|
LISTE_PAD* pt_liste_generale;
|
||||||
D_PAD* pad_ref,
|
D_PAD* pad_ref;
|
||||||
* pad_externe;
|
D_PAD* pad_externe;
|
||||||
LISTE_PAD* pt_liste_pad_limite,
|
LISTE_PAD* pt_liste_pad_limite;
|
||||||
* pt_start_liste,
|
LISTE_PAD* pt_start_liste;
|
||||||
* pt_end_liste;
|
LISTE_PAD* pt_end_liste;
|
||||||
int ii, jj;
|
int ii, jj;
|
||||||
CHEVELU* local_chevelu;
|
CHEVELU* local_chevelu;
|
||||||
static CHEVELU* pt_fin_int_chevelu; // pointeur sur la fin de la liste
|
static CHEVELU* pt_fin_int_chevelu; // pointeur sur la fin de la liste
|
||||||
|
@ -955,12 +992,15 @@ char* WinEDA_BasePcbFrame::build_ratsnest_module( wxDC* DC, MODULE* Module )
|
||||||
goto calcul_chevelu_ext;
|
goto calcul_chevelu_ext;
|
||||||
|
|
||||||
/* calcul du chevelu "interne", c.a.d. liant les seuls pads du module */
|
/* calcul du chevelu "interne", c.a.d. liant les seuls pads du module */
|
||||||
pt_liste_pad = (LISTE_PAD*) adr_lowmem; nb_pads_ref = 0;
|
pt_liste_pad = (LISTE_PAD*) adr_lowmem;
|
||||||
|
nb_pads_ref = 0;
|
||||||
|
|
||||||
pad_ref = Module->m_Pads;
|
pad_ref = Module->m_Pads;
|
||||||
for( ; pad_ref != NULL; pad_ref = (D_PAD*) pad_ref->Pnext )
|
for( ; pad_ref != NULL; pad_ref = (D_PAD*) pad_ref->Pnext )
|
||||||
{
|
{
|
||||||
if( pad_ref->m_NetCode == 0 )
|
if( pad_ref->m_NetCode == 0 )
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
*pt_liste_pad = pad_ref;
|
*pt_liste_pad = pad_ref;
|
||||||
pad_ref->m_logical_connexion = 0;
|
pad_ref->m_logical_connexion = 0;
|
||||||
pad_ref->m_physical_connexion = 0;
|
pad_ref->m_physical_connexion = 0;
|
||||||
|
@ -970,13 +1010,14 @@ char* WinEDA_BasePcbFrame::build_ratsnest_module( wxDC* DC, MODULE* Module )
|
||||||
if( nb_pads_ref == 0 )
|
if( nb_pads_ref == 0 )
|
||||||
return (char*) pt_liste_pad; /* pas de connexions! */
|
return (char*) pt_liste_pad; /* pas de connexions! */
|
||||||
|
|
||||||
qsort( adr_lowmem, nb_pads_ref, sizeof(D_PAD *),
|
qsort( adr_lowmem, nb_pads_ref, sizeof(D_PAD *), tri_par_net );
|
||||||
( int( * ) ( const void*, const void* ) )tri_par_net );
|
|
||||||
|
|
||||||
/* construction de la liste des pads connectes aux pads de ce module */
|
/* construction de la liste des pads connectes aux pads de ce module */
|
||||||
DisplayRastnestInProgress = FALSE;
|
DisplayRastnestInProgress = FALSE;
|
||||||
pt_liste_ref = (LISTE_PAD*) adr_lowmem;
|
pt_liste_ref = (LISTE_PAD*) adr_lowmem;
|
||||||
nb_pads_externes = 0; current_net_code = 0;
|
|
||||||
|
nb_pads_externes = 0;
|
||||||
|
current_net_code = 0;
|
||||||
for( ii = 0; ii < nb_pads_ref; ii++ )
|
for( ii = 0; ii < nb_pads_ref; ii++ )
|
||||||
{
|
{
|
||||||
pad_ref = pt_liste_ref[ii];
|
pad_ref = pt_liste_ref[ii];
|
||||||
|
@ -990,8 +1031,10 @@ char* WinEDA_BasePcbFrame::build_ratsnest_module( wxDC* DC, MODULE* Module )
|
||||||
pad_externe = *pt_liste_generale; pt_liste_generale++;
|
pad_externe = *pt_liste_generale; pt_liste_generale++;
|
||||||
if( pad_externe->m_NetCode != current_net_code )
|
if( pad_externe->m_NetCode != current_net_code )
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
if( pad_externe->m_Parent == Module )
|
if( pad_externe->m_Parent == Module )
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
pad_externe->m_logical_connexion = 0;
|
pad_externe->m_logical_connexion = 0;
|
||||||
pad_externe->m_physical_connexion = 0;
|
pad_externe->m_physical_connexion = 0;
|
||||||
*pt_liste_pad = pad_externe; pt_liste_pad++;
|
*pt_liste_pad = pad_externe; pt_liste_pad++;
|
||||||
|
@ -1001,7 +1044,7 @@ char* WinEDA_BasePcbFrame::build_ratsnest_module( wxDC* DC, MODULE* Module )
|
||||||
|
|
||||||
/* tri par net_codes croissants de la liste des pads externes */
|
/* tri par net_codes croissants de la liste des pads externes */
|
||||||
qsort( pt_liste_ref + nb_pads_ref, nb_pads_externes, sizeof(D_PAD *),
|
qsort( pt_liste_ref + nb_pads_ref, nb_pads_externes, sizeof(D_PAD *),
|
||||||
( int( * ) ( const void*, const void* ) )tri_par_net );
|
tri_par_net );
|
||||||
|
|
||||||
/* calcul du chevelu interne au module:
|
/* calcul du chevelu interne au module:
|
||||||
* Ce calcul est identique au calcul du chevelu general, mais il est
|
* Ce calcul est identique au calcul du chevelu general, mais il est
|
||||||
|
@ -1023,6 +1066,7 @@ char* WinEDA_BasePcbFrame::build_ratsnest_module( wxDC* DC, MODULE* Module )
|
||||||
{
|
{
|
||||||
if( pt_end_liste >= pt_liste_pad_limite )
|
if( pt_end_liste >= pt_liste_pad_limite )
|
||||||
break;
|
break;
|
||||||
|
|
||||||
if( (*pt_end_liste)->m_NetCode != current_net_code )
|
if( (*pt_end_liste)->m_NetCode != current_net_code )
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -1070,6 +1114,7 @@ calcul_chevelu_ext:
|
||||||
nb_local_chevelu = nb_int_chevelu;
|
nb_local_chevelu = nb_int_chevelu;
|
||||||
pt_liste_ref = (LISTE_PAD*) adr_lowmem;
|
pt_liste_ref = (LISTE_PAD*) adr_lowmem;
|
||||||
pad_ref = *pt_liste_ref;
|
pad_ref = *pt_liste_ref;
|
||||||
|
|
||||||
current_net_code = pad_ref->m_NetCode;
|
current_net_code = pad_ref->m_NetCode;
|
||||||
local_chevelu->dist = 0x7FFFFFFF;
|
local_chevelu->dist = 0x7FFFFFFF;
|
||||||
local_chevelu->status = 0;
|
local_chevelu->status = 0;
|
||||||
|
@ -1078,8 +1123,9 @@ calcul_chevelu_ext:
|
||||||
{
|
{
|
||||||
pad_ref = *(pt_liste_ref + ii);
|
pad_ref = *(pt_liste_ref + ii);
|
||||||
if( pad_ref->m_NetCode != current_net_code )
|
if( pad_ref->m_NetCode != current_net_code )
|
||||||
{ /* un nouveau chevelu est cree (si necessaire) pour
|
{
|
||||||
* chaque nouveau net */
|
/* un nouveau chevelu est cree (si necessaire) pour
|
||||||
|
* chaque nouveau net */
|
||||||
if( increment )
|
if( increment )
|
||||||
{
|
{
|
||||||
nb_local_chevelu++; local_chevelu++;
|
nb_local_chevelu++; local_chevelu++;
|
||||||
|
@ -1096,13 +1142,17 @@ calcul_chevelu_ext:
|
||||||
for( jj = nb_pads_externes; jj > 0; jj-- )
|
for( jj = nb_pads_externes; jj > 0; jj-- )
|
||||||
{
|
{
|
||||||
pad_externe = *pt_liste_generale; pt_liste_generale++;
|
pad_externe = *pt_liste_generale; pt_liste_generale++;
|
||||||
|
|
||||||
/* les netcodes doivent etre identiques */
|
/* les netcodes doivent etre identiques */
|
||||||
if( pad_externe->m_NetCode < pad_ref->m_NetCode )
|
if( pad_externe->m_NetCode < pad_ref->m_NetCode )
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
if( pad_externe->m_NetCode > pad_ref->m_NetCode )
|
if( pad_externe->m_NetCode > pad_ref->m_NetCode )
|
||||||
break;
|
break;
|
||||||
|
|
||||||
distance = abs( pad_externe->m_Pos.x - pad_pos_X ) +
|
distance = abs( pad_externe->m_Pos.x - pad_pos_X ) +
|
||||||
abs( pad_externe->m_Pos.y - pad_pos_Y );
|
abs( pad_externe->m_Pos.y - pad_pos_Y );
|
||||||
|
|
||||||
if( distance < local_chevelu->dist )
|
if( distance < local_chevelu->dist )
|
||||||
{
|
{
|
||||||
local_chevelu->pad_start = pad_ref;
|
local_chevelu->pad_start = pad_ref;
|
||||||
|
@ -1117,7 +1167,8 @@ calcul_chevelu_ext:
|
||||||
|
|
||||||
if( increment ) // fin de balayage : le ratsnest courant doit etre memorise
|
if( increment ) // fin de balayage : le ratsnest courant doit etre memorise
|
||||||
{
|
{
|
||||||
nb_local_chevelu++; local_chevelu++;
|
nb_local_chevelu++;
|
||||||
|
local_chevelu++;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Retourne l'adr de la zone disponible */
|
/* Retourne l'adr de la zone disponible */
|
||||||
|
@ -1193,8 +1244,11 @@ void WinEDA_BasePcbFrame::trace_ratsnest_module( wxDC* DC )
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* routine locale de tri par longueur de links utilisee par la fonction QSORT */
|
/* routine locale de tri par longueur de links utilisee par la fonction QSORT */
|
||||||
static int sort_by_localnetlength( int* ref, int* compare )
|
static int sort_by_localnetlength( const void* o1, const void* o2 )
|
||||||
{
|
{
|
||||||
|
int* ref = (int*) o1;
|
||||||
|
int* compare = (int*) o2;
|
||||||
|
|
||||||
int* org = (int*) adr_lowmem;
|
int* org = (int*) adr_lowmem;
|
||||||
int ox = *org++;
|
int ox = *org++;
|
||||||
int oy = *org++;
|
int oy = *org++;
|
||||||
|
@ -1202,9 +1256,13 @@ static int sort_by_localnetlength( int* ref, int* compare )
|
||||||
|
|
||||||
lengthref = abs( *ref - ox );
|
lengthref = abs( *ref - ox );
|
||||||
ref++;
|
ref++;
|
||||||
|
|
||||||
lengthref += abs( *ref - oy ); // = longueur entre point origine et pad ref
|
lengthref += abs( *ref - oy ); // = longueur entre point origine et pad ref
|
||||||
|
|
||||||
lengthcmp = abs( *compare - ox );
|
lengthcmp = abs( *compare - ox );
|
||||||
|
|
||||||
compare++;
|
compare++;
|
||||||
|
|
||||||
lengthcmp += abs( *compare - oy ); // = longueur entre point origine et pad comparé
|
lengthcmp += abs( *compare - oy ); // = longueur entre point origine et pad comparé
|
||||||
|
|
||||||
return lengthref - lengthcmp;
|
return lengthref - lengthcmp;
|
||||||
|
@ -1223,7 +1281,7 @@ int* WinEDA_BasePcbFrame::build_ratsnest_pad( EDA_BaseStruct* ref,
|
||||||
D_PAD* pad_ref = NULL;
|
D_PAD* pad_ref = NULL;
|
||||||
|
|
||||||
if( ( (m_Pcb->m_Status_Pcb & LISTE_CHEVELU_OK) == 0 )
|
if( ( (m_Pcb->m_Status_Pcb & LISTE_CHEVELU_OK) == 0 )
|
||||||
|| ( (m_Pcb->m_Status_Pcb & LISTE_PAD_OK) == 0 ) )
|
|| ( (m_Pcb->m_Status_Pcb & LISTE_PAD_OK) == 0 ) )
|
||||||
{
|
{
|
||||||
nb_local_chevelu = 0;
|
nb_local_chevelu = 0;
|
||||||
return NULL;
|
return NULL;
|
||||||
|
@ -1274,8 +1332,10 @@ int* WinEDA_BasePcbFrame::build_ratsnest_pad( EDA_BaseStruct* ref,
|
||||||
D_PAD* pad = *padlist;
|
D_PAD* pad = *padlist;
|
||||||
if( pad->m_NetCode != current_net_code )
|
if( pad->m_NetCode != current_net_code )
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
if( pad == pad_ref )
|
if( pad == pad_ref )
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
if( !pad->m_physical_connexion || (pad->m_physical_connexion != conn_number) )
|
if( !pad->m_physical_connexion || (pad->m_physical_connexion != conn_number) )
|
||||||
{
|
{
|
||||||
*pt_coord = pad->m_Pos.x; pt_coord++;
|
*pt_coord = pad->m_Pos.x; pt_coord++;
|
||||||
|
@ -1290,7 +1350,7 @@ int* WinEDA_BasePcbFrame::build_ratsnest_pad( EDA_BaseStruct* ref,
|
||||||
}
|
}
|
||||||
|
|
||||||
qsort( base_data + 2, nb_local_chevelu, 2 * sizeof(int),
|
qsort( base_data + 2, nb_local_chevelu, 2 * sizeof(int),
|
||||||
( int( * ) ( const void*, const void* ) )sort_by_localnetlength );
|
sort_by_localnetlength );
|
||||||
return pt_coord;
|
return pt_coord;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1309,12 +1369,15 @@ void WinEDA_BasePcbFrame::trace_ratsnest_pad( wxDC* DC )
|
||||||
|
|
||||||
if( (m_Pcb->m_Status_Pcb & LISTE_CHEVELU_OK) == 0 )
|
if( (m_Pcb->m_Status_Pcb & LISTE_CHEVELU_OK) == 0 )
|
||||||
return;
|
return;
|
||||||
|
|
||||||
if( nb_local_chevelu == 0 )
|
if( nb_local_chevelu == 0 )
|
||||||
return;
|
return;
|
||||||
|
|
||||||
if( local_liste_chevelu == NULL )
|
if( local_liste_chevelu == NULL )
|
||||||
return;
|
return;
|
||||||
|
|
||||||
pt_coord = (int*) local_liste_chevelu;
|
pt_coord = (int*) local_liste_chevelu;
|
||||||
|
|
||||||
refX = *pt_coord; pt_coord++;
|
refX = *pt_coord; pt_coord++;
|
||||||
refY = *pt_coord; pt_coord++;
|
refY = *pt_coord; pt_coord++;
|
||||||
|
|
||||||
|
@ -1323,6 +1386,7 @@ void WinEDA_BasePcbFrame::trace_ratsnest_pad( wxDC* DC )
|
||||||
{
|
{
|
||||||
if( ii >= g_MaxLinksShowed )
|
if( ii >= g_MaxLinksShowed )
|
||||||
break;
|
break;
|
||||||
|
|
||||||
GRLine( &DrawPanel->m_ClipBox, DC, refX, refY, *pt_coord, *(pt_coord + 1),
|
GRLine( &DrawPanel->m_ClipBox, DC, refX, refY, *pt_coord, *(pt_coord + 1),
|
||||||
0, YELLOW );
|
0, YELLOW );
|
||||||
pt_coord += 2;
|
pt_coord += 2;
|
||||||
|
|
Loading…
Reference in New Issue