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CADSTAR PCB: Load all three net properties into a single Netclass 

The final netclass name will be a bit long but it will allow for custom
DRC rules to individually target each of the three properties available
in CADSTAR:
- Route Code (which specifies width of the track in min, max, opt)
- Net class (only used in signal integrity analysis)
- Spacing class (for specifying clearance requirements between classes)
This commit is contained in:
Roberto Fernandez Bautista 2021-10-10 20:05:27 +01:00
parent e9030283cc
commit 7a71ebf9ac
2 changed files with 28 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp
View File

@ -3850,18 +3850,39 @@ NETINFO_ITEM* CADSTAR_PCB_ARCHIVE_LOADER::getKiCadNet( const NET_ID& aCadstarNet
NETINFO_ITEM* netInfo = new NETINFO_ITEM( m_board, newName, ++m_numNets );
NETCLASSPTR netclass;
if( m_netClassMap.find( csNet.RouteCodeID ) != m_netClassMap.end() )
std::tuple<ROUTECODE_ID, NETCLASS_ID, SPACING_CLASS_ID> key = { csNet.RouteCodeID,
csNet.NetClassID,
csNet.SpacingClassID };
if( m_netClassMap.find( key ) != m_netClassMap.end() )
{
netclass = m_netClassMap.at( csNet.RouteCodeID );
netclass = m_netClassMap.at( key );
}
else
{
ROUTECODE rc = getRouteCode( csNet.RouteCodeID );
wxString netClassName;
ROUTECODE rc = getRouteCode( csNet.RouteCodeID );
netClassName += wxT( "Route code: " ) + rc.Name;
if( !csNet.NetClassID.IsEmpty() )
{
CADSTAR_NETCLASS nc = Assignments.Codedefs.NetClasses.at( csNet.NetClassID );
netClassName += wxT( " | Net class: " ) + nc.Name;
}
if( !csNet.SpacingClassID.IsEmpty() )
{
SPCCLASSNAME sp = Assignments.Codedefs.SpacingClassNames.at( csNet.SpacingClassID );
netClassName += wxT( " | Spacing class: " ) + sp.Name;
}
netclass.reset( new NETCLASS( *m_board->GetDesignSettings().GetDefault() ) );
netclass->SetName( rc.Name );
netclass->SetName( netClassName );
m_board->GetDesignSettings().GetNetClasses().Add( netclass );
netclass->SetTrackWidth( getKiCadLength( rc.OptimalWidth ) );
m_netClassMap.insert( { csNet.RouteCodeID, netclass } );
m_netClassMap.insert( { key, netclass } );
}
netclass->Add( newName );

3
pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.h
View File

@ -115,7 +115,8 @@ private:
std::map<SYMDEF_ID, ASSOCIATED_COPPER_PADS> m_librarycopperpads;
std::map<NET_ID, NETINFO_ITEM*> m_netMap; ///< Map between Cadstar and KiCad Nets
std::map<ROUTECODE_ID, NETCLASSPTR> m_netClassMap; ///< Map between Cadstar and KiCad classes
std::map<std::tuple<ROUTECODE_ID, NETCLASS_ID, SPACING_CLASS_ID>, NETCLASSPTR>
m_netClassMap; ///< Map between Cadstar and KiCad classes
std::map<TEMPLATE_ID, ZONE*> m_zonesMap; ///< Map between Cadstar and KiCad zones
std::vector<LAYER_ID> m_powerPlaneLayers; ///< List of layers that are marked as
///< power plane in CADSTAR. This is used