Add basic netlist QA test
This commit is contained in:
Jon Evans
parent
b802a3e776
commit
7df3df3381
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@ -129,6 +129,10 @@ option( KICAD_USE_VALGRIND
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"Build KiCad with valgrind stack tracking enabled."
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OFF )
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option( KICAD_NETLIST_QA
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"Run eeschema netlist QA tests (requires Python 3)"
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OFF )
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# when option KICAD_SCRIPTING OR KICAD_SCRIPTING_MODULES is enabled:
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# PYTHON_EXECUTABLE can be defined when invoking cmake
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# ( use -DPYTHON_EXECUTABLE=<python path>/python.exe or python2 )
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@ -100,3 +100,14 @@ set_source_files_properties( eeschema_test_utils.cpp PROPERTIES
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)
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kicad_add_boost_test( qa_eeschema eeschema )
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# eeschema netlist tests
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# technically this doesn't depend on KICAD_SCRIPTING but if we have that, we know we have Python.
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if( KICAD_SCRIPTING_MODULES AND KICAD_NETLIST_QA )
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add_test( NAME qa_netlist
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COMMAND ${PYTHON_EXECUTABLE} test_netlists.py ${CMAKE_BINARY_DIR}
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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endif()
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@ -0,0 +1,804 @@
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EESchema Schematic File Version 5
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EELAYER 30 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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Sheet 2 3
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Title "Complex hierarchy: demo"
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Date "2017-01-15"
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Rev "1"
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Comp ""
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Comment1 ""
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Comment9 ""
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$EndDescr
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F 2 "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal" V 7200 3600 10 0000 C CNN
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||||
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||||
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||||
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||||
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||||
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|
||||
L complex_hierarchy_schlib:GND #PWR025
|
||||
U 1 1 4B3A1373
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||||
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||||
AR Path="/4B3A13A4/4B3A1373" Ref="#PWR025" Part="1"
|
||||
AR Path="/4B3A1333/4B3A1373" Ref="#PWR041" Part="1"
|
||||
F 0 "#PWR025" H 7300 3850 30 0001 C CNN
|
||||
F 1 "GND" H 7300 3780 30 0001 C CNN
|
||||
F 2 "" H 7300 3850 10 0001 C CNN
|
||||
F 3 "" H 7300 3850 60 0001 C CNN
|
||||
1 7300 3850
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||||
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||||
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|
||||
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|
||||
L complex_hierarchy_schlib:R R18
|
||||
U 1 1 4B3A1371
|
||||
P 7250 5100
|
||||
AR Path="/4B3A13A4/4B3A1371" Ref="R18" Part="1"
|
||||
AR Path="/4B3A1333/4B3A1371" Ref="R8" Part="1"
|
||||
F 0 "R18" V 7150 5100 50 0000 C CNN
|
||||
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|
||||
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|
||||
F 3 "" H 7250 5100 60 0001 C CNN
|
||||
1 7250 5100
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||||
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||||
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||||
$Comp
|
||||
L complex_hierarchy_schlib:R R22
|
||||
U 1 1 4B3A1370
|
||||
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|
||||
AR Path="/4B3A13A4/4B3A1370" Ref="R22" Part="1"
|
||||
AR Path="/4B3A1333/4B3A1370" Ref="R12" Part="1"
|
||||
F 0 "R22" V 9000 5100 50 0000 C CNN
|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
L complex_hierarchy_schlib:+12V #U026
|
||||
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||||
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||||
AR Path="/4B3A13A4/4B3A136F" Ref="#U026" Part="1"
|
||||
AR Path="/4B3A1333/4B3A136F" Ref="#U042" Part="1"
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
L complex_hierarchy_schlib:R R19
|
||||
U 1 1 4B3A136D
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||||
P 7400 5400
|
||||
AR Path="/4B3A13A4/4B3A136D" Ref="R19" Part="1"
|
||||
AR Path="/4B3A1333/4B3A136D" Ref="R9" Part="1"
|
||||
F 0 "R19" V 7300 5400 50 0000 C CNN
|
||||
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||||
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||||
F 3 "" H 7400 5400 60 0001 C CNN
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||||
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||||
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||||
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||||
$Comp
|
||||
L complex_hierarchy_schlib:CONN_2 P5
|
||||
U 1 1 4B3A136C
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||||
P 10750 4400
|
||||
AR Path="/4B3A13A4/4B3A136C" Ref="P5" Part="1"
|
||||
AR Path="/4B3A1333/4B3A136C" Ref="P3" Part="1"
|
||||
F 0 "P5" V 10700 4400 40 0000 C CNN
|
||||
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|
||||
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|
||||
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||||
1 10750 4400
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||||
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||||
Text Label 7100 6400 0 60 ~ 0
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S_OUT+
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||||
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|
||||
L complex_hierarchy_schlib:R R16
|
||||
U 1 1 4B3A136B
|
||||
P 3250 2000
|
||||
AR Path="/4B3A13A4/4B3A136B" Ref="R16" Part="1"
|
||||
AR Path="/4B3A1333/4B3A136B" Ref="R6" Part="1"
|
||||
F 0 "R16" V 3150 2000 50 0000 C CNN
|
||||
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|
||||
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|
||||
F 3 "" H 3250 2000 60 0001 C CNN
|
||||
1 3250 2000
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:GND #PWR027
|
||||
U 1 1 4B3A136A
|
||||
P 1800 2250
|
||||
AR Path="/4B3A13A4/4B3A136A" Ref="#PWR027" Part="1"
|
||||
AR Path="/4B3A1333/4B3A136A" Ref="#PWR043" Part="1"
|
||||
F 0 "#PWR027" H 1800 2250 30 0001 C CNN
|
||||
F 1 "GND" H 1800 2180 30 0001 C CNN
|
||||
F 2 "" H 1800 2250 10 0001 C CNN
|
||||
F 3 "" H 1800 2250 60 0001 C CNN
|
||||
1 1800 2250
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||||
1 0 0 -1
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||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:GND #PWR028
|
||||
U 1 1 4B3A1369
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||||
P 4000 2750
|
||||
AR Path="/4B3A13A4/4B3A1369" Ref="#PWR028" Part="1"
|
||||
AR Path="/4B3A1333/4B3A1369" Ref="#PWR044" Part="1"
|
||||
F 0 "#PWR028" H 4000 2750 30 0001 C CNN
|
||||
F 1 "GND" H 4000 2680 30 0001 C CNN
|
||||
F 2 "" H 4000 2750 10 0001 C CNN
|
||||
F 3 "" H 4000 2750 60 0001 C CNN
|
||||
1 4000 2750
|
||||
1 0 0 -1
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||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:LM358N U4
|
||||
U 1 1 4B3A1368
|
||||
P 6400 5400
|
||||
AR Path="/4B3A13A4/4B3A1368" Ref="U4" Part="1"
|
||||
AR Path="/4B3A1333/4B3A1368" Ref="U3" Part="1"
|
||||
F 0 "U4" H 6450 5600 60 0000 C CNN
|
||||
F 1 "LM358N" H 6550 5200 50 0000 C CNN
|
||||
F 2 "Package_DIP:DIP-8_W7.62mm_LongPads" H 6650 5150 10 0000 C CNN
|
||||
F 3 "" H 6400 5400 60 0001 C CNN
|
||||
1 6400 5400
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||||
1 0 0 -1
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||||
$EndComp
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||||
$Comp
|
||||
L complex_hierarchy_schlib:CONN_2 P6
|
||||
U 1 1 4B3A1367
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||||
P 1350 2100
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||||
AR Path="/4B3A13A4/4B3A1367" Ref="P6" Part="1"
|
||||
AR Path="/4B3A1333/4B3A1367" Ref="P4" Part="1"
|
||||
F 0 "P6" V 1300 2100 40 0000 C CNN
|
||||
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|
||||
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|
||||
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|
||||
1 1350 2100
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||||
-1 0 0 -1
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||||
$EndComp
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||||
$Comp
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||||
L complex_hierarchy_schlib:C C7
|
||||
U 1 1 4B3A1366
|
||||
P 4000 2550
|
||||
AR Path="/4B3A13A4/4B3A1366" Ref="C7" Part="1"
|
||||
AR Path="/4B3A1333/4B3A1366" Ref="C4" Part="1"
|
||||
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|
||||
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|
||||
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|
||||
F 3 "" H 4000 2550 60 0001 C CNN
|
||||
1 4000 2550
|
||||
1 0 0 -1
|
||||
$EndComp
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||||
$Comp
|
||||
L complex_hierarchy_schlib:C C8
|
||||
U 1 1 4B3A1365
|
||||
P 8100 5750
|
||||
AR Path="/4B3A13A4/4B3A1365" Ref="C8" Part="1"
|
||||
AR Path="/4B3A1333/4B3A1365" Ref="C5" Part="1"
|
||||
F 0 "C8" H 8150 5850 50 0000 L CNN
|
||||
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|
||||
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|
||||
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|
||||
1 8100 5750
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||||
1 0 0 -1
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||||
$EndComp
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||||
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||||
L complex_hierarchy_schlib:R R15
|
||||
U 1 1 4B3A1364
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||||
P 9450 4150
|
||||
AR Path="/4B3A13A4/4B3A1364" Ref="R15" Part="1"
|
||||
AR Path="/4B3A1333/4B3A1364" Ref="R5" Part="1"
|
||||
F 0 "R15" V 9530 4150 50 0000 C CNN
|
||||
F 1 "47" V 9450 4150 50 0000 C CNN
|
||||
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|
||||
F 3 "" H 9450 4150 60 0001 C CNN
|
||||
1 9450 4150
|
||||
0 1 1 0
|
||||
$EndComp
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||||
$Comp
|
||||
L complex_hierarchy_schlib:GND #PWR029
|
||||
U 1 1 4B3A1363
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||||
P 10250 4550
|
||||
AR Path="/4B3A13A4/4B3A1363" Ref="#PWR029" Part="1"
|
||||
AR Path="/4B3A1333/4B3A1363" Ref="#PWR045" Part="1"
|
||||
F 0 "#PWR029" H 10250 4550 30 0001 C CNN
|
||||
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|
||||
F 2 "" H 10250 4550 10 0001 C CNN
|
||||
F 3 "" H 10250 4550 60 0001 C CNN
|
||||
1 10250 4550
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||||
1 0 0 -1
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||||
$EndComp
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||||
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||||
L complex_hierarchy_schlib:R R21
|
||||
U 1 1 4B3A1362
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||||
P 5250 6400
|
||||
AR Path="/4B3A13A4/4B3A1362" Ref="R21" Part="1"
|
||||
AR Path="/4B3A1333/4B3A1362" Ref="R11" Part="1"
|
||||
F 0 "R21" V 5150 6400 50 0000 C CNN
|
||||
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|
||||
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|
||||
F 3 "" H 5250 6400 60 0001 C CNN
|
||||
1 5250 6400
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||||
0 1 1 0
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||||
$EndComp
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||||
$Comp
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||||
L complex_hierarchy_schlib:GND #PWR030
|
||||
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P 5050 6400
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||||
AR Path="/4B3A13A4/4B3A1361" Ref="#PWR030" Part="1"
|
||||
AR Path="/4B3A1333/4B3A1361" Ref="#PWR046" Part="1"
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||||
F 0 "#PWR030" H 5050 6400 30 0001 C CNN
|
||||
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|
||||
F 2 "" H 5050 6400 10 0001 C CNN
|
||||
F 3 "" H 5050 6400 60 0001 C CNN
|
||||
1 5050 6400
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||||
0 1 1 0
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||||
$EndComp
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||||
$Comp
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||||
L complex_hierarchy_schlib:MPSA92 Q5
|
||||
U 1 1 4B3A1360
|
||||
P 7800 3300
|
||||
AR Path="/4B3A13A4/4B3A1360" Ref="Q5" Part="1"
|
||||
AR Path="/4B3A1333/4B3A1360" Ref="Q1" Part="1"
|
||||
F 0 "Q5" H 7800 3150 60 0000 R CNN
|
||||
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|
||||
F 2 "Package_TO_SOT_THT:TO-92_HandSolder" H 7750 3100 10 0000 C CNN
|
||||
F 3 "" H 7800 3300 60 0001 C CNN
|
||||
1 7800 3300
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||||
1 0 0 1
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||||
$EndComp
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||||
$Comp
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||||
L complex_hierarchy_schlib:HT #PWR031
|
||||
U 1 1 4B3A135F
|
||||
P 7300 2650
|
||||
AR Path="/4B3A13A4/4B3A135F" Ref="#PWR031" Part="1"
|
||||
AR Path="/4B3A1333/4B3A135F" Ref="#PWR047" Part="1"
|
||||
F 0 "#PWR031" H 7300 2770 20 0001 C CNN
|
||||
F 1 "HT" H 7300 2740 40 0000 C CNN
|
||||
F 2 "" H 7300 2650 10 0001 C CNN
|
||||
F 3 "" H 7300 2650 60 0001 C CNN
|
||||
1 7300 2650
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||||
1 0 0 -1
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||||
$EndComp
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||||
$Comp
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||||
L complex_hierarchy_schlib:HT #PWR032
|
||||
U 1 1 4B3A135E
|
||||
P 7900 2550
|
||||
AR Path="/4B3A13A4/4B3A135E" Ref="#PWR032" Part="1"
|
||||
AR Path="/4B3A1333/4B3A135E" Ref="#PWR048" Part="1"
|
||||
F 0 "#PWR032" H 7900 2670 20 0001 C CNN
|
||||
F 1 "HT" H 7900 2640 40 0000 C CNN
|
||||
F 2 "" H 7900 2550 10 0001 C CNN
|
||||
F 3 "" H 7900 2550 60 0001 C CNN
|
||||
1 7900 2550
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||||
1 0 0 -1
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||||
$EndComp
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||||
$Comp
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||||
L complex_hierarchy_schlib:HT #PWR033
|
||||
U 1 1 4B3A135D
|
||||
P 8600 3300
|
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AR Path="/4B3A13A4/4B3A135D" Ref="#PWR033" Part="1"
|
||||
AR Path="/4B3A1333/4B3A135D" Ref="#PWR049" Part="1"
|
||||
F 0 "#PWR033" H 8600 3420 20 0001 C CNN
|
||||
F 1 "HT" H 8600 3390 40 0000 C CNN
|
||||
F 2 "" H 8600 3300 10 0001 C CNN
|
||||
F 3 "" H 8600 3300 60 0001 C CNN
|
||||
1 8600 3300
|
||||
1 0 0 -1
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||||
$EndComp
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||||
$Comp
|
||||
L complex_hierarchy_schlib:LM358N U4
|
||||
U 2 1 4B3A135C
|
||||
P 4850 2400
|
||||
AR Path="/4B3A13A4/4B3A135C" Ref="U4" Part="2"
|
||||
AR Path="/4B3A1333/4B3A135C" Ref="U3" Part="2"
|
||||
F 0 "U4" H 4900 2600 60 0000 C CNN
|
||||
F 1 "LM358N" H 5000 2200 50 0000 C CNN
|
||||
F 2 "Package_DIP:DIP-8_W7.62mm_LongPads" H 5100 2150 10 0000 C CNN
|
||||
F 3 "" H 4850 2400 60 0001 C CNN
|
||||
2 4850 2400
|
||||
1 0 0 -1
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||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:+12V #U034
|
||||
U 1 1 4B3A135B
|
||||
P 4750 1950
|
||||
AR Path="/4B3A13A4/4B3A135B" Ref="#U034" Part="1"
|
||||
AR Path="/4B3A1333/4B3A135B" Ref="#U050" Part="1"
|
||||
F 0 "#U034" H 4750 1900 20 0001 C CNN
|
||||
F 1 "+12V" H 4750 2050 40 0000 C CNN
|
||||
F 2 "" H 4750 1950 10 0001 C CNN
|
||||
F 3 "" H 4750 1950 60 0001 C CNN
|
||||
1 4750 1950
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:R R17
|
||||
U 1 1 4B3A1359
|
||||
P 3950 2000
|
||||
AR Path="/4B3A13A4/4B3A1359" Ref="R17" Part="1"
|
||||
AR Path="/4B3A1333/4B3A1359" Ref="R7" Part="1"
|
||||
F 0 "R17" V 3850 2000 50 0000 C CNN
|
||||
F 1 "22K" V 3950 2000 50 0000 C CNN
|
||||
F 2 "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal" V 3800 2000 10 0000 C CNN
|
||||
F 3 "" H 3950 2000 60 0001 C CNN
|
||||
1 3950 2000
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:C C6
|
||||
U 1 1 4B3A1358
|
||||
P 4350 1600
|
||||
AR Path="/4B3A13A4/4B3A1358" Ref="C6" Part="1"
|
||||
AR Path="/4B3A1333/4B3A1358" Ref="C3" Part="1"
|
||||
F 0 "C6" V 4200 1600 50 0000 C CNN
|
||||
F 1 "15nF" V 4500 1600 50 0000 C CNN
|
||||
F 2 "Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm" V 4150 1600 10 0000 C CNN
|
||||
F 3 "" H 4350 1600 60 0001 C CNN
|
||||
1 4350 1600
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||||
0 1 1 0
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$EndComp
|
||||
Text Notes 2600 2950 0 80 Italic 16
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Filter:\nFc =1000Hz
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:POT RV2
|
||||
U 1 1 4B3A1357
|
||||
P 5850 6400
|
||||
AR Path="/4B3A13A4/4B3A1357" Ref="RV2" Part="1"
|
||||
AR Path="/4B3A1333/4B3A1357" Ref="RV1" Part="1"
|
||||
F 0 "RV2" H 5850 6300 50 0000 C CNN
|
||||
F 1 "4,7K" H 5850 6400 50 0000 C CNN
|
||||
F 2 "Potentiometer_THT:Potentiometer_Bourns_3266W_Vertical" H 5850 6250 10 0000 C CNN
|
||||
F 3 "" H 5850 6400 60 0001 C CNN
|
||||
1 5850 6400
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||||
1 0 0 -1
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$EndComp
|
||||
Wire Wire Line
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7900 4100 7900 4400
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Wire Wire Line
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8600 4450 8900 4450
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Wire Wire Line
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8600 4450 8600 4600
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Wire Wire Line
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8600 4150 9100 4150
|
||||
Wire Wire Line
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8600 4150 8600 3900
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||||
Wire Wire Line
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2850 2450 2850 2400
|
||||
Wire Wire Line
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4350 2000 4350 2200
|
||||
Wire Wire Line
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4350 2200 4000 2200
|
||||
Wire Wire Line
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4000 2200 4000 2400
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Connection ~ 4350 2200
|
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Wire Wire Line
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4000 2750 4000 2700
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Wire Wire Line
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4750 2850 4750 2800
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Wire Wire Line
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4750 1950 4750 2000
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Wire Wire Line
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7300 2700 7300 2650
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Wire Wire Line
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7900 2550 7900 2600
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Wire Wire Line
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7900 4800 8100 4800
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Connection ~ 7900 4800
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Wire Wire Line
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8100 5900 8100 5950
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Wire Wire Line
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6300 4950 6300 5000
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Wire Wire Line
|
||||
6300 5850 6300 5800
|
||||
Wire Wire Line
|
||||
5050 6400 5100 6400
|
||||
Wire Wire Line
|
||||
7100 5100 7000 5100
|
||||
Wire Wire Line
|
||||
7300 3000 7300 2900
|
||||
Wire Wire Line
|
||||
9100 4150 9300 4150
|
||||
Wire Wire Line
|
||||
7300 3300 7300 3450
|
||||
Wire Wire Line
|
||||
5450 2400 5450 1600
|
||||
Wire Wire Line
|
||||
7900 3700 7900 3900
|
||||
Wire Wire Line
|
||||
3600 2000 3800 2000
|
||||
Wire Wire Line
|
||||
2850 2000 3100 2000
|
||||
Wire Wire Line
|
||||
5150 3000 5450 3000
|
||||
Wire Wire Line
|
||||
8100 4800 8300 4800
|
||||
Wire Wire Line
|
||||
9800 4300 9800 4450
|
||||
Wire Wire Line
|
||||
8900 4450 9300 4450
|
||||
Wire Wire Line
|
||||
8900 5400 8900 6400
|
||||
Wire Wire Line
|
||||
4350 2200 4350 2300
|
||||
Wire Wire Line
|
||||
7900 4800 7900 4900
|
||||
$EndSCHEMATC
|
||||
|
|
@ -0,0 +1,302 @@
|
|||
EESchema-LIBRARY Version 2.4
|
||||
#encoding utf-8
|
||||
#
|
||||
# complex_hierarchy_schlib_+12C
|
||||
#
|
||||
DEF complex_hierarchy_schlib_+12C #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "complex_hierarchy_schlib_+12C" 0 150 50 H V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
P 2 0 1 0 -30 50 0 100 N
|
||||
P 2 0 1 0 0 0 0 100 N
|
||||
P 2 0 1 0 0 100 30 50 N
|
||||
X +12C 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# complex_hierarchy_schlib_+12V
|
||||
#
|
||||
DEF complex_hierarchy_schlib_+12V #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "complex_hierarchy_schlib_+12V" 0 140 50 H V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
P 2 0 1 0 -30 50 0 100 N
|
||||
P 2 0 1 0 0 0 0 100 N
|
||||
P 2 0 1 0 0 100 30 50 N
|
||||
X +12V 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# complex_hierarchy_schlib_-VAA
|
||||
#
|
||||
DEF complex_hierarchy_schlib_-VAA #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 100 20 H I C CNN
|
||||
F1 "complex_hierarchy_schlib_-VAA" 0 100 30 H V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
P 3 0 1 0 0 0 0 50 0 50 N
|
||||
P 7 0 1 0 0 80 30 50 -20 50 -30 50 0 80 0 80 0 80 F
|
||||
X -VAA 1 0 0 0 U 20 20 0 0 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# complex_hierarchy_schlib_7805
|
||||
#
|
||||
DEF complex_hierarchy_schlib_7805 U 0 20 Y Y 1 F N
|
||||
F0 "U" 150 -196 60 H V C CNN
|
||||
F1 "complex_hierarchy_schlib_7805" 0 200 60 H V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
S -200 -150 200 150 0 1 0 N
|
||||
X VO 1 400 50 200 L 30 40 1 1 w
|
||||
X GND 2 0 -250 100 U 30 40 1 1 I
|
||||
X VI 3 -400 50 200 R 30 40 1 1 I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# complex_hierarchy_schlib_C
|
||||
#
|
||||
DEF complex_hierarchy_schlib_C C 0 10 N Y 1 F N
|
||||
F0 "C" 25 100 50 H V L CNN
|
||||
F1 "complex_hierarchy_schlib_C" 25 -100 50 H V L CNN
|
||||
F2 "" 38 -150 30 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
$FPLIST
|
||||
C?
|
||||
C_????_*
|
||||
C_????
|
||||
SMD*_c
|
||||
Capacitor*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
P 2 0 1 20 -80 -30 80 -30 N
|
||||
P 2 0 1 20 -80 30 80 30 N
|
||||
X ~ 1 0 150 110 D 40 40 1 1 P
|
||||
X ~ 2 0 -150 110 U 40 40 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# complex_hierarchy_schlib_CONN_2
|
||||
#
|
||||
DEF complex_hierarchy_schlib_CONN_2 P 0 40 Y N 1 F N
|
||||
F0 "P" -50 0 40 V V C CNN
|
||||
F1 "complex_hierarchy_schlib_CONN_2" 50 0 40 V V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
S -100 150 100 -150 0 1 0 N
|
||||
X P1 1 -350 100 250 R 60 60 1 1 P I
|
||||
X PM 2 -350 -100 250 R 60 60 1 1 P I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# complex_hierarchy_schlib_CP
|
||||
#
|
||||
DEF complex_hierarchy_schlib_CP C 0 10 N Y 1 F N
|
||||
F0 "C" 25 100 50 H V L CNN
|
||||
F1 "complex_hierarchy_schlib_CP" 25 -100 50 H V L CNN
|
||||
F2 "" 38 -150 30 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
$FPLIST
|
||||
CP*
|
||||
Elko*
|
||||
TantalC*
|
||||
C*elec
|
||||
c_elec*
|
||||
SMD*_Pol
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -90 20 -90 40 0 1 0 N
|
||||
S -90 20 90 20 0 1 0 N
|
||||
S -70 90 -30 90 0 1 0 N
|
||||
S -50 70 -50 110 0 1 0 N
|
||||
S 90 -20 -90 -40 0 1 0 F
|
||||
S 90 40 -90 40 0 1 0 N
|
||||
S 90 40 90 20 0 1 0 N
|
||||
X ~ 1 0 150 110 D 40 40 1 1 P
|
||||
X ~ 2 0 -150 110 U 40 40 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# complex_hierarchy_schlib_D_Small
|
||||
#
|
||||
DEF complex_hierarchy_schlib_D_Small D 0 10 N N 1 F N
|
||||
F0 "D" -50 80 50 H V L CNN
|
||||
F1 "complex_hierarchy_schlib_D_Small" -150 -80 50 H V L CNN
|
||||
F2 "" 0 0 60 V V C CNN
|
||||
F3 "" 0 0 60 V V C CNN
|
||||
$FPLIST
|
||||
Diode_*
|
||||
D-Pak_TO252AA
|
||||
*SingleDiode
|
||||
*SingleDiode*
|
||||
*_Diode_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
P 2 0 1 0 -30 -40 -30 40 N
|
||||
P 4 0 1 0 30 -40 -30 0 30 40 30 -40 F
|
||||
X K 1 -100 0 70 R 50 50 1 1 P
|
||||
X A 2 100 0 70 L 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# complex_hierarchy_schlib_GND
|
||||
#
|
||||
DEF complex_hierarchy_schlib_GND #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "complex_hierarchy_schlib_GND" 0 -123 30 H V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
|
||||
X GND 1 0 0 0 D 20 30 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# complex_hierarchy_schlib_HT
|
||||
#
|
||||
DEF complex_hierarchy_schlib_HT #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 120 50 H I C CNN
|
||||
F1 "complex_hierarchy_schlib_HT" 0 90 50 H V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
P 3 0 1 0 0 0 0 40 0 40 N
|
||||
P 6 0 1 0 0 40 20 20 0 70 -20 20 0 40 0 40 N
|
||||
X HT 1 0 0 0 U 20 20 0 0 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# complex_hierarchy_schlib_ICL7660
|
||||
#
|
||||
DEF complex_hierarchy_schlib_ICL7660 U 0 40 Y Y 1 F N
|
||||
F0 "U" 200 400 70 H V L CNN
|
||||
F1 "complex_hierarchy_schlib_ICL7660" 50 -450 70 H V L CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
S -550 -350 550 350 0 1 0 N
|
||||
X CAP+ 2 -850 250 300 R 60 60 1 1 I
|
||||
X GND 3 -50 -650 300 U 60 60 1 1 W
|
||||
X CAP- 4 -850 50 300 R 60 60 1 1 I
|
||||
X VOUT 5 850 150 300 L 60 60 1 1 w
|
||||
X LV 6 850 -150 300 L 60 60 1 1 I
|
||||
X OSC 7 -850 -150 300 R 60 60 1 1 I
|
||||
X V+ 8 -50 650 300 D 60 60 1 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# complex_hierarchy_schlib_MPSA42
|
||||
#
|
||||
DEF complex_hierarchy_schlib_MPSA42 Q 0 0 Y Y 1 F N
|
||||
F0 "Q" 150 -150 60 H V L CNN
|
||||
F1 "complex_hierarchy_schlib_MPSA42" 150 150 60 H V L CNN
|
||||
F2 "TO92-CBE" 150 0 30 H I C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
$FPLIST
|
||||
TO92-CBE
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C 50 0 111 0 1 10 N
|
||||
P 2 0 1 0 0 0 100 100 N
|
||||
P 3 0 1 10 0 75 0 -75 0 -75 N
|
||||
P 3 0 1 0 50 -50 0 0 0 0 N
|
||||
P 3 0 1 0 90 -90 100 -100 100 -100 N
|
||||
P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F
|
||||
X E 1 100 -200 100 U 20 20 1 1 P
|
||||
X B 2 -200 0 200 R 20 20 1 1 I
|
||||
X C 3 100 200 100 D 20 20 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# complex_hierarchy_schlib_MPSA92
|
||||
#
|
||||
DEF complex_hierarchy_schlib_MPSA92 Q 0 0 Y Y 1 F N
|
||||
F0 "Q" 150 -150 60 H V L CNN
|
||||
F1 "complex_hierarchy_schlib_MPSA92" 150 150 60 H V L CNN
|
||||
F2 "TO92-CBE" 150 0 30 H I C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
$FPLIST
|
||||
TO92-CBE
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C 50 0 111 0 1 10 N
|
||||
P 2 0 1 0 0 0 100 100 N
|
||||
P 3 0 1 10 0 75 0 -75 0 -75 F
|
||||
P 3 0 1 0 25 -25 0 0 0 0 N
|
||||
P 3 0 1 0 100 -100 65 -65 65 -65 N
|
||||
P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F
|
||||
X E 1 100 -200 100 U 20 20 1 1 P
|
||||
X B 2 -200 0 200 R 20 20 1 1 I
|
||||
X C 3 100 200 100 D 20 20 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# complex_hierarchy_schlib_POT
|
||||
#
|
||||
DEF complex_hierarchy_schlib_POT RV 0 40 Y N 1 F N
|
||||
F0 "RV" 0 -100 50 H V C CNN
|
||||
F1 "complex_hierarchy_schlib_POT" 0 0 50 H V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
S -150 50 150 -50 0 1 0 N
|
||||
P 3 0 1 0 0 50 -20 70 20 70 F
|
||||
X 1 1 -250 0 100 R 40 40 1 1 P
|
||||
X 2 2 0 150 80 D 40 40 1 1 P
|
||||
X 3 3 250 0 100 L 40 40 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# complex_hierarchy_schlib_PWR_FLAG
|
||||
#
|
||||
DEF complex_hierarchy_schlib_PWR_FLAG #FLG 0 0 N N 1 F P
|
||||
F0 "#FLG" 0 95 50 H I C CNN
|
||||
F1 "complex_hierarchy_schlib_PWR_FLAG" 0 180 50 H V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
|
||||
X pwr 1 0 0 0 U 20 20 0 0 w
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# complex_hierarchy_schlib_R
|
||||
#
|
||||
DEF complex_hierarchy_schlib_R R 0 0 N Y 1 F N
|
||||
F0 "R" 80 0 50 V V C CNN
|
||||
F1 "complex_hierarchy_schlib_R" 0 0 50 V V C CNN
|
||||
F2 "" -70 0 30 V V C CNN
|
||||
F3 "" 0 0 30 H V C CNN
|
||||
$FPLIST
|
||||
R_*
|
||||
Resistor_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -40 -100 40 100 0 1 10 N
|
||||
X ~ 1 0 150 50 D 60 60 1 1 P
|
||||
X ~ 2 0 -150 50 U 60 60 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# complex_hierarchy_schlib_VCC
|
||||
#
|
||||
DEF complex_hierarchy_schlib_VCC #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "complex_hierarchy_schlib_VCC" 0 150 50 H V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
C 0 75 25 0 1 0 N
|
||||
P 2 0 1 0 0 0 0 50 N
|
||||
X VCC 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
||||
|
|
@ -0,0 +1,803 @@
|
|||
(export (version "D")
|
||||
(design
|
||||
(source "/home/jon/work/kicad-master/qa/eeschema/data/netlists/complex_hierarchy/complex_hierarchy.sch")
|
||||
(date "Sun 19 Apr 2020 16:13:41 EDT")
|
||||
(tool "Eeschema (5.99.0-1347-g0d2b30b74-dirty)")
|
||||
(sheet (number "1") (name "/") (tstamps "/")
|
||||
(title_block
|
||||
(title "Complex hierarchy: demo")
|
||||
(company)
|
||||
(rev)
|
||||
(date "2017-01-15")
|
||||
(source "complex_hierarchy.sch")
|
||||
(comment (number "1") (value ""))
|
||||
(comment (number "2") (value ""))
|
||||
(comment (number "3") (value ""))
|
||||
(comment (number "4") (value ""))
|
||||
(comment (number "5") (value ""))
|
||||
(comment (number "6") (value ""))
|
||||
(comment (number "7") (value ""))
|
||||
(comment (number "8") (value ""))
|
||||
(comment (number "9") (value ""))))
|
||||
(sheet (number "2") (name "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/")
|
||||
(title_block
|
||||
(title "Complex hierarchy: demo")
|
||||
(company)
|
||||
(rev "1")
|
||||
(date "2017-01-15")
|
||||
(source "ampli_ht.sch")
|
||||
(comment (number "1") (value ""))
|
||||
(comment (number "2") (value ""))
|
||||
(comment (number "3") (value ""))
|
||||
(comment (number "4") (value ""))
|
||||
(comment (number "5") (value ""))
|
||||
(comment (number "6") (value ""))
|
||||
(comment (number "7") (value ""))
|
||||
(comment (number "8") (value ""))
|
||||
(comment (number "9") (value ""))))
|
||||
(sheet (number "3") (name "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/")
|
||||
(title_block
|
||||
(title "Complex hierarchy: demo")
|
||||
(company)
|
||||
(rev "1")
|
||||
(date "2017-01-15")
|
||||
(source "ampli_ht.sch")
|
||||
(comment (number "1") (value ""))
|
||||
(comment (number "2") (value ""))
|
||||
(comment (number "3") (value ""))
|
||||
(comment (number "4") (value ""))
|
||||
(comment (number "5") (value ""))
|
||||
(comment (number "6") (value ""))
|
||||
(comment (number "7") (value ""))
|
||||
(comment (number "8") (value ""))
|
||||
(comment (number "9") (value "")))))
|
||||
(components
|
||||
(comp (ref "C1")
|
||||
(value "47uF")
|
||||
(footprint "Capacitor_THT:CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "CP") (description ""))
|
||||
(sheetpath (names "/") (tstamps "/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b03cec2"))
|
||||
(comp (ref "C10")
|
||||
(value "10uF")
|
||||
(footprint "Capacitor_THT:CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "CP") (description ""))
|
||||
(sheetpath (names "/") (tstamps "/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b4b15e7"))
|
||||
(comp (ref "C11")
|
||||
(value "10uF")
|
||||
(footprint "Capacitor_THT:CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "CP") (description ""))
|
||||
(sheetpath (names "/") (tstamps "/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b4b15d9"))
|
||||
(comp (ref "C2")
|
||||
(value "47uF/20V")
|
||||
(footprint "Capacitor_THT:CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "CP") (description ""))
|
||||
(sheetpath (names "/") (tstamps "/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004ae173cf"))
|
||||
(comp (ref "C9")
|
||||
(value "47uF/63V")
|
||||
(footprint "Capacitor_THT:CP_Axial_L11.0mm_D6.0mm_P18.00mm_Horizontal")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "CP") (description ""))
|
||||
(sheetpath (names "/") (tstamps "/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b3a1558"))
|
||||
(comp (ref "D1")
|
||||
(value "1N4007")
|
||||
(footprint "Diode_THT:D_DO-41_SOD81_P12.70mm_Horizontal")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "D_Small") (description ""))
|
||||
(sheetpath (names "/") (tstamps "/"))
|
||||
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|
||||
(comp (ref "Q7")
|
||||
(value "MPSA92")
|
||||
(footprint "Package_TO_SOT_THT:TO-92_HandSolder")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "MPSA92") (description ""))
|
||||
(sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b3a137c"))
|
||||
(comp (ref "Q8")
|
||||
(value "MPSA42")
|
||||
(footprint "Package_TO_SOT_THT:TO-92_HandSolder")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "MPSA42") (description ""))
|
||||
(sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b3a1379"))
|
||||
(comp (ref "R13")
|
||||
(value "470")
|
||||
(footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
|
||||
(sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b3a1376"))
|
||||
(comp (ref "R14")
|
||||
(value "220K")
|
||||
(footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
|
||||
(sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b3a1374"))
|
||||
(comp (ref "R15")
|
||||
(value "47")
|
||||
(footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
|
||||
(sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b3a1364"))
|
||||
(comp (ref "R16")
|
||||
(value "22K")
|
||||
(footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
|
||||
(sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b3a136b"))
|
||||
(comp (ref "R17")
|
||||
(value "22K")
|
||||
(footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
|
||||
(sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b3a1359"))
|
||||
(comp (ref "R18")
|
||||
(value "1K")
|
||||
(footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
|
||||
(sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b3a1371"))
|
||||
(comp (ref "R19")
|
||||
(value "1K")
|
||||
(footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
|
||||
(sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b3a136d"))
|
||||
(comp (ref "R20")
|
||||
(value "5,6K")
|
||||
(footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
|
||||
(sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b61688c"))
|
||||
(comp (ref "R21")
|
||||
(value "4,7K")
|
||||
(footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
|
||||
(sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b3a1362"))
|
||||
(comp (ref "R22")
|
||||
(value "220K")
|
||||
(footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
|
||||
(sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b3a1370"))
|
||||
(comp (ref "R24")
|
||||
(value "1K")
|
||||
(footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
|
||||
(sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b4f363e"))
|
||||
(comp (ref "R27")
|
||||
(value "47")
|
||||
(footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
|
||||
(sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b616b96"))
|
||||
(comp (ref "R28")
|
||||
(value "220K")
|
||||
(footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
|
||||
(sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b617b88"))
|
||||
(comp (ref "RV2")
|
||||
(value "4,7K")
|
||||
(footprint "Potentiometer_THT:Potentiometer_Bourns_3266W_Vertical")
|
||||
(libsource (lib "complex_hierarchy_schlib") (part "POT") (description ""))
|
||||
(sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b3a1357"))
|
||||
(comp (ref "U4")
|
||||
(value "LM358N")
|
||||
(footprint "Package_DIP:DIP-8_W7.62mm_LongPads")
|
||||
(libsource (lib "") (part "LM358N") (description ""))
|
||||
(sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
|
||||
(tstamp "00000000-0000-0000-0000-00004b3a1368")))
|
||||
(libparts
|
||||
(libpart (lib "") (part "LM358N")
|
||||
(fields
|
||||
(field (name "Reference") "U")
|
||||
(field (name "Value") "LM358N"))
|
||||
(pins
|
||||
(pin (num "1") (name "~") (type "output"))
|
||||
(pin (num "2") (name "-") (type "input"))
|
||||
(pin (num "3") (name "+") (type "input"))
|
||||
(pin (num "4") (name "V-") (type "power_in"))
|
||||
(pin (num "5") (name "+") (type "input"))
|
||||
(pin (num "6") (name "-") (type "input"))
|
||||
(pin (num "7") (name "~") (type "output"))
|
||||
(pin (num "8") (name "V+") (type "power_in"))))
|
||||
(libpart (lib "complex_hierarchy_schlib") (part "7805")
|
||||
(fields
|
||||
(field (name "Reference") "U")
|
||||
(field (name "Value") "7805"))
|
||||
(pins
|
||||
(pin (num "1") (name "VO") (type "power_out"))
|
||||
(pin (num "2") (name "GND") (type "input"))
|
||||
(pin (num "3") (name "VI") (type "input"))))
|
||||
(libpart (lib "complex_hierarchy_schlib") (part "C")
|
||||
(footprints
|
||||
(fp "C?")
|
||||
(fp "C_????_*")
|
||||
(fp "C_????")
|
||||
(fp "SMD*_c")
|
||||
(fp "Capacitor*"))
|
||||
(fields
|
||||
(field (name "Reference") "C")
|
||||
(field (name "Value") "C"))
|
||||
(pins
|
||||
(pin (num "1") (name "~") (type "passive"))
|
||||
(pin (num "2") (name "~") (type "passive"))))
|
||||
(libpart (lib "complex_hierarchy_schlib") (part "CONN_2")
|
||||
(fields
|
||||
(field (name "Reference") "P")
|
||||
(field (name "Value") "CONN_2"))
|
||||
(pins
|
||||
(pin (num "1") (name "P1") (type "passive"))
|
||||
(pin (num "2") (name "PM") (type "passive"))))
|
||||
(libpart (lib "complex_hierarchy_schlib") (part "CP")
|
||||
(footprints
|
||||
(fp "CP*")
|
||||
(fp "Elko*")
|
||||
(fp "TantalC*")
|
||||
(fp "C*elec")
|
||||
(fp "c_elec*")
|
||||
(fp "SMD*_Pol"))
|
||||
(fields
|
||||
(field (name "Reference") "C")
|
||||
(field (name "Value") "CP"))
|
||||
(pins
|
||||
(pin (num "1") (name "~") (type "passive"))
|
||||
(pin (num "2") (name "~") (type "passive"))))
|
||||
(libpart (lib "complex_hierarchy_schlib") (part "D_Small")
|
||||
(footprints
|
||||
(fp "Diode_*")
|
||||
(fp "D-Pak_TO252AA")
|
||||
(fp "*SingleDiode")
|
||||
(fp "*SingleDiode*")
|
||||
(fp "*_Diode_*"))
|
||||
(fields
|
||||
(field (name "Reference") "D")
|
||||
(field (name "Value") "D_Small"))
|
||||
(pins
|
||||
(pin (num "1") (name "K") (type "passive"))
|
||||
(pin (num "2") (name "A") (type "passive"))))
|
||||
(libpart (lib "complex_hierarchy_schlib") (part "ICL7660")
|
||||
(fields
|
||||
(field (name "Reference") "U")
|
||||
(field (name "Value") "ICL7660"))
|
||||
(pins
|
||||
(pin (num "2") (name "CAP+") (type "input"))
|
||||
(pin (num "3") (name "GND") (type "power_in"))
|
||||
(pin (num "4") (name "CAP-") (type "input"))
|
||||
(pin (num "5") (name "VOUT") (type "power_out"))
|
||||
(pin (num "6") (name "LV") (type "input"))
|
||||
(pin (num "7") (name "OSC") (type "input"))
|
||||
(pin (num "8") (name "V+") (type "power_in"))))
|
||||
(libpart (lib "complex_hierarchy_schlib") (part "MPSA42")
|
||||
(footprints
|
||||
(fp "TO92-CBE"))
|
||||
(fields
|
||||
(field (name "Reference") "Q")
|
||||
(field (name "Value") "MPSA42")
|
||||
(field (name "Footprint") "TO92-CBE"))
|
||||
(pins
|
||||
(pin (num "1") (name "E") (type "passive"))
|
||||
(pin (num "2") (name "B") (type "input"))
|
||||
(pin (num "3") (name "C") (type "passive"))))
|
||||
(libpart (lib "complex_hierarchy_schlib") (part "MPSA92")
|
||||
(footprints
|
||||
(fp "TO92-CBE"))
|
||||
(fields
|
||||
(field (name "Reference") "Q")
|
||||
(field (name "Value") "MPSA92")
|
||||
(field (name "Footprint") "TO92-CBE"))
|
||||
(pins
|
||||
(pin (num "1") (name "E") (type "passive"))
|
||||
(pin (num "2") (name "B") (type "input"))
|
||||
(pin (num "3") (name "C") (type "passive"))))
|
||||
(libpart (lib "complex_hierarchy_schlib") (part "POT")
|
||||
(fields
|
||||
(field (name "Reference") "RV")
|
||||
(field (name "Value") "POT"))
|
||||
(pins
|
||||
(pin (num "1") (name "1") (type "passive"))
|
||||
(pin (num "2") (name "2") (type "passive"))
|
||||
(pin (num "3") (name "3") (type "passive"))))
|
||||
(libpart (lib "complex_hierarchy_schlib") (part "R")
|
||||
(footprints
|
||||
(fp "R_*")
|
||||
(fp "Resistor_*"))
|
||||
(fields
|
||||
(field (name "Reference") "R")
|
||||
(field (name "Value") "R"))
|
||||
(pins
|
||||
(pin (num "1") (name "~") (type "passive"))
|
||||
(pin (num "2") (name "~") (type "passive")))))
|
||||
(libraries
|
||||
(library (logical "complex_hierarchy_schlib")
|
||||
(uri "/home/jon/work/kicad-master/qa/eeschema/data/netlists/complex_hierarchy/complex_hierarchy_schlib.lib")))
|
||||
(nets
|
||||
(net (code "1") (name "+12C")
|
||||
(node (ref "C2") (pin "1"))
|
||||
(node (ref "D1") (pin "1") (pinfunction "K"))
|
||||
(node (ref "U2") (pin "3") (pinfunction "VI"))
|
||||
(node (ref "U3") (pin "8") (pinfunction "V+"))
|
||||
(node (ref "U4") (pin "8") (pinfunction "V+")))
|
||||
(net (code "2") (name "-VAA")
|
||||
(node (ref "C11") (pin "2"))
|
||||
(node (ref "U1") (pin "5") (pinfunction "VOUT"))
|
||||
(node (ref "U3") (pin "4") (pinfunction "V-"))
|
||||
(node (ref "U4") (pin "4") (pinfunction "V-")))
|
||||
(net (code "3") (name "/12Vext")
|
||||
(node (ref "D1") (pin "2") (pinfunction "A"))
|
||||
(node (ref "P2") (pin "1") (pinfunction "P1")))
|
||||
(net (code "4") (name "/ampli_ht_horizontal/PIEZO_IN")
|
||||
(node (ref "P6") (pin "1") (pinfunction "P1"))
|
||||
(node (ref "R24") (pin "2")))
|
||||
(net (code "5") (name "/ampli_ht_horizontal/PIEZO_OUT")
|
||||
(node (ref "P5") (pin "1") (pinfunction "P1"))
|
||||
(node (ref "R15") (pin "1"))
|
||||
(node (ref "R27") (pin "1")))
|
||||
(net (code "6") (name "/ampli_ht_horizontal/S_OUT+")
|
||||
(node (ref "R22") (pin "1"))
|
||||
(node (ref "R28") (pin "1"))
|
||||
(node (ref "RV2") (pin "3") (pinfunction "3")))
|
||||
(net (code "7") (name "/ampli_ht_horizontal/Vpil_0_3,3V")
|
||||
(node (ref "C6") (pin "1"))
|
||||
(node (ref "U4") (pin "3") (pinfunction "+"))
|
||||
(node (ref "U4") (pin "6") (pinfunction "-"))
|
||||
(node (ref "U4") (pin "7")))
|
||||
(net (code "8") (name "/ampli_ht_vertical/PIEZO_IN")
|
||||
(node (ref "P4") (pin "1") (pinfunction "P1"))
|
||||
(node (ref "R23") (pin "2")))
|
||||
(net (code "9") (name "/ampli_ht_vertical/PIEZO_OUT")
|
||||
(node (ref "P3") (pin "1") (pinfunction "P1"))
|
||||
(node (ref "R25") (pin "1"))
|
||||
(node (ref "R5") (pin "1")))
|
||||
(net (code "10") (name "/ampli_ht_vertical/S_OUT+")
|
||||
(node (ref "R12") (pin "1"))
|
||||
(node (ref "R26") (pin "1"))
|
||||
(node (ref "RV1") (pin "3") (pinfunction "3")))
|
||||
(net (code "11") (name "/ampli_ht_vertical/Vpil_0_3,3V")
|
||||
(node (ref "C3") (pin "1"))
|
||||
(node (ref "U3") (pin "3") (pinfunction "+"))
|
||||
(node (ref "U3") (pin "6") (pinfunction "-"))
|
||||
(node (ref "U3") (pin "7")))
|
||||
(net (code "12") (name "GND")
|
||||
(node (ref "C1") (pin "2"))
|
||||
(node (ref "C11") (pin "1"))
|
||||
(node (ref "C12") (pin "2"))
|
||||
(node (ref "C14") (pin "2"))
|
||||
(node (ref "C2") (pin "2"))
|
||||
(node (ref "C4") (pin "2"))
|
||||
(node (ref "C5") (pin "2"))
|
||||
(node (ref "C7") (pin "2"))
|
||||
(node (ref "C8") (pin "2"))
|
||||
(node (ref "C9") (pin "2"))
|
||||
(node (ref "P1") (pin "2") (pinfunction "PM"))
|
||||
(node (ref "P2") (pin "2") (pinfunction "PM"))
|
||||
(node (ref "P3") (pin "2") (pinfunction "PM"))
|
||||
(node (ref "P4") (pin "2") (pinfunction "PM"))
|
||||
(node (ref "P5") (pin "2") (pinfunction "PM"))
|
||||
(node (ref "P6") (pin "2") (pinfunction "PM"))
|
||||
(node (ref "Q3") (pin "3") (pinfunction "C"))
|
||||
(node (ref "Q7") (pin "3") (pinfunction "C"))
|
||||
(node (ref "R11") (pin "2"))
|
||||
(node (ref "R14") (pin "2"))
|
||||
(node (ref "R18") (pin "2"))
|
||||
(node (ref "R21") (pin "2"))
|
||||
(node (ref "R4") (pin "2"))
|
||||
(node (ref "R8") (pin "2"))
|
||||
(node (ref "U1") (pin "3") (pinfunction "GND"))
|
||||
(node (ref "U2") (pin "2") (pinfunction "GND")))
|
||||
(net (code "13") (name "HT")
|
||||
(node (ref "C9") (pin "1"))
|
||||
(node (ref "D2") (pin "2") (pinfunction "A"))
|
||||
(node (ref "D5") (pin "2") (pinfunction "A"))
|
||||
(node (ref "P1") (pin "1") (pinfunction "P1"))
|
||||
(node (ref "Q2") (pin "3") (pinfunction "C"))
|
||||
(node (ref "Q6") (pin "3") (pinfunction "C"))
|
||||
(node (ref "R13") (pin "1"))
|
||||
(node (ref "R3") (pin "1")))
|
||||
(net (code "14") (name "Net-(C10-Pad1)")
|
||||
(node (ref "C10") (pin "1"))
|
||||
(node (ref "U1") (pin "2") (pinfunction "CAP+")))
|
||||
(net (code "15") (name "Net-(C10-Pad2)")
|
||||
(node (ref "C10") (pin "2"))
|
||||
(node (ref "U1") (pin "4") (pinfunction "CAP-")))
|
||||
(net (code "16") (name "Net-(C12-Pad1)")
|
||||
(node (ref "C12") (pin "1"))
|
||||
(node (ref "R23") (pin "1"))
|
||||
(node (ref "R6") (pin "2")))
|
||||
(net (code "17") (name "Net-(C14-Pad1)")
|
||||
(node (ref "C14") (pin "1"))
|
||||
(node (ref "R16") (pin "2"))
|
||||
(node (ref "R24") (pin "1")))
|
||||
(net (code "18") (name "Net-(C3-Pad2)")
|
||||
(node (ref "C3") (pin "2"))
|
||||
(node (ref "R6") (pin "1"))
|
||||
(node (ref "R7") (pin "2")))
|
||||
(net (code "19") (name "Net-(C4-Pad1)")
|
||||
(node (ref "C4") (pin "1"))
|
||||
(node (ref "R7") (pin "1"))
|
||||
(node (ref "U3") (pin "5") (pinfunction "+")))
|
||||
(net (code "20") (name "Net-(C5-Pad1)")
|
||||
(node (ref "C5") (pin "1"))
|
||||
(node (ref "R10") (pin "2")))
|
||||
(net (code "21") (name "Net-(C6-Pad2)")
|
||||
(node (ref "C6") (pin "2"))
|
||||
(node (ref "R16") (pin "1"))
|
||||
(node (ref "R17") (pin "2")))
|
||||
(net (code "22") (name "Net-(C7-Pad1)")
|
||||
(node (ref "C7") (pin "1"))
|
||||
(node (ref "R17") (pin "1"))
|
||||
(node (ref "U4") (pin "5") (pinfunction "+")))
|
||||
(net (code "23") (name "Net-(C8-Pad1)")
|
||||
(node (ref "C8") (pin "1"))
|
||||
(node (ref "R20") (pin "2")))
|
||||
(net (code "24") (name "Net-(D2-Pad1)")
|
||||
(node (ref "D2") (pin "1") (pinfunction "K"))
|
||||
(node (ref "D3") (pin "2") (pinfunction "A")))
|
||||
(net (code "25") (name "Net-(D3-Pad1)")
|
||||
(node (ref "D3") (pin "1") (pinfunction "K"))
|
||||
(node (ref "Q1") (pin "2") (pinfunction "B"))
|
||||
(node (ref "R4") (pin "1")))
|
||||
(net (code "26") (name "Net-(D4-Pad1)")
|
||||
(node (ref "D4") (pin "1") (pinfunction "K"))
|
||||
(node (ref "Q3") (pin "2") (pinfunction "B"))
|
||||
(node (ref "Q4") (pin "3") (pinfunction "C"))
|
||||
(node (ref "R10") (pin "1")))
|
||||
(net (code "27") (name "Net-(D4-Pad2)")
|
||||
(node (ref "D4") (pin "2") (pinfunction "A"))
|
||||
(node (ref "D8") (pin "1") (pinfunction "K")))
|
||||
(net (code "28") (name "Net-(D5-Pad1)")
|
||||
(node (ref "D5") (pin "1") (pinfunction "K"))
|
||||
(node (ref "D6") (pin "2") (pinfunction "A")))
|
||||
(net (code "29") (name "Net-(D6-Pad1)")
|
||||
(node (ref "D6") (pin "1") (pinfunction "K"))
|
||||
(node (ref "Q5") (pin "2") (pinfunction "B"))
|
||||
(node (ref "R14") (pin "1")))
|
||||
(net (code "30") (name "Net-(D7-Pad1)")
|
||||
(node (ref "D7") (pin "1") (pinfunction "K"))
|
||||
(node (ref "Q7") (pin "2") (pinfunction "B"))
|
||||
(node (ref "Q8") (pin "3") (pinfunction "C"))
|
||||
(node (ref "R20") (pin "1")))
|
||||
(net (code "31") (name "Net-(D7-Pad2)")
|
||||
(node (ref "D7") (pin "2") (pinfunction "A"))
|
||||
(node (ref "D9") (pin "1") (pinfunction "K")))
|
||||
(net (code "32") (name "Net-(D8-Pad2)")
|
||||
(node (ref "D8") (pin "2") (pinfunction "A"))
|
||||
(node (ref "Q1") (pin "3") (pinfunction "C"))
|
||||
(node (ref "Q2") (pin "2") (pinfunction "B")))
|
||||
(net (code "33") (name "Net-(D9-Pad2)")
|
||||
(node (ref "D9") (pin "2") (pinfunction "A"))
|
||||
(node (ref "Q5") (pin "3") (pinfunction "C"))
|
||||
(node (ref "Q6") (pin "2") (pinfunction "B")))
|
||||
(net (code "34") (name "Net-(Q1-Pad1)")
|
||||
(node (ref "Q1") (pin "1") (pinfunction "E"))
|
||||
(node (ref "R3") (pin "2")))
|
||||
(net (code "35") (name "Net-(Q2-Pad1)")
|
||||
(node (ref "Q2") (pin "1") (pinfunction "E"))
|
||||
(node (ref "R26") (pin "2"))
|
||||
(node (ref "R5") (pin "2")))
|
||||
(net (code "36") (name "Net-(Q3-Pad1)")
|
||||
(node (ref "Q3") (pin "1") (pinfunction "E"))
|
||||
(node (ref "R12") (pin "2"))
|
||||
(node (ref "R25") (pin "2")))
|
||||
(net (code "37") (name "Net-(Q4-Pad1)")
|
||||
(node (ref "Q4") (pin "1") (pinfunction "E"))
|
||||
(node (ref "R9") (pin "1")))
|
||||
(net (code "38") (name "Net-(Q4-Pad2)")
|
||||
(node (ref "Q4") (pin "2") (pinfunction "B"))
|
||||
(node (ref "R8") (pin "1")))
|
||||
(net (code "39") (name "Net-(Q5-Pad1)")
|
||||
(node (ref "Q5") (pin "1") (pinfunction "E"))
|
||||
(node (ref "R13") (pin "2")))
|
||||
(net (code "40") (name "Net-(Q6-Pad1)")
|
||||
(node (ref "Q6") (pin "1") (pinfunction "E"))
|
||||
(node (ref "R15") (pin "2"))
|
||||
(node (ref "R28") (pin "2")))
|
||||
(net (code "41") (name "Net-(Q7-Pad1)")
|
||||
(node (ref "Q7") (pin "1") (pinfunction "E"))
|
||||
(node (ref "R22") (pin "2"))
|
||||
(node (ref "R27") (pin "2")))
|
||||
(net (code "42") (name "Net-(Q8-Pad1)")
|
||||
(node (ref "Q8") (pin "1") (pinfunction "E"))
|
||||
(node (ref "R19") (pin "1")))
|
||||
(net (code "43") (name "Net-(Q8-Pad2)")
|
||||
(node (ref "Q8") (pin "2") (pinfunction "B"))
|
||||
(node (ref "R18") (pin "1")))
|
||||
(net (code "44") (name "Net-(R11-Pad1)")
|
||||
(node (ref "R11") (pin "1"))
|
||||
(node (ref "RV1") (pin "1") (pinfunction "1")))
|
||||
(net (code "45") (name "Net-(R19-Pad2)")
|
||||
(node (ref "R19") (pin "2"))
|
||||
(node (ref "U4") (pin "1")))
|
||||
(net (code "46") (name "Net-(R21-Pad1)")
|
||||
(node (ref "R21") (pin "1"))
|
||||
(node (ref "RV2") (pin "1") (pinfunction "1")))
|
||||
(net (code "47") (name "Net-(R9-Pad2)")
|
||||
(node (ref "R9") (pin "2"))
|
||||
(node (ref "U3") (pin "1")))
|
||||
(net (code "48") (name "Net-(RV1-Pad2)")
|
||||
(node (ref "RV1") (pin "2") (pinfunction "2"))
|
||||
(node (ref "U3") (pin "2") (pinfunction "-")))
|
||||
(net (code "49") (name "Net-(RV2-Pad2)")
|
||||
(node (ref "RV2") (pin "2") (pinfunction "2"))
|
||||
(node (ref "U4") (pin "2") (pinfunction "-")))
|
||||
(net (code "50") (name "Net-(U1-Pad6)")
|
||||
(node (ref "U1") (pin "6") (pinfunction "LV")))
|
||||
(net (code "51") (name "Net-(U1-Pad7)")
|
||||
(node (ref "U1") (pin "7") (pinfunction "OSC")))
|
||||
(net (code "52") (name "VCC")
|
||||
(node (ref "C1") (pin "1"))
|
||||
(node (ref "U1") (pin "8") (pinfunction "V+"))
|
||||
(node (ref "U2") (pin "1") (pinfunction "VO")))))
|
||||
|
|
@ -0,0 +1,272 @@
|
|||
update=Tue 21 Jan 2020 12:19:00 PM EST
|
||||
version=1
|
||||
last_client=kicad
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[cvpcb/libraries]
|
||||
EquName1=devcms
|
||||
[general]
|
||||
version=1
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=
|
||||
LastSTEPExportPath=
|
||||
LastIDFExportPath=
|
||||
LastVRMLExportPath=
|
||||
LastSpecctraDSNExportPath=
|
||||
LastGenCADExportPath=
|
||||
CopperLayerCount=2
|
||||
BoardThickness=1.6002
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.2032
|
||||
MinViaDiameter=0.889
|
||||
MinViaDrill=0.508
|
||||
MinMicroViaDiameter=0.508
|
||||
MinMicroViaDrill=0.2032
|
||||
MinHoleToHole=0.25
|
||||
CopperEdgeClearance=0.01
|
||||
TrackWidth1=0.4
|
||||
ViaDiameter1=1.651
|
||||
ViaDrill1=0.6
|
||||
dPairWidth1=0.4
|
||||
dPairGap1=0.35
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.2
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.2
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=0
|
||||
CopperLineWidth=0.3
|
||||
CopperTextSizeV=2
|
||||
CopperTextSizeH=2
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=0
|
||||
EdgeCutLineWidth=0.09999999999999999
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.09999999999999999
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=0
|
||||
DimensionUnits=0
|
||||
DimensionPrecision=1
|
||||
SolderMaskClearance=0.254
|
||||
SolderMaskMinWidth=0
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=top_copper
|
||||
Type=1
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=bottom_copper
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.3
|
||||
TrackWidth=0.4
|
||||
ViaDiameter=1.651
|
||||
ViaDrill=0.6
|
||||
uViaDiameter=0.508
|
||||
uViaDrill=0.2032
|
||||
dPairWidth=0.4
|
||||
dPairGap=0.35
|
||||
dPairViaGap=0.25
|
||||
[pcbnew/Netclasses/1]
|
||||
Name=power
|
||||
Clearance=0.3
|
||||
TrackWidth=0.6
|
||||
ViaDiameter=1.651
|
||||
ViaDrill=0.6
|
||||
uViaDiameter=0.508
|
||||
uViaDrill=0.2032
|
||||
dPairWidth=0.4
|
||||
dPairGap=0.35
|
||||
dPairViaGap=0.25
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_WriteFile=0
|
||||
ERC_TestSimilarLabels=1
|
||||
ERC_CheckUniqueGlobalLabels=1
|
||||
ERC_CheckBusDriverConflicts=1
|
||||
ERC_CheckBusEntryConflicts=1
|
||||
ERC_CheckBusToBusConflicts=1
|
||||
ERC_CheckBusToNetConflicts=1
|
||||
|
|
@ -0,0 +1,445 @@
|
|||
EESchema Schematic File Version 5
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 1 3
|
||||
Title "Complex hierarchy: demo"
|
||||
Date "2017-01-15"
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
Comment5 ""
|
||||
Comment6 ""
|
||||
Comment7 ""
|
||||
Comment8 ""
|
||||
Comment9 ""
|
||||
$EndDescr
|
||||
NoConn ~ 8800 3050
|
||||
Connection ~ 9200 2750
|
||||
Wire Wire Line
|
||||
9200 2650 9200 2750
|
||||
Wire Wire Line
|
||||
6650 2900 6650 3000
|
||||
Wire Wire Line
|
||||
6650 3000 7050 3000
|
||||
Wire Wire Line
|
||||
7050 3000 7050 2850
|
||||
Wire Wire Line
|
||||
7050 2850 7100 2850
|
||||
Wire Wire Line
|
||||
9200 2350 9200 2250
|
||||
Connection ~ 2500 1300
|
||||
Wire Wire Line
|
||||
8300 1300 9200 1300
|
||||
Wire Wire Line
|
||||
2800 2500 3000 2500
|
||||
Wire Wire Line
|
||||
2500 1250 2500 1300
|
||||
Wire Wire Line
|
||||
3800 2500 3800 2450
|
||||
Wire Wire Line
|
||||
2100 2800 2100 2700
|
||||
Wire Wire Line
|
||||
2100 2700 2000 2700
|
||||
Wire Wire Line
|
||||
2000 2500 2600 2500
|
||||
Wire Wire Line
|
||||
3200 2900 3200 3000
|
||||
Wire Wire Line
|
||||
3200 2500 3200 2600
|
||||
Connection ~ 3200 2500
|
||||
Wire Wire Line
|
||||
3550 2450 3550 2500
|
||||
Connection ~ 3550 2500
|
||||
Wire Wire Line
|
||||
3000 2500 3000 2450
|
||||
Connection ~ 3000 2500
|
||||
Wire Wire Line
|
||||
7400 1250 7400 1300
|
||||
Wire Wire Line
|
||||
7400 1300 7500 1300
|
||||
Wire Wire Line
|
||||
9200 1750 9200 1800
|
||||
Wire Wire Line
|
||||
9200 1250 9200 1300
|
||||
Connection ~ 9200 1300
|
||||
Wire Wire Line
|
||||
2200 1650 2200 1700
|
||||
Wire Wire Line
|
||||
2500 1650 2500 1700
|
||||
Wire Wire Line
|
||||
6650 2600 6650 2500
|
||||
Wire Wire Line
|
||||
6650 2500 7050 2500
|
||||
Wire Wire Line
|
||||
7050 2500 7050 2650
|
||||
Wire Wire Line
|
||||
7050 2650 7100 2650
|
||||
Wire Wire Line
|
||||
8800 2750 9200 2750
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:CP C10
|
||||
U 1 1 4B4B15E7
|
||||
P 6650 2750
|
||||
F 0 "C10" H 6800 2800 50 0000 L CNN
|
||||
F 1 "10uF" H 6800 2750 50 0000 L TNN
|
||||
F 2 "Capacitor_THT:CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal" H 6800 2650 10 0000 C CNN
|
||||
F 3 "" H 6650 2750 60 0001 C CNN
|
||||
1 6650 2750
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:GND #PWR01
|
||||
U 1 1 4B4B15DA
|
||||
P 9050 2300
|
||||
F 0 "#PWR01" H 9050 2300 30 0001 C CNN
|
||||
F 1 "GND" H 9050 2230 30 0001 C CNN
|
||||
F 2 "" H 9050 2300 10 0001 C CNN
|
||||
F 3 "" H 9050 2300 60 0001 C CNN
|
||||
1 9050 2300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:CP C11
|
||||
U 1 1 4B4B15D9
|
||||
P 9200 2500
|
||||
F 0 "C11" H 9350 2550 50 0000 L CNN
|
||||
F 1 "10uF" H 9350 2500 50 0000 L TNN
|
||||
F 2 "Capacitor_THT:CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal" H 9550 2400 10 0000 C CNN
|
||||
F 3 "" H 9200 2500 60 0001 C CNN
|
||||
1 9200 2500
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
NoConn ~ 7100 3050
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:-VAA #PWR02
|
||||
U 1 1 4B4B1578
|
||||
P 9350 2750
|
||||
F 0 "#PWR02" H 9350 2850 20 0001 C CNN
|
||||
F 1 "-VAA" V 9350 2950 40 0000 C CNN
|
||||
F 2 "" H 9350 2750 10 0001 C CNN
|
||||
F 3 "" H 9350 2750 60 0001 C CNN
|
||||
1 9350 2750
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:7805 U2
|
||||
U 1 1 4B4B1532
|
||||
P 7900 1350
|
||||
F 0 "U2" H 7900 1650 60 0000 C CNN
|
||||
F 1 "78L05" H 7900 1550 60 0000 C CNN
|
||||
F 2 "Package_TO_SOT_THT:TO-92_HandSolder" H 8150 1150 10 0000 C CNN
|
||||
F 3 "" H 7900 1350 60 0001 C CNN
|
||||
1 7900 1350
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:VCC #PWR03
|
||||
U 1 1 4B4B1253
|
||||
P 7900 2200
|
||||
F 0 "#PWR03" H 7900 2300 30 0001 C CNN
|
||||
F 1 "VCC" H 7900 2300 40 0000 C CNN
|
||||
F 2 "" H 7900 2200 10 0001 C CNN
|
||||
F 3 "" H 7900 2200 60 0001 C CNN
|
||||
1 7900 2200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:VCC #PWR04
|
||||
U 1 1 4B4B124E
|
||||
P 9200 1250
|
||||
F 0 "#PWR04" H 9200 1350 30 0001 C CNN
|
||||
F 1 "VCC" H 9200 1350 40 0000 C CNN
|
||||
F 2 "" H 9200 1250 10 0001 C CNN
|
||||
F 3 "" H 9200 1250 60 0001 C CNN
|
||||
1 9200 1250
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:GND #PWR05
|
||||
U 1 1 4B4B1237
|
||||
P 7900 3600
|
||||
F 0 "#PWR05" H 7900 3600 30 0001 C CNN
|
||||
F 1 "GND" H 7900 3530 30 0001 C CNN
|
||||
F 2 "" H 7900 3600 10 0001 C CNN
|
||||
F 3 "" H 7900 3600 60 0001 C CNN
|
||||
1 7900 3600
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:ICL7660 U1
|
||||
U 1 1 4B4B1230
|
||||
P 7950 2900
|
||||
F 0 "U1" H 7400 3300 70 0000 L CNN
|
||||
F 1 "ICL7660" H 8500 2450 70 0000 R CNN
|
||||
F 2 "Package_DIP:DIP-8_W7.62mm_LongPads" H 8250 2350 10 0000 C CNN
|
||||
F 3 "" H 7950 2900 60 0001 C CNN
|
||||
1 7950 2900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 2150 2500 0 60 ~ 0
|
||||
12Vext
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:CP C9
|
||||
U 1 1 4B3A1558
|
||||
P 2500 1500
|
||||
F 0 "C9" H 2650 1550 50 0000 L CNN
|
||||
F 1 "47uF/63V" H 2650 1500 50 0000 L TNN
|
||||
F 2 "Capacitor_THT:CP_Axial_L11.0mm_D6.0mm_P18.00mm_Horizontal" H 2800 1400 10 0000 C CNN
|
||||
F 3 "" H 2500 1500 60 0001 C CNN
|
||||
1 2500 1500
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:GND #PWR06
|
||||
U 1 1 4B3A1557
|
||||
P 2500 1700
|
||||
F 0 "#PWR06" H 2500 1700 30 0001 C CNN
|
||||
F 1 "GND" H 2500 1630 30 0001 C CNN
|
||||
F 2 "" H 2500 1700 10 0001 C CNN
|
||||
F 3 "" H 2500 1700 60 0001 C CNN
|
||||
1 2500 1700
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Sheet
|
||||
S 6100 4400 2000 1450
|
||||
U 4B3A13A4
|
||||
F0 "ampli_ht_horizontal" 60
|
||||
F1 "ampli_ht.sch" 60
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 2800 4400 2000 1450
|
||||
U 4B3A1333
|
||||
F0 "ampli_ht_vertical" 60
|
||||
F1 "ampli_ht.sch" 60
|
||||
$EndSheet
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:GND #PWR07
|
||||
U 1 1 4B3A1302
|
||||
P 2200 1750
|
||||
F 0 "#PWR07" H 2200 1750 30 0001 C CNN
|
||||
F 1 "GND" H 2200 1680 30 0001 C CNN
|
||||
F 2 "" H 2200 1750 10 0001 C CNN
|
||||
F 3 "" H 2200 1750 60 0001 C CNN
|
||||
1 2200 1750
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:CONN_2 P1
|
||||
U 1 1 4B3A12F4
|
||||
P 1650 1400
|
||||
F 0 "P1" V 1600 1400 40 0000 C CNN
|
||||
F 1 "CONN_2" V 1700 1400 40 0000 C CNN
|
||||
F 2 "TerminalBlock_Altech:Altech_AK300_1x02_P5.00mm_45-Degree" H 1650 1200 10 0000 C CNN
|
||||
F 3 "" H 1650 1400 60 0001 C CNN
|
||||
1 1650 1400
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:HT #PWR08
|
||||
U 1 1 4B0FA68B
|
||||
P 2500 1250
|
||||
F 0 "#PWR08" H 2500 1370 20 0001 C CNN
|
||||
F 1 "HT" H 2500 1340 30 0000 C CNN
|
||||
F 2 "" H 2500 1250 10 0001 C CNN
|
||||
F 3 "" H 2500 1250 60 0001 C CNN
|
||||
1 2500 1250
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:CP C1
|
||||
U 1 1 4B03CEC2
|
||||
P 9200 1600
|
||||
F 0 "C1" H 9350 1650 50 0000 L CNN
|
||||
F 1 "47uF" H 9350 1600 50 0000 L TNN
|
||||
F 2 "Capacitor_THT:CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal" H 9500 1500 10 0000 C CNN
|
||||
F 3 "" H 9200 1600 60 0001 C CNN
|
||||
1 9200 1600
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:GND #PWR09
|
||||
U 1 1 4B03CEC1
|
||||
P 9200 1800
|
||||
F 0 "#PWR09" H 9200 1800 30 0001 C CNN
|
||||
F 1 "GND" H 9200 1730 30 0001 C CNN
|
||||
F 2 "" H 9200 1800 10 0001 C CNN
|
||||
F 3 "" H 9200 1800 60 0001 C CNN
|
||||
1 9200 1800
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:GND #PWR010
|
||||
U 1 1 4B03CE88
|
||||
P 7900 1650
|
||||
F 0 "#PWR010" H 7900 1650 30 0001 C CNN
|
||||
F 1 "GND" H 7900 1580 30 0001 C CNN
|
||||
F 2 "" H 7900 1650 10 0001 C CNN
|
||||
F 3 "" H 7900 1650 60 0001 C CNN
|
||||
1 7900 1650
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:+12C #PWR011
|
||||
U 1 1 4B03CE6C
|
||||
P 7400 1250
|
||||
F 0 "#PWR011" H 7400 1220 30 0001 C CNN
|
||||
F 1 "+12C" H 7400 1360 40 0000 C CNN
|
||||
F 2 "" H 7400 1250 10 0001 C CNN
|
||||
F 3 "" H 7400 1250 60 0001 C CNN
|
||||
1 7400 1250
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:PWR_FLAG #U012
|
||||
U 1 1 4B03CAA3
|
||||
P 2200 1250
|
||||
F 0 "#U012" H 2200 1520 30 0001 C CNN
|
||||
F 1 "PWR_FLAG" H 2200 1480 30 0000 C CNN
|
||||
F 2 "" H 2200 1250 10 0001 C CNN
|
||||
F 3 "" H 2200 1250 60 0001 C CNN
|
||||
1 2200 1250
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:PWR_FLAG #U013
|
||||
U 1 1 4B03C9F9
|
||||
P 3000 2450
|
||||
F 0 "#U013" H 3000 2720 30 0001 C CNN
|
||||
F 1 "PWR_FLAG" H 3000 2680 30 0000 C CNN
|
||||
F 2 "" H 3000 2450 10 0001 C CNN
|
||||
F 3 "" H 3000 2450 60 0001 C CNN
|
||||
1 3000 2450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:+12C #PWR014
|
||||
U 1 1 4B03C68D
|
||||
P 3800 2450
|
||||
F 0 "#PWR014" H 3800 2420 30 0001 C CNN
|
||||
F 1 "+12C" H 3800 2560 40 0000 C CNN
|
||||
F 2 "" H 3800 2450 10 0001 C CNN
|
||||
F 3 "" H 3800 2450 60 0001 C CNN
|
||||
1 3800 2450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:PWR_FLAG #U015
|
||||
U 1 1 4AE17C31
|
||||
P 2200 1650
|
||||
F 0 "#U015" H 2200 1920 30 0001 C CNN
|
||||
F 1 "PWR_FLAG" H 2200 1880 30 0000 C CNN
|
||||
F 2 "" H 2200 1650 10 0001 C CNN
|
||||
F 3 "" H 2200 1650 60 0001 C CNN
|
||||
1 2200 1650
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:+12V #U016
|
||||
U 1 1 4AE173EF
|
||||
P 3550 2450
|
||||
F 0 "#U016" H 3550 2400 20 0001 C CNN
|
||||
F 1 "+12V" H 3550 2550 40 0000 C CNN
|
||||
F 2 "" H 3550 2450 10 0001 C CNN
|
||||
F 3 "" H 3550 2450 60 0001 C CNN
|
||||
1 3550 2450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:GND #PWR017
|
||||
U 1 1 4AE173D0
|
||||
P 3200 3000
|
||||
F 0 "#PWR017" H 3200 3000 30 0001 C CNN
|
||||
F 1 "GND" H 3200 2930 30 0001 C CNN
|
||||
F 2 "" H 3200 3000 10 0001 C CNN
|
||||
F 3 "" H 3200 3000 60 0001 C CNN
|
||||
1 3200 3000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:CP C2
|
||||
U 1 1 4AE173CF
|
||||
P 3200 2750
|
||||
F 0 "C2" H 3350 2800 50 0000 L CNN
|
||||
F 1 "47uF/20V" H 3350 2700 50 0000 L TNN
|
||||
F 2 "Capacitor_THT:CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal" H 3550 2600 10 0000 C CNN
|
||||
F 3 "" H 3200 2750 60 0001 C CNN
|
||||
1 3200 2750
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:D_Small D1
|
||||
U 1 1 4AE172F4
|
||||
P 2700 2500
|
||||
F 0 "D1" H 2700 2400 40 0000 C CNN
|
||||
F 1 "1N4007" H 2700 2600 40 0000 C CNN
|
||||
F 2 "Diode_THT:D_DO-41_SOD81_P12.70mm_Horizontal" H 2700 2350 10 0000 C CNN
|
||||
F 3 "" H 2700 2500 60 0001 C CNN
|
||||
1 2700 2500
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:GND #PWR018
|
||||
U 1 1 4AD71B8E
|
||||
P 2100 2800
|
||||
F 0 "#PWR018" H 2100 2800 30 0001 C CNN
|
||||
F 1 "GND" H 2100 2730 30 0001 C CNN
|
||||
F 2 "" H 2100 2800 10 0001 C CNN
|
||||
F 3 "" H 2100 2800 60 0001 C CNN
|
||||
1 2100 2800
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L complex_hierarchy_schlib:CONN_2 P2
|
||||
U 1 1 4AD71B06
|
||||
P 1650 2600
|
||||
F 0 "P2" V 1600 2600 40 0000 C CNN
|
||||
F 1 "CONN_2" V 1700 2600 40 0000 C CNN
|
||||
F 2 "TerminalBlock_Altech:Altech_AK300_1x02_P5.00mm_45-Degree" H 1650 2400 10 0000 C CNN
|
||||
F 3 "" H 1650 2600 60 0001 C CNN
|
||||
1 1650 2600
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2200 1250 2200 1300
|
||||
Connection ~ 2200 1300
|
||||
Wire Wire Line
|
||||
2000 1300 2200 1300
|
||||
Wire Wire Line
|
||||
2000 1500 2100 1500
|
||||
Wire Wire Line
|
||||
2100 1500 2100 1700
|
||||
Wire Wire Line
|
||||
2100 1700 2200 1700
|
||||
Connection ~ 2200 1700
|
||||
Wire Wire Line
|
||||
9050 2300 9050 2250
|
||||
Wire Wire Line
|
||||
9050 2250 9200 2250
|
||||
Wire Wire Line
|
||||
7900 2200 7900 2250
|
||||
Wire Wire Line
|
||||
7900 1650 7900 1600
|
||||
Wire Wire Line
|
||||
7900 3600 7900 3550
|
||||
Wire Wire Line
|
||||
9200 2750 9350 2750
|
||||
Wire Wire Line
|
||||
2500 1300 2500 1350
|
||||
Wire Wire Line
|
||||
3200 2500 3550 2500
|
||||
Wire Wire Line
|
||||
3550 2500 3800 2500
|
||||
Wire Wire Line
|
||||
3000 2500 3200 2500
|
||||
Wire Wire Line
|
||||
9200 1300 9200 1450
|
||||
Wire Wire Line
|
||||
2200 1300 2500 1300
|
||||
Wire Wire Line
|
||||
2200 1700 2200 1750
|
||||
$EndSCHEMATC
|
||||
|
|
@ -0,0 +1,324 @@
|
|||
EESchema-LIBRARY Version 2.4
|
||||
#encoding utf-8
|
||||
#
|
||||
# +12C
|
||||
#
|
||||
DEF +12C #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "+12C" 0 150 50 H V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
P 2 0 1 0 -30 50 0 100 N
|
||||
P 2 0 1 0 0 0 0 100 N
|
||||
P 2 0 1 0 0 100 30 50 N
|
||||
X +12C 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# +12V
|
||||
#
|
||||
DEF +12V #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "+12V" 0 140 50 H V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
P 2 0 1 0 -30 50 0 100 N
|
||||
P 2 0 1 0 0 0 0 100 N
|
||||
P 2 0 1 0 0 100 30 50 N
|
||||
X +12V 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# -VAA
|
||||
#
|
||||
DEF -VAA #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 100 20 H I C CNN
|
||||
F1 "-VAA" 0 100 30 H V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
P 3 0 1 0 0 0 0 50 0 50 N
|
||||
P 7 0 1 0 0 80 30 50 -20 50 -30 50 0 80 0 80 0 80 F
|
||||
X -VAA 1 0 0 0 U 20 20 0 0 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# 7805
|
||||
#
|
||||
DEF 7805 U 0 20 Y Y 1 F N
|
||||
F0 "U" 150 -196 60 H V C CNN
|
||||
F1 "7805" 0 200 60 H V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
ALIAS 78L05 LM7805 LM7812
|
||||
DRAW
|
||||
S -200 -150 200 150 0 1 0 N
|
||||
X VO 1 400 50 200 L 30 40 1 1 w
|
||||
X GND 2 0 -250 100 U 30 40 1 1 I
|
||||
X VI 3 -400 50 200 R 30 40 1 1 I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# C
|
||||
#
|
||||
DEF C C 0 10 N Y 1 F N
|
||||
F0 "C" 25 100 50 H V L CNN
|
||||
F1 "C" 25 -100 50 H V L CNN
|
||||
F2 "" 38 -150 30 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
$FPLIST
|
||||
C?
|
||||
C_????_*
|
||||
C_????
|
||||
SMD*_c
|
||||
Capacitor*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
P 2 0 1 20 -80 -30 80 -30 N
|
||||
P 2 0 1 20 -80 30 80 30 N
|
||||
X ~ 1 0 150 110 D 40 40 1 1 P
|
||||
X ~ 2 0 -150 110 U 40 40 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# CONN_2
|
||||
#
|
||||
DEF CONN_2 P 0 40 Y N 1 F N
|
||||
F0 "P" -50 0 40 V V C CNN
|
||||
F1 "CONN_2" 50 0 40 V V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
S -100 150 100 -150 0 1 0 N
|
||||
X P1 1 -350 100 250 R 60 60 1 1 P I
|
||||
X PM 2 -350 -100 250 R 60 60 1 1 P I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# CP
|
||||
#
|
||||
DEF CP C 0 10 N Y 1 F N
|
||||
F0 "C" 25 100 50 H V L CNN
|
||||
F1 "CP" 25 -100 50 H V L CNN
|
||||
F2 "" 38 -150 30 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
$FPLIST
|
||||
CP*
|
||||
Elko*
|
||||
TantalC*
|
||||
C*elec
|
||||
c_elec*
|
||||
SMD*_Pol
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -90 20 -90 40 0 1 0 N
|
||||
S -90 20 90 20 0 1 0 N
|
||||
S -70 90 -30 90 0 1 0 N
|
||||
S -50 70 -50 110 0 1 0 N
|
||||
S 90 -20 -90 -40 0 1 0 F
|
||||
S 90 40 -90 40 0 1 0 N
|
||||
S 90 40 90 20 0 1 0 N
|
||||
X ~ 1 0 150 110 D 40 40 1 1 P
|
||||
X ~ 2 0 -150 110 U 40 40 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# D_Small
|
||||
#
|
||||
DEF D_Small D 0 10 N N 1 F N
|
||||
F0 "D" -50 80 50 H V L CNN
|
||||
F1 "D_Small" -150 -80 50 H V L CNN
|
||||
F2 "" 0 0 60 V V C CNN
|
||||
F3 "" 0 0 60 V V C CNN
|
||||
$FPLIST
|
||||
Diode_*
|
||||
D-Pak_TO252AA
|
||||
*SingleDiode
|
||||
*SingleDiode*
|
||||
*_Diode_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
P 2 0 1 0 -30 -40 -30 40 N
|
||||
P 4 0 1 0 30 -40 -30 0 30 40 30 -40 F
|
||||
X K 1 -100 0 70 R 50 50 1 1 P
|
||||
X A 2 100 0 70 L 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# GND
|
||||
#
|
||||
DEF GND #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "GND" 0 -123 30 H V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
|
||||
X GND 1 0 0 0 D 20 30 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# HT
|
||||
#
|
||||
DEF HT #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 120 50 H I C CNN
|
||||
F1 "HT" 0 90 50 H V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
P 3 0 1 0 0 0 0 40 0 40 N
|
||||
P 6 0 1 0 0 40 20 20 0 70 -20 20 0 40 0 40 N
|
||||
X HT 1 0 0 0 U 20 20 0 0 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# ICL7660
|
||||
#
|
||||
DEF ICL7660 U 0 40 Y Y 1 F N
|
||||
F0 "U" 200 400 70 H V L CNN
|
||||
F1 "ICL7660" 50 -450 70 H V L CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
S -550 -350 550 350 0 1 0 N
|
||||
X CAP+ 2 -850 250 300 R 60 60 1 1 I
|
||||
X GND 3 -50 -650 300 U 60 60 1 1 W
|
||||
X CAP- 4 -850 50 300 R 60 60 1 1 I
|
||||
X VOUT 5 850 150 300 L 60 60 1 1 w
|
||||
X LV 6 850 -150 300 L 60 60 1 1 I
|
||||
X OSC 7 -850 -150 300 R 60 60 1 1 I
|
||||
X V+ 8 -50 650 300 D 60 60 1 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# LM358
|
||||
#
|
||||
DEF LM358 U 0 20 Y Y 2 F N
|
||||
F0 "U" -50 200 60 H V L CNN
|
||||
F1 "LM358" -50 -250 60 H V L CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
ALIAS LM358N LMC6062 LMC6082 TL072 TL082
|
||||
DRAW
|
||||
P 4 0 1 6 -200 200 200 0 -200 -200 -200 200 f
|
||||
X V- 4 -100 -400 250 U 40 40 0 1 W
|
||||
X V+ 8 -100 400 250 D 40 40 0 1 W
|
||||
X ~ 1 500 0 300 L 40 40 1 1 O
|
||||
X - 2 -500 -100 300 R 40 40 1 1 I
|
||||
X + 3 -500 100 300 R 40 40 1 1 I
|
||||
X + 5 -500 100 300 R 40 40 2 1 I
|
||||
X - 6 -500 -100 300 R 40 40 2 1 I
|
||||
X ~ 7 500 0 300 L 40 40 2 1 O
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# MPSA42
|
||||
#
|
||||
DEF MPSA42 Q 0 0 Y Y 1 F N
|
||||
F0 "Q" 150 -150 60 H V L CNN
|
||||
F1 "MPSA42" 150 150 60 H V L CNN
|
||||
F2 "TO92-CBE" 150 0 30 H I C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
$FPLIST
|
||||
TO92-CBE
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C 50 0 111 0 1 10 N
|
||||
P 2 0 1 0 0 0 100 100 N
|
||||
P 3 0 1 10 0 75 0 -75 0 -75 N
|
||||
P 3 0 1 0 50 -50 0 0 0 0 N
|
||||
P 3 0 1 0 90 -90 100 -100 100 -100 N
|
||||
P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F
|
||||
X E 1 100 -200 100 U 20 20 1 1 P
|
||||
X B 2 -200 0 200 R 20 20 1 1 I
|
||||
X C 3 100 200 100 D 20 20 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# MPSA92
|
||||
#
|
||||
DEF MPSA92 Q 0 0 Y Y 1 F N
|
||||
F0 "Q" 150 -150 60 H V L CNN
|
||||
F1 "MPSA92" 150 150 60 H V L CNN
|
||||
F2 "TO92-CBE" 150 0 30 H I C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
$FPLIST
|
||||
TO92-CBE
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C 50 0 111 0 1 10 N
|
||||
P 2 0 1 0 0 0 100 100 N
|
||||
P 3 0 1 10 0 75 0 -75 0 -75 F
|
||||
P 3 0 1 0 25 -25 0 0 0 0 N
|
||||
P 3 0 1 0 100 -100 65 -65 65 -65 N
|
||||
P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F
|
||||
X E 1 100 -200 100 U 20 20 1 1 P
|
||||
X B 2 -200 0 200 R 20 20 1 1 I
|
||||
X C 3 100 200 100 D 20 20 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# POT
|
||||
#
|
||||
DEF POT RV 0 40 Y N 1 F N
|
||||
F0 "RV" 0 -100 50 H V C CNN
|
||||
F1 "POT" 0 0 50 H V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
S -150 50 150 -50 0 1 0 N
|
||||
P 3 0 1 0 0 50 -20 70 20 70 F
|
||||
X 1 1 -250 0 100 R 40 40 1 1 P
|
||||
X 2 2 0 150 80 D 40 40 1 1 P
|
||||
X 3 3 250 0 100 L 40 40 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# PWR_FLAG
|
||||
#
|
||||
DEF PWR_FLAG #FLG 0 0 N N 1 F P
|
||||
F0 "#FLG" 0 95 50 H I C CNN
|
||||
F1 "PWR_FLAG" 0 180 50 H V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
|
||||
X pwr 1 0 0 0 U 20 20 0 0 w
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# R
|
||||
#
|
||||
DEF R R 0 0 N Y 1 F N
|
||||
F0 "R" 80 0 50 V V C CNN
|
||||
F1 "R" 0 0 50 V V C CNN
|
||||
F2 "" -70 0 30 V V C CNN
|
||||
F3 "" 0 0 30 H V C CNN
|
||||
$FPLIST
|
||||
R_*
|
||||
Resistor_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -40 -100 40 100 0 1 10 N
|
||||
X ~ 1 0 150 50 D 60 60 1 1 P
|
||||
X ~ 2 0 -150 50 U 60 60 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# VCC
|
||||
#
|
||||
DEF VCC #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "VCC" 0 150 50 H V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
C 0 75 25 0 1 0 N
|
||||
P 2 0 1 0 0 0 0 50 N
|
||||
X VCC 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
(fp_lib_table
|
||||
(lib (name "Package_DIP")(type "KiCad")(uri "$(KISYSMOD)/Package_DIP.pretty")(options "")(descr ""))
|
||||
(lib (name "Capacitor_THT")(type "KiCad")(uri "$(KISYSMOD)/Capacitor_THT.pretty")(options "")(descr ""))
|
||||
(lib (name "Resistor_THT")(type "KiCad")(uri "$(KISYSMOD)/Resistor_THT.pretty")(options "")(descr ""))
|
||||
(lib (name "Package_TO_SOT_THT")(type "KiCad")(uri "$(KISYSMOD)/Package_TO_SOT_THT.pretty")(options "")(descr ""))
|
||||
(lib (name "TerminalBlock_Altech")(type "KiCad")(uri "${KISYSMOD}/TerminalBlock_Altech.pretty")(options "")(descr ""))
|
||||
(lib (name "Potentiometer_THT")(type "KiCad")(uri "${KISYSMOD}/Potentiometer_THT.pretty")(options "")(descr ""))
|
||||
)
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
(sym_lib_table
|
||||
(lib (name complex_hierarchy_schlib)(type Legacy)(uri ${KIPRJMOD}/complex_hierarchy_schlib.lib)(options "")(descr ""))
|
||||
)
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
EESchema Schematic File Version 5
|
||||
EELAYER 31 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 2 2
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
Comment5 ""
|
||||
Comment6 ""
|
||||
Comment7 ""
|
||||
Comment8 ""
|
||||
Comment9 ""
|
||||
$EndDescr
|
||||
Wire Wire Line
|
||||
2850 2000 4050 2000
|
||||
Text Label 4050 2000 2 50 ~ 0
|
||||
5V
|
||||
Text GLabel 2850 2000 0 50 Input ~ 0
|
||||
5Vanalog
|
||||
$EndSCHEMATC
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
EESchema-LIBRARY Version 2.4
|
||||
#encoding utf-8
|
||||
#
|
||||
# Device_C
|
||||
#
|
||||
DEF Device_C C 0 10 N Y 1 F N
|
||||
F0 "C" 25 100 50 H V L CNN
|
||||
F1 "Device_C" 25 -100 50 H V L CNN
|
||||
F2 "" 38 -150 50 H I C CNN
|
||||
F3 "~" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
C_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
P 2 0 1 20 -80 -30 80 -30 N
|
||||
P 2 0 1 20 -80 30 80 30 N
|
||||
X ~ 1 0 150 110 D 50 50 1 1 P
|
||||
X ~ 2 0 -150 110 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_R
|
||||
#
|
||||
DEF Device_R R 0 0 N Y 1 F N
|
||||
F0 "R" 80 0 50 V V C CNN
|
||||
F1 "Device_R" 0 0 50 V V C CNN
|
||||
F2 "" -70 0 50 V I C CNN
|
||||
F3 "~" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
R_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -40 -100 40 100 0 1 10 N
|
||||
X ~ 1 0 150 50 D 50 50 1 1 P
|
||||
X ~ 2 0 -150 50 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_GND
|
||||
#
|
||||
DEF power_GND #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -250 50 H I C CNN
|
||||
F1 "power_GND" 0 -150 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
|
||||
X GND 1 0 0 0 D 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
(export (version "D")
|
||||
(design
|
||||
(source "/home/jon/work/kicad-master/qa/eeschema/data/netlists/test_global_promotion/test_global_promotion.sch")
|
||||
(date "Sun 19 Apr 2020 16:13:42 EDT")
|
||||
(tool "Eeschema (5.99.0-1347-g0d2b30b74-dirty)")
|
||||
(sheet (number "1") (name "/") (tstamps "/")
|
||||
(title_block
|
||||
(title)
|
||||
(company)
|
||||
(rev)
|
||||
(date)
|
||||
(source "test_global_promotion.sch")
|
||||
(comment (number "1") (value ""))
|
||||
(comment (number "2") (value ""))
|
||||
(comment (number "3") (value ""))
|
||||
(comment (number "4") (value ""))
|
||||
(comment (number "5") (value ""))
|
||||
(comment (number "6") (value ""))
|
||||
(comment (number "7") (value ""))
|
||||
(comment (number "8") (value ""))
|
||||
(comment (number "9") (value ""))))
|
||||
(sheet (number "2") (name "/Subcircuit/") (tstamps "/00000000-0000-0000-0000-00005e68e19b/")
|
||||
(title_block
|
||||
(title)
|
||||
(company)
|
||||
(rev)
|
||||
(date)
|
||||
(source "Sub.sch")
|
||||
(comment (number "1") (value ""))
|
||||
(comment (number "2") (value ""))
|
||||
(comment (number "3") (value ""))
|
||||
(comment (number "4") (value ""))
|
||||
(comment (number "5") (value ""))
|
||||
(comment (number "6") (value ""))
|
||||
(comment (number "7") (value ""))
|
||||
(comment (number "8") (value ""))
|
||||
(comment (number "9") (value "")))))
|
||||
(components
|
||||
(comp (ref "C1")
|
||||
(value "C")
|
||||
(footprint "Capacitor_THT:CP_Axial_L18.0mm_D8.0mm_P25.00mm_Horizontal")
|
||||
(datasheet "~")
|
||||
(libsource (lib "Device") (part "C") (description "Unpolarized capacitor"))
|
||||
(sheetpath (names "/") (tstamps "/"))
|
||||
(tstamp "00000000-0000-0000-0000-00005e68c688"))
|
||||
(comp (ref "R1")
|
||||
(value "R")
|
||||
(footprint "Resistor_THT:R_Axial_Power_L25.0mm_W6.4mm_P30.48mm")
|
||||
(datasheet "~")
|
||||
(libsource (lib "Device") (part "R") (description "Resistor"))
|
||||
(sheetpath (names "/") (tstamps "/"))
|
||||
(tstamp "00000000-0000-0000-0000-00005e68b6bd")))
|
||||
(libparts
|
||||
(libpart (lib "Device") (part "C")
|
||||
(description "Unpolarized capacitor")
|
||||
(docs "~")
|
||||
(footprints
|
||||
(fp "C_*"))
|
||||
(fields
|
||||
(field (name "Reference") "C")
|
||||
(field (name "Value") "C")
|
||||
(field (name "Datasheet") "~"))
|
||||
(pins
|
||||
(pin (num "1") (name "~") (type "passive"))
|
||||
(pin (num "2") (name "~") (type "passive"))))
|
||||
(libpart (lib "Device") (part "R")
|
||||
(description "Resistor")
|
||||
(docs "~")
|
||||
(footprints
|
||||
(fp "R_*"))
|
||||
(fields
|
||||
(field (name "Reference") "R")
|
||||
(field (name "Value") "R")
|
||||
(field (name "Datasheet") "~"))
|
||||
(pins
|
||||
(pin (num "1") (name "~") (type "passive"))
|
||||
(pin (num "2") (name "~") (type "passive")))))
|
||||
(libraries
|
||||
(library (logical "Device")
|
||||
(uri "/home/jon/kicad-library/kicad-symbols//Device.lib")))
|
||||
(nets
|
||||
(net (code "1") (name "5V")
|
||||
(node (ref "R1") (pin "1")))
|
||||
(net (code "2") (name "5Vanalog")
|
||||
(node (ref "C1") (pin "1"))
|
||||
(node (ref "R1") (pin "2")))
|
||||
(net (code "3") (name "GND")
|
||||
(node (ref "C1") (pin "2")))))
|
||||
|
|
@ -0,0 +1,251 @@
|
|||
update=ven. 06 mars 2020 00:05:42 CET
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[SchematicFrame]
|
||||
version=1
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=
|
||||
LastSTEPExportPath=
|
||||
LastIDFExportPath=
|
||||
LastVRMLExportPath=
|
||||
LastSpecctraDSNExportPath=
|
||||
LastGenCADExportPath=
|
||||
CopperLayerCount=2
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
MinTrackWidth=0.2
|
||||
MinViaDiameter=0.4
|
||||
MinViaDrill=0.3
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
CopperEdgeClearance=0.01
|
||||
TrackWidth1=0.25
|
||||
ViaDiameter1=0.8
|
||||
ViaDrill1=0.4
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.12
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=0
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=0
|
||||
EdgeCutLineWidth=0.05
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.09999999999999999
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=0
|
||||
DimensionUnits=0
|
||||
DimensionPrecision=1
|
||||
SolderMaskClearance=0.051
|
||||
SolderMaskMinWidth=0.25
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=1
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.2
|
||||
TrackWidth=0.25
|
||||
ViaDiameter=0.8
|
||||
ViaDrill=0.4
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
[sheetnames]
|
||||
1=00000000-0000-0000-0000-00005e6184cb:Sheet00000000-0000-0000-0000-00005e6184cb
|
||||
2=00000000-0000-0000-0000-00005e68e19b:Subcircuit
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
EESchema Schematic File Version 5
|
||||
EELAYER 31 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 1 2
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
Comment5 ""
|
||||
Comment6 ""
|
||||
Comment7 ""
|
||||
Comment8 ""
|
||||
Comment9 ""
|
||||
$EndDescr
|
||||
Connection ~ 3650 1700
|
||||
Wire Wire Line
|
||||
3000 1700 3250 1700
|
||||
Wire Wire Line
|
||||
3550 1700 3650 1700
|
||||
Wire Wire Line
|
||||
3650 1700 3650 1850
|
||||
Wire Wire Line
|
||||
3650 1700 3850 1700
|
||||
Wire Wire Line
|
||||
3650 2150 3650 2250
|
||||
Text GLabel 3000 1700 0 50 Input ~ 0
|
||||
5V
|
||||
Text GLabel 3850 1700 2 50 Output ~ 0
|
||||
5Vanalog
|
||||
$Comp
|
||||
L power:GND #PWR0101
|
||||
U 1 1 5E68CE9F
|
||||
P 3650 2250
|
||||
F 0 "#PWR0101" H 3650 2000 50 0001 C CNN
|
||||
F 1 "GND" H 3655 2077 50 0000 C CNN
|
||||
F 2 "" H 3650 2250 50 0001 C CNN
|
||||
F 3 "" H 3650 2250 50 0001 C CNN
|
||||
1 3650 2250
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R R1
|
||||
U 1 1 5E68B6BD
|
||||
P 3400 1700
|
||||
F 0 "R1" V 3606 1700 50 0000 C CNN
|
||||
F 1 "R" V 3515 1700 50 0000 C CNN
|
||||
F 2 "Resistor_THT:R_Axial_Power_L25.0mm_W6.4mm_P30.48mm" V 3330 1700 50 0001 C CNN
|
||||
F 3 "~" H 3400 1700 50 0001 C CNN
|
||||
1 3400 1700
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:C C1
|
||||
U 1 1 5E68C688
|
||||
P 3650 2000
|
||||
F 0 "C1" H 3765 2045 50 0000 L CNN
|
||||
F 1 "C" H 3765 1955 50 0000 L CNN
|
||||
F 2 "Capacitor_THT:CP_Axial_L18.0mm_D8.0mm_P25.00mm_Horizontal" H 3688 1850 50 0001 C CNN
|
||||
F 3 "~" H 3650 2000 50 0001 C CNN
|
||||
1 3650 2000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Sheet
|
||||
S 4900 1500 450 600
|
||||
U 5E68E19B
|
||||
F0 "Subcircuit" 50
|
||||
F1 "Sub.sch" 50
|
||||
$EndSheet
|
||||
$EndSCHEMATC
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,3 @@
|
|||
EESchema-DOCLIB Version 2.0
|
||||
#
|
||||
#End Doc Library
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,997 @@
|
|||
EESchema Schematic File Version 5
|
||||
EELAYER 33 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 6 8
|
||||
Title "Video"
|
||||
Date "Sun 22 Mar 2015"
|
||||
Rev "2.0B"
|
||||
Comp "Kicad EDA"
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
Comment5 ""
|
||||
Comment6 ""
|
||||
Comment7 ""
|
||||
Comment8 ""
|
||||
Comment9 ""
|
||||
$EndDescr
|
||||
Connection ~ 2500 1800
|
||||
Connection ~ 7100 1200
|
||||
Connection ~ 6900 2700
|
||||
Connection ~ 5200 3000
|
||||
Connection ~ 5800 3000
|
||||
Connection ~ 6800 3850
|
||||
Connection ~ 3900 1500
|
||||
Connection ~ 5500 4600
|
||||
Connection ~ 9800 4700
|
||||
Connection ~ 9800 3100
|
||||
Connection ~ 9800 1500
|
||||
Connection ~ 3500 1500
|
||||
Connection ~ 7200 1200
|
||||
NoConn ~ 2600 3000
|
||||
NoConn ~ 2600 3100
|
||||
NoConn ~ 2600 2900
|
||||
NoConn ~ 2600 2800
|
||||
Wire Wire Line
|
||||
950 3200 950 3450
|
||||
Wire Wire Line
|
||||
950 3900 950 3850
|
||||
Wire Wire Line
|
||||
1500 3900 2600 3900
|
||||
Wire Wire Line
|
||||
1500 3950 1500 3900
|
||||
Wire Wire Line
|
||||
1500 4400 1500 4350
|
||||
Wire Wire Line
|
||||
1600 3600 1550 3600
|
||||
Wire Wire Line
|
||||
1950 3300 2000 3300
|
||||
Wire Wire Line
|
||||
2100 3500 1550 3500
|
||||
Wire Wire Line
|
||||
2100 3700 1550 3700
|
||||
Wire Wire Line
|
||||
2100 4100 2100 4500
|
||||
Wire Wire Line
|
||||
2100 5150 2100 5100
|
||||
Wire Wire Line
|
||||
2100 5600 2100 5550
|
||||
Wire Wire Line
|
||||
2400 1800 2500 1800
|
||||
Wire Wire Line
|
||||
2500 1800 2500 1950
|
||||
Wire Wire Line
|
||||
2500 1800 2700 1800
|
||||
Wire Wire Line
|
||||
2500 2350 2500 2600
|
||||
Wire Wire Line
|
||||
2500 2600 2600 2600
|
||||
Wire Wire Line
|
||||
2500 3300 2600 3300
|
||||
Wire Wire Line
|
||||
2600 3200 950 3200
|
||||
Wire Wire Line
|
||||
2600 3500 2500 3500
|
||||
Wire Wire Line
|
||||
2600 3600 2000 3600
|
||||
Wire Wire Line
|
||||
2600 3700 2500 3700
|
||||
Wire Wire Line
|
||||
2600 4100 2100 4100
|
||||
Wire Wire Line
|
||||
3300 1800 3200 1800
|
||||
Wire Wire Line
|
||||
3300 1850 3300 1800
|
||||
Wire Wire Line
|
||||
3500 1450 3500 1500
|
||||
Wire Wire Line
|
||||
3500 1500 3500 2250
|
||||
Wire Wire Line
|
||||
3500 1500 3900 1500
|
||||
Wire Wire Line
|
||||
3500 4500 3500 4450
|
||||
Wire Wire Line
|
||||
3900 1500 3900 1600
|
||||
Wire Wire Line
|
||||
3900 1500 4000 1500
|
||||
Wire Wire Line
|
||||
3900 2050 3900 2000
|
||||
Wire Wire Line
|
||||
4400 2700 6900 2700
|
||||
Wire Wire Line
|
||||
4400 3000 5200 3000
|
||||
Wire Wire Line
|
||||
4400 3200 4900 3200
|
||||
Wire Wire Line
|
||||
4400 3300 4900 3300
|
||||
Wire Wire Line
|
||||
4400 3400 4900 3400
|
||||
Wire Wire Line
|
||||
4400 3600 5500 3600
|
||||
Wire Wire Line
|
||||
4400 3700 5500 3700
|
||||
Wire Wire Line
|
||||
4400 3900 4500 3900
|
||||
Wire Wire Line
|
||||
4450 3800 4400 3800
|
||||
Wire Wire Line
|
||||
4500 2400 4500 2600
|
||||
Wire Wire Line
|
||||
4500 2600 4400 2600
|
||||
Wire Wire Line
|
||||
4500 3900 4500 4000
|
||||
Wire Wire Line
|
||||
4500 4450 4500 4400
|
||||
Wire Wire Line
|
||||
4600 1500 4700 1500
|
||||
Wire Wire Line
|
||||
4600 2400 4500 2400
|
||||
Wire Wire Line
|
||||
5100 2400 5350 2400
|
||||
Wire Wire Line
|
||||
5200 3000 5200 3100
|
||||
Wire Wire Line
|
||||
5200 3000 5800 3000
|
||||
Wire Wire Line
|
||||
5500 3700 5500 3900
|
||||
Wire Wire Line
|
||||
5500 4500 5500 4600
|
||||
Wire Wire Line
|
||||
5500 4600 5500 4700
|
||||
Wire Wire Line
|
||||
5500 5150 5500 5100
|
||||
Wire Wire Line
|
||||
5800 3000 5800 3300
|
||||
Wire Wire Line
|
||||
5800 3000 6300 3000
|
||||
Wire Wire Line
|
||||
5800 3300 5900 3300
|
||||
Wire Wire Line
|
||||
5950 2400 6900 2400
|
||||
Wire Wire Line
|
||||
6000 3600 6100 3600
|
||||
Wire Wire Line
|
||||
6200 4600 5500 4600
|
||||
Wire Wire Line
|
||||
6200 4700 6200 4600
|
||||
Wire Wire Line
|
||||
6200 5100 6200 5150
|
||||
Wire Wire Line
|
||||
6350 3750 6350 3850
|
||||
Wire Wire Line
|
||||
6350 3850 6800 3850
|
||||
Wire Wire Line
|
||||
6800 3600 6600 3600
|
||||
Wire Wire Line
|
||||
6800 3850 6800 3600
|
||||
Wire Wire Line
|
||||
6800 3950 6800 3850
|
||||
Wire Wire Line
|
||||
6900 1200 7100 1200
|
||||
Wire Wire Line
|
||||
6900 2400 6900 2700
|
||||
Wire Wire Line
|
||||
6900 2700 6900 3000
|
||||
Wire Wire Line
|
||||
6900 3000 6800 3000
|
||||
Wire Wire Line
|
||||
7100 1200 7100 1100
|
||||
Wire Wire Line
|
||||
7100 1200 7200 1200
|
||||
Wire Wire Line
|
||||
7200 1200 7200 1300
|
||||
Wire Wire Line
|
||||
7200 1200 7300 1200
|
||||
Wire Wire Line
|
||||
7200 1750 7200 1700
|
||||
Wire Wire Line
|
||||
7900 1200 8000 1200
|
||||
Wire Wire Line
|
||||
8400 1200 8900 1200
|
||||
Wire Wire Line
|
||||
8400 4400 8900 4400
|
||||
Wire Wire Line
|
||||
8500 2800 8900 2800
|
||||
Wire Wire Line
|
||||
9400 1200 9500 1200
|
||||
Wire Wire Line
|
||||
9400 2800 9500 2800
|
||||
Wire Wire Line
|
||||
9400 4400 9500 4400
|
||||
Wire Wire Line
|
||||
9800 900 9800 1000
|
||||
Wire Wire Line
|
||||
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|
||||
Wire Wire Line
|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
9800 4600 9800 4700
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
RED
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
YOUT
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||||
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||||
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||||
$Comp
|
||||
L video_schlib:VCC #PWR011
|
||||
U 1 1 33A51A5E
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||||
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||||
F 0 "#PWR011" H 1950 3500 40 0001 C CNN
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||||
F 1 "VCC" V 1950 3450 40 0000 C CNN
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||||
F 2 "" H 1950 3300 60 0001 C CNN
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||||
F 3 "" H 1950 3300 60 0001 C CNN
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||||
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||||
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||||
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||||
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|
||||
L video_schlib:VCC #VCC028
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
L video_schlib:VCC #VCC033
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
L video_schlib:+5F #+030
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||||
F 1 "+5F" H 7100 1250 40 0000 C CNN
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||||
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||||
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||||
L video_schlib:+5F #+029
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||||
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||||
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F 3 "" H 9800 900 60 0001 C CNN
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||||
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$Comp
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L video_schlib:+5F #+031
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F 3 "" H 9800 2500 60 0001 C CNN
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||||
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$Comp
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||||
L video_schlib:+5F #+032
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||||
F 1 "+5F" H 9800 4250 40 0000 C CNN
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||||
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F 3 "" H 9800 4100 60 0001 C CNN
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||||
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$Comp
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L video_schlib:GND #GND015
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F 1 "GND" H 950 3830 40 0001 C CNN
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F 2 "" H 950 3900 60 0001 C CNN
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F 3 "" H 950 3900 60 0001 C CNN
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||||
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L video_schlib:GND #GND014
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||||
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||||
F 2 "" H 1500 4400 60 0001 C CNN
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||||
F 3 "" H 1500 4400 60 0001 C CNN
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||||
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L video_schlib:GND #GND016
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||||
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F 2 "" H 2100 5600 60 0001 C CNN
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F 3 "" H 2100 5600 60 0001 C CNN
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||||
$Comp
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L video_schlib:GND #GND020
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|
||||
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|
||||
F 2 "" H 3300 1850 60 0001 C CNN
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F 3 "" H 3300 1850 60 0001 C CNN
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||||
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||||
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L video_schlib:GND #GND012
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||||
F 1 "GND" H 3500 4400 60 0001 C CNN
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||||
F 2 "" H 3500 4500 60 0001 C CNN
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||||
F 3 "" H 3500 4500 60 0001 C CNN
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||||
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||||
$Comp
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||||
L video_schlib:GND #GND013
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||||
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|
||||
F 1 "GND" H 3900 1950 60 0001 C CNN
|
||||
F 2 "" H 3900 2050 60 0001 C CNN
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F 3 "" H 3900 2050 60 0001 C CNN
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||||
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$Comp
|
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L video_schlib:GND #PWR010
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||||
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L video_schlib:GND #GND019
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L video_schlib:GND #GND018
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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F 3 "" H 7600 1200 60 0001 C CNN
|
||||
1 7600 1200
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|
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|
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|
||||
F 3 "" H 2150 1800 60 0001 C CNN
|
||||
1 2150 1800
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|
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||||
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|
||||
F 3 "" H 2250 3300 60 0001 C CNN
|
||||
F 4 "~" V 2250 3220 50 0001 C CNN "Champ7"
|
||||
1 2250 3300
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L video_schlib:R R31
|
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||||
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|
||||
F 2 "Resistor_SMD:R_1206_3216Metric_Pad1.24x1.80mm_HandSolder" H 2950 1800 60 0001 C CNN
|
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F 3 "" H 2950 1800 60 0001 C CNN
|
||||
1 2950 1800
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L video_schlib:R R10
|
||||
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|
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||||
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||||
F 2 "Resistor_SMD:R_1206_3216Metric_Pad1.24x1.80mm_HandSolder" H 4850 2400 60 0001 C CNN
|
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F 3 "" H 4850 2400 60 0001 C CNN
|
||||
1 4850 2400
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$Comp
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L video_schlib:R R9
|
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||||
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||||
F 2 "Resistor_SMD:R_1206_3216Metric_Pad1.24x1.80mm_HandSolder" H 5750 3600 60 0001 C CNN
|
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F 3 "" H 5750 3600 60 0001 C CNN
|
||||
1 5750 3600
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$EndComp
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$Comp
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L video_schlib:R R11
|
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U 1 1 22760FBC
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P 6550 3000
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F 0 "R11" V 6630 3000 50 0000 C CNN
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||||
F 1 "1K" V 6550 3000 50 0000 C CNN
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F 2 "Resistor_SMD:R_1206_3216Metric_Pad1.24x1.80mm_HandSolder" H 6550 3000 60 0001 C CNN
|
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F 3 "" H 6550 3000 60 0001 C CNN
|
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1 6550 3000
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
F 3 "" H 7200 1500 60 0001 C CNN
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
F 2 "Resistor_SMD:R_1206_3216Metric_Pad1.24x1.80mm_HandSolder" H 950 3650 60 0001 C CNN
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||||
F 3 "" H 950 3650 60 0001 C CNN
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||||
1 950 3650
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||||
1 0 0 -1
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
F 3 "" H 1500 4150 60 0001 C CNN
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
F 3 "" H 1800 3600 60 0001 C CNN
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
F 3 "" H 2300 3500 60 0001 C CNN
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
F 3 "" H 2300 3700 60 0001 C CNN
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||||
1 2300 3700
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||||
0 1 1 0
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||||
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||||
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||||
L video_schlib:C C61
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||||
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||||
F 1 "47nF" H 2600 2050 50 0000 C CNN
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||||
F 2 "Resistor_SMD:R_1206_3216Metric_Pad1.24x1.80mm_HandSolder" H 2500 2150 60 0001 C CNN
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||||
F 3 "" H 2500 2150 60 0001 C CNN
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||||
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||||
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||||
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||||
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||||
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||||
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||||
F 3 "" H 4500 4200 60 0001 C CNN
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||||
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1 0 0 -1
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||||
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||||
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||||
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||||
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||||
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||||
F 3 "" H 5200 3300 60 0001 C CNN
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||||
1 5200 3300
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||||
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||||
$EndComp
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||||
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||||
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||||
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||||
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||||
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||||
F 3 "" H 5500 4900 60 0001 C CNN
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||||
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||||
1 0 0 -1
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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1 0 0 -1
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||||
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||||
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||||
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||||
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||||
F 1 "5/30pF" H 2250 5190 50 0000 C CNN
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||||
F 2 "Discret:CV3-30PF" H 2100 5350 60 0001 C CNN
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||||
F 3 "" H 2100 5350 60 0001 C CNN
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||||
1 2100 5350
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||||
1 0 0 -1
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||||
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||||
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||||
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||||
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||||
F 3 "" H 6350 3600 60 0001 C CNN
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||||
1 6350 3600
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$EndComp
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||||
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||||
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||||
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||||
F 2 "Crystal:Crystal_HC18-U_Horizontal" H 2100 4800 60 0001 C CNN
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||||
F 3 "" H 2100 4800 60 0001 C CNN
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||||
1 2100 4800
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0 -1 -1 0
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||||
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||||
L video_schlib:NPN Q1
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||||
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||||
F 1 "BC848" H 9600 1350 50 0000 C CNN
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||||
F 2 "lib_smd:SOT23EBC" H 9700 1200 60 0001 C CNN
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||||
F 3 "" H 9700 1200 60 0001 C CNN
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||||
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||||
1 0 0 -1
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|
||||
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||||
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||||
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||||
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||||
F 2 "lib_smd:SOT23EBC" H 9700 2800 60 0001 C CNN
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||||
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||||
1 9700 2800
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||||
1 0 0 -1
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||||
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||||
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||||
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||||
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||||
F 2 "lib_smd:SOT23EBC" H 9700 4400 60 0001 C CNN
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||||
F 3 "" H 9700 4400 60 0001 C CNN
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||||
1 9700 4400
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1 0 0 -1
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$EndComp
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|
||||
L video_schlib:LIGNE_A_RETARD L6
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||||
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||||
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||||
F 2 "footprints:LRTDK" H 5650 2400 60 0001 C CNN
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||||
F 3 "" H 5650 2400 60 0001 C CNN
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||||
1 5650 2400
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||||
0 -1 -1 0
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||||
$EndComp
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||||
$Comp
|
||||
L video_schlib:TDA8501 U20
|
||||
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F 0 "U20" H 3500 3500 60 0000 C CNN
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||||
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||||
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||||
F 3 "" H 3500 3400 60 0001 C CNN
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||||
1 3500 3400
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1 0 0 -1
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$EndComp
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||||
$EndSCHEMATC
|
||||
|
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@ -0,0 +1,669 @@
|
|||
EESchema Schematic File Version 5
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||||
EELAYER 33 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 2 8
|
||||
Title "Video"
|
||||
Date "Sun 22 Mar 2015"
|
||||
Rev "2.0B"
|
||||
Comp "Kicad EDA"
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
Comment5 ""
|
||||
Comment6 ""
|
||||
Comment7 ""
|
||||
Comment8 ""
|
||||
Comment9 ""
|
||||
$EndDescr
|
||||
Connection ~ 2500 3200
|
||||
Connection ~ 2550 3300
|
||||
Connection ~ 2550 4500
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||||
Connection ~ 2500 4400
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||||
Connection ~ 2500 5600
|
||||
Connection ~ 2550 5700
|
||||
Connection ~ 6100 1700
|
||||
Connection ~ 6100 1600
|
||||
NoConn ~ 6100 4800
|
||||
NoConn ~ 8000 4300
|
||||
NoConn ~ 8000 4200
|
||||
NoConn ~ 6100 3100
|
||||
NoConn ~ 6100 2300
|
||||
NoConn ~ 6100 4000
|
||||
NoConn ~ 6100 3900
|
||||
NoConn ~ 6100 3800
|
||||
NoConn ~ 6100 3500
|
||||
NoConn ~ 6100 3000
|
||||
NoConn ~ 6100 2900
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||||
NoConn ~ 6100 2800
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||||
NoConn ~ 6100 2600
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||||
NoConn ~ 8000 3600
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||||
Wire Wire Line
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2400 5600 2500 5600
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Wire Wire Line
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2500 2000 2600 2000
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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2600 2300 2050 2300
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Wire Wire Line
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Wire Wire Line
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2600 2500 2050 2500
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Wire Wire Line
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2600 2600 2050 2600
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Wire Wire Line
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2600 2700 2050 2700
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Wire Wire Line
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Wire Wire Line
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2600 2900 2050 2900
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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2600 3300 2550 3300
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Wire Wire Line
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2600 3500 2050 3500
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Wire Wire Line
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2600 3600 2050 3600
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Wire Wire Line
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2600 3700 2050 3700
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Wire Wire Line
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2600 3800 2050 3800
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Wire Wire Line
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2600 3900 2050 3900
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Wire Wire Line
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2600 4000 2050 4000
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Wire Wire Line
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2600 4100 2050 4100
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Wire Wire Line
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2600 4200 2050 4200
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Wire Wire Line
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2600 4400 2500 4400
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||||
Wire Wire Line
|
||||
2600 4500 2550 4500
|
||||
Wire Wire Line
|
||||
2600 4700 2050 4700
|
||||
Wire Wire Line
|
||||
2600 4800 2050 4800
|
||||
Wire Wire Line
|
||||
2600 4900 2050 4900
|
||||
Wire Wire Line
|
||||
2600 5000 2050 5000
|
||||
Wire Wire Line
|
||||
2600 5100 2050 5100
|
||||
Wire Wire Line
|
||||
2600 5200 2050 5200
|
||||
Wire Wire Line
|
||||
2600 5300 2050 5300
|
||||
Wire Wire Line
|
||||
2600 5400 2050 5400
|
||||
Wire Wire Line
|
||||
2600 5700 2550 5700
|
||||
Wire Wire Line
|
||||
4000 1100 4550 1100
|
||||
Wire Wire Line
|
||||
4000 1200 4550 1200
|
||||
Wire Wire Line
|
||||
4000 1300 4550 1300
|
||||
Wire Wire Line
|
||||
4000 1400 4550 1400
|
||||
Wire Wire Line
|
||||
4000 1500 4550 1500
|
||||
Wire Wire Line
|
||||
4000 1600 4550 1600
|
||||
Wire Wire Line
|
||||
4000 1700 4550 1700
|
||||
Wire Wire Line
|
||||
4000 1800 4550 1800
|
||||
Wire Wire Line
|
||||
4000 2300 4550 2300
|
||||
Wire Wire Line
|
||||
4000 2400 4550 2400
|
||||
Wire Wire Line
|
||||
4000 2500 4550 2500
|
||||
Wire Wire Line
|
||||
4000 2600 4550 2600
|
||||
Wire Wire Line
|
||||
4000 2700 4550 2700
|
||||
Wire Wire Line
|
||||
4000 2800 4550 2800
|
||||
Wire Wire Line
|
||||
4000 2900 4550 2900
|
||||
Wire Wire Line
|
||||
4000 3000 4550 3000
|
||||
Wire Wire Line
|
||||
4000 3500 4550 3500
|
||||
Wire Wire Line
|
||||
4000 3600 4550 3600
|
||||
Wire Wire Line
|
||||
4000 3700 4550 3700
|
||||
Wire Wire Line
|
||||
4000 3800 4550 3800
|
||||
Wire Wire Line
|
||||
4000 3900 4550 3900
|
||||
Wire Wire Line
|
||||
4000 4000 4550 4000
|
||||
Wire Wire Line
|
||||
4000 4100 4550 4100
|
||||
Wire Wire Line
|
||||
4000 4200 4550 4200
|
||||
Wire Wire Line
|
||||
4000 4700 4550 4700
|
||||
Wire Wire Line
|
||||
4000 4800 4550 4800
|
||||
Wire Wire Line
|
||||
4000 4900 4550 4900
|
||||
Wire Wire Line
|
||||
4000 5000 4550 5000
|
||||
Wire Wire Line
|
||||
4000 5100 4550 5100
|
||||
Wire Wire Line
|
||||
4000 5200 4550 5200
|
||||
Wire Wire Line
|
||||
4000 5300 4550 5300
|
||||
Wire Wire Line
|
||||
4000 5400 4550 5400
|
||||
Wire Wire Line
|
||||
5650 2500 6100 2500
|
||||
Wire Wire Line
|
||||
5650 4100 6100 4100
|
||||
Wire Wire Line
|
||||
5650 4200 6100 4200
|
||||
Wire Wire Line
|
||||
5650 4300 6100 4300
|
||||
Wire Wire Line
|
||||
5650 4400 6100 4400
|
||||
Wire Wire Line
|
||||
5650 5000 6100 5000
|
||||
Wire Wire Line
|
||||
5650 5400 6100 5400
|
||||
Wire Wire Line
|
||||
5650 5500 6100 5500
|
||||
Wire Wire Line
|
||||
5650 5600 6100 5600
|
||||
Wire Wire Line
|
||||
5650 5700 6100 5700
|
||||
Wire Wire Line
|
||||
5650 5900 6100 5900
|
||||
Wire Wire Line
|
||||
5650 6000 6100 6000
|
||||
Wire Wire Line
|
||||
6100 1600 6100 1550
|
||||
Wire Wire Line
|
||||
6100 1700 6100 1600
|
||||
Wire Wire Line
|
||||
6100 1800 6100 1700
|
||||
Wire Wire Line
|
||||
6100 2400 5600 2400
|
||||
Wire Wire Line
|
||||
6100 4500 5350 4500
|
||||
Wire Wire Line
|
||||
6100 5200 5650 5200
|
||||
Wire Wire Line
|
||||
6100 5300 5650 5300
|
||||
Wire Wire Line
|
||||
8000 1800 8450 1800
|
||||
Wire Wire Line
|
||||
8000 1900 8450 1900
|
||||
Wire Wire Line
|
||||
8000 2000 8450 2000
|
||||
Wire Wire Line
|
||||
8000 2100 8450 2100
|
||||
Wire Wire Line
|
||||
8000 2200 8450 2200
|
||||
Wire Wire Line
|
||||
8000 2300 8450 2300
|
||||
Wire Wire Line
|
||||
8000 2600 8450 2600
|
||||
Wire Wire Line
|
||||
8000 2700 8450 2700
|
||||
Wire Wire Line
|
||||
8000 2800 8450 2800
|
||||
Wire Wire Line
|
||||
8000 2900 8450 2900
|
||||
Wire Wire Line
|
||||
8000 3000 8450 3000
|
||||
Wire Wire Line
|
||||
8000 3100 8450 3100
|
||||
Wire Wire Line
|
||||
8000 3400 8500 3400
|
||||
Wire Wire Line
|
||||
8000 3500 8450 3500
|
||||
Wire Wire Line
|
||||
8000 3700 8450 3700
|
||||
Wire Wire Line
|
||||
8000 3800 8450 3800
|
||||
Wire Wire Line
|
||||
8000 3900 8450 3900
|
||||
Wire Wire Line
|
||||
8000 4000 8450 4000
|
||||
Wire Wire Line
|
||||
8000 4100 8450 4100
|
||||
Wire Wire Line
|
||||
8000 4700 8450 4700
|
||||
Wire Wire Line
|
||||
8000 4800 8450 4800
|
||||
Wire Wire Line
|
||||
8000 4900 8450 4900
|
||||
Wire Wire Line
|
||||
8000 5000 8450 5000
|
||||
Wire Wire Line
|
||||
8000 5100 8450 5100
|
||||
Wire Wire Line
|
||||
8000 5400 8450 5400
|
||||
Wire Wire Line
|
||||
8000 5500 8450 5500
|
||||
Wire Wire Line
|
||||
8000 5600 8450 5600
|
||||
Wire Wire Line
|
||||
8000 5700 8450 5700
|
||||
Wire Wire Line
|
||||
8000 5800 8450 5800
|
||||
Wire Wire Line
|
||||
8000 5900 8450 5900
|
||||
Wire Wire Line
|
||||
8600 1600 8000 1600
|
||||
Wire Wire Line
|
||||
8600 1700 8000 1700
|
||||
Wire Wire Line
|
||||
8600 2400 8000 2400
|
||||
Wire Wire Line
|
||||
8600 2500 8000 2500
|
||||
Wire Wire Line
|
||||
8600 3200 8000 3200
|
||||
Wire Wire Line
|
||||
8600 3300 8000 3300
|
||||
Wire Wire Line
|
||||
8600 4400 8000 4400
|
||||
Wire Wire Line
|
||||
8600 4500 8000 4500
|
||||
Wire Wire Line
|
||||
8600 4600 8000 4600
|
||||
Wire Wire Line
|
||||
8600 5200 8000 5200
|
||||
Wire Wire Line
|
||||
8600 5300 8000 5300
|
||||
Wire Wire Line
|
||||
8600 6000 8000 6000
|
||||
Wire Wire Line
|
||||
8600 6100 8000 6100
|
||||
Text Label 2100 1100 0 60 ~ 0
|
||||
DPC0
|
||||
Text Label 2100 1200 0 60 ~ 0
|
||||
DPC1
|
||||
Text Label 2100 1300 0 60 ~ 0
|
||||
DPC2
|
||||
Text Label 2100 1400 0 60 ~ 0
|
||||
DPC3
|
||||
Text Label 2100 1500 0 60 ~ 0
|
||||
DPC4
|
||||
Text Label 2100 1600 0 60 ~ 0
|
||||
DPC5
|
||||
Text Label 2100 1700 0 60 ~ 0
|
||||
DPC6
|
||||
Text Label 2100 1800 0 60 ~ 0
|
||||
DPC7
|
||||
Text Label 2100 2300 0 60 ~ 0
|
||||
DPC8
|
||||
Text Label 2100 2400 0 60 ~ 0
|
||||
DPC9
|
||||
Text Label 2100 2500 0 60 ~ 0
|
||||
DPC10
|
||||
Text Label 2100 2600 0 60 ~ 0
|
||||
DPC11
|
||||
Text Label 2100 2700 0 60 ~ 0
|
||||
DPC12
|
||||
Text Label 2100 2800 0 60 ~ 0
|
||||
DPC13
|
||||
Text Label 2100 2900 0 60 ~ 0
|
||||
DPC14
|
||||
Text Label 2100 3000 0 60 ~ 0
|
||||
DPC15
|
||||
Text Label 2100 3500 0 60 ~ 0
|
||||
DPC16
|
||||
Text Label 2100 3600 0 60 ~ 0
|
||||
DPC17
|
||||
Text Label 2100 3700 0 60 ~ 0
|
||||
DPC18
|
||||
Text Label 2100 3800 0 60 ~ 0
|
||||
DPC19
|
||||
Text Label 2100 3900 0 60 ~ 0
|
||||
DPC20
|
||||
Text Label 2100 4000 0 60 ~ 0
|
||||
DPC21
|
||||
Text Label 2100 4100 0 60 ~ 0
|
||||
DPC22
|
||||
Text Label 2100 4200 0 60 ~ 0
|
||||
DPC23
|
||||
Text Label 2100 4700 0 60 ~ 0
|
||||
DPC24
|
||||
Text Label 2100 4800 0 60 ~ 0
|
||||
DPC25
|
||||
Text Label 2100 4900 0 60 ~ 0
|
||||
DPC26
|
||||
Text Label 2100 5000 0 60 ~ 0
|
||||
DPC27
|
||||
Text Label 2100 5100 0 60 ~ 0
|
||||
DPC28
|
||||
Text Label 2100 5200 0 60 ~ 0
|
||||
DPC29
|
||||
Text Label 2100 5300 0 60 ~ 0
|
||||
DPC30
|
||||
Text Label 2100 5400 0 60 ~ 0
|
||||
DPC31
|
||||
Text Label 4100 1100 0 60 ~ 0
|
||||
VRAM0
|
||||
Text Label 4100 1200 0 60 ~ 0
|
||||
VRAM1
|
||||
Text Label 4100 1300 0 60 ~ 0
|
||||
VRAM2
|
||||
Text Label 4100 1400 0 60 ~ 0
|
||||
VRAM3
|
||||
Text Label 4100 1500 0 60 ~ 0
|
||||
VRAM4
|
||||
Text Label 4100 1600 0 60 ~ 0
|
||||
VRAM5
|
||||
Text Label 4100 1700 0 60 ~ 0
|
||||
VRAM6
|
||||
Text Label 4100 1800 0 60 ~ 0
|
||||
VRAM7
|
||||
Text Label 4100 2300 0 60 ~ 0
|
||||
VRAM8
|
||||
Text Label 4100 2400 0 60 ~ 0
|
||||
VRAM9
|
||||
Text Label 4100 2500 0 60 ~ 0
|
||||
VRAM10
|
||||
Text Label 4100 2600 0 60 ~ 0
|
||||
VRAM11
|
||||
Text Label 4100 2700 0 60 ~ 0
|
||||
VRAM12
|
||||
Text Label 4100 2800 0 60 ~ 0
|
||||
VRAM13
|
||||
Text Label 4100 2900 0 60 ~ 0
|
||||
VRAM14
|
||||
Text Label 4100 3000 0 60 ~ 0
|
||||
VRAM15
|
||||
Text Label 4100 3500 0 60 ~ 0
|
||||
VRAM16
|
||||
Text Label 4100 3600 0 60 ~ 0
|
||||
VRAM17
|
||||
Text Label 4100 3700 0 60 ~ 0
|
||||
VRAM18
|
||||
Text Label 4100 3800 0 60 ~ 0
|
||||
VRAM19
|
||||
Text Label 4100 3900 0 60 ~ 0
|
||||
VRAM20
|
||||
Text Label 4100 4000 0 60 ~ 0
|
||||
VRAM21
|
||||
Text Label 4100 4100 0 60 ~ 0
|
||||
VRAM22
|
||||
Text Label 4100 4200 0 60 ~ 0
|
||||
VRAM23
|
||||
Text Label 4100 4700 0 60 ~ 0
|
||||
VRAM24
|
||||
Text Label 4100 4800 0 60 ~ 0
|
||||
VRAM25
|
||||
Text Label 4100 4900 0 60 ~ 0
|
||||
VRAM26
|
||||
Text Label 4100 5000 0 60 ~ 0
|
||||
VRAM27
|
||||
Text Label 4100 5100 0 60 ~ 0
|
||||
VRAM28
|
||||
Text Label 4100 5200 0 60 ~ 0
|
||||
VRAM29
|
||||
Text Label 4100 5300 0 60 ~ 0
|
||||
VRAM30
|
||||
Text Label 4100 5400 0 60 ~ 0
|
||||
VRAM31
|
||||
Text Label 5350 4500 0 60 ~ 0
|
||||
ACCES_RAM-
|
||||
Text Label 5650 5200 0 60 ~ 0
|
||||
VRAM6
|
||||
Text Label 5650 5300 0 60 ~ 0
|
||||
VRAM7
|
||||
Text Label 5700 2500 0 60 ~ 0
|
||||
VRAM4
|
||||
Text Label 5700 4100 0 60 ~ 0
|
||||
VRAM0
|
||||
Text Label 5700 4200 0 60 ~ 0
|
||||
VRAM3
|
||||
Text Label 5700 4300 0 60 ~ 0
|
||||
VRAM1
|
||||
Text Label 5700 4400 0 60 ~ 0
|
||||
VRAM2
|
||||
Text Label 5700 5000 0 60 ~ 0
|
||||
VRAM5
|
||||
Text Label 5700 5400 0 60 ~ 0
|
||||
VRAM8
|
||||
Text Label 5700 5500 0 60 ~ 0
|
||||
VRAM9
|
||||
Text Label 5700 5600 0 60 ~ 0
|
||||
VRAM10
|
||||
Text Label 5700 5700 0 60 ~ 0
|
||||
VRAM11
|
||||
Text Label 5700 5900 0 60 ~ 0
|
||||
VRAM12
|
||||
Text Label 5700 6000 0 60 ~ 0
|
||||
VRAM13
|
||||
Text Label 8050 4700 0 60 ~ 0
|
||||
VRAM28
|
||||
Text Label 8050 4800 0 60 ~ 0
|
||||
VRAM27
|
||||
Text Label 8050 4900 0 60 ~ 0
|
||||
VRAM26
|
||||
Text Label 8050 5000 0 60 ~ 0
|
||||
VRAM25
|
||||
Text Label 8050 5100 0 60 ~ 0
|
||||
VRAM24
|
||||
Text Label 8050 5400 0 60 ~ 0
|
||||
VRAM21
|
||||
Text Label 8050 5500 0 60 ~ 0
|
||||
VRAM20
|
||||
Text Label 8050 5600 0 60 ~ 0
|
||||
VRAM19
|
||||
Text Label 8050 5700 0 60 ~ 0
|
||||
VRAM18
|
||||
Text Label 8050 5800 0 60 ~ 0
|
||||
VRAM17
|
||||
Text Label 8050 5900 0 60 ~ 0
|
||||
VRAM16
|
||||
Text Label 8100 1800 0 60 ~ 0
|
||||
TVB5
|
||||
Text Label 8100 1900 0 60 ~ 0
|
||||
TVB4
|
||||
Text Label 8100 2000 0 60 ~ 0
|
||||
TVB3
|
||||
Text Label 8100 2100 0 60 ~ 0
|
||||
TVB2
|
||||
Text Label 8100 2200 0 60 ~ 0
|
||||
TVB1
|
||||
Text Label 8100 2300 0 60 ~ 0
|
||||
TVB0
|
||||
Text Label 8100 2600 0 60 ~ 0
|
||||
TVR5
|
||||
Text Label 8100 2700 0 60 ~ 0
|
||||
TVR4
|
||||
Text Label 8100 2800 0 60 ~ 0
|
||||
TVR3
|
||||
Text Label 8100 2900 0 60 ~ 0
|
||||
TVR2
|
||||
Text Label 8100 3000 0 60 ~ 0
|
||||
TVR1
|
||||
Text Label 8100 3100 0 60 ~ 0
|
||||
TVR0
|
||||
Text Label 8100 3500 0 60 ~ 0
|
||||
TVG5
|
||||
Text Label 8100 3700 0 60 ~ 0
|
||||
TVG4
|
||||
Text Label 8100 3800 0 60 ~ 0
|
||||
TVG3
|
||||
Text Label 8100 3900 0 60 ~ 0
|
||||
TVG2
|
||||
Text Label 8100 4000 0 60 ~ 0
|
||||
TVG1
|
||||
Text Label 8100 4100 0 60 ~ 0
|
||||
TVG0
|
||||
Text Label 8100 4400 0 60 ~ 0
|
||||
VRAM31
|
||||
Text Label 8100 5200 0 60 ~ 0
|
||||
VRAM23
|
||||
Text Label 8100 6000 0 60 ~ 0
|
||||
VRAM15
|
||||
Text Label 8150 1600 0 60 ~ 0
|
||||
TVB7
|
||||
Text Label 8150 1700 0 60 ~ 0
|
||||
TVB6
|
||||
Text Label 8150 2400 0 60 ~ 0
|
||||
TVR7
|
||||
Text Label 8150 2500 0 60 ~ 0
|
||||
TVR6
|
||||
Text Label 8150 3200 0 60 ~ 0
|
||||
TVG7
|
||||
Text Label 8150 3300 0 60 ~ 0
|
||||
TVG6
|
||||
Text Label 8150 4500 0 60 ~ 0
|
||||
VRAM30
|
||||
Text Label 8150 4600 0 60 ~ 0
|
||||
VRAM29
|
||||
Text Label 8150 5300 0 60 ~ 0
|
||||
VRAM22
|
||||
Text Label 8150 6100 0 60 ~ 0
|
||||
VRAM14
|
||||
Text HLabel 2350 900 0 60 BiDi ~ 0
|
||||
DPC[0..31]
|
||||
Text HLabel 2400 5600 0 60 Input ~ 0
|
||||
DATA_WR
|
||||
Text HLabel 2400 5700 0 60 Input ~ 0
|
||||
ACCES_RAM-
|
||||
Text HLabel 5600 2400 0 60 Input ~ 0
|
||||
X_CLK
|
||||
Text HLabel 6100 2000 0 60 Input ~ 0
|
||||
X_PROG-
|
||||
Text HLabel 6100 2100 0 60 Output ~ 0
|
||||
X_DONE
|
||||
Text HLabel 6100 2200 0 60 Input ~ 0
|
||||
X_DIN
|
||||
Text HLabel 6100 2700 0 60 Input ~ 0
|
||||
CLKCAD
|
||||
Text HLabel 6100 3200 0 60 Input ~ 0
|
||||
CLAMP
|
||||
Text HLabel 6100 3300 0 60 Input ~ 0
|
||||
BLANK-
|
||||
Text HLabel 6100 3400 0 60 Input ~ 0
|
||||
CSYNC-OUT
|
||||
Text HLabel 6100 3700 0 60 Input ~ 0
|
||||
ACQ_ON
|
||||
Text HLabel 8500 3400 2 60 Input ~ 0
|
||||
CLKCDA
|
||||
Text HLabel 9500 1000 2 60 BiDi ~ 0
|
||||
VRAM[0..31]
|
||||
Text HLabel 9500 1100 2 60 BiDi ~ 0
|
||||
TVR[0..7]
|
||||
Text HLabel 9500 1200 2 60 BiDi ~ 0
|
||||
TVG[0..7]
|
||||
Text HLabel 9500 1300 2 60 BiDi ~ 0
|
||||
TVB[0..7]
|
||||
$Comp
|
||||
L video_schlib:VCC #PWR06
|
||||
U 1 1 33A567E7
|
||||
P 6100 1550
|
||||
F 0 "#PWR06" H 6100 1750 40 0001 C CNN
|
||||
F 1 "VCC" H 6100 1700 40 0000 C CNN
|
||||
F 2 "" H 6100 1550 60 0001 C CNN
|
||||
F 3 "" H 6100 1550 60 0001 C CNN
|
||||
1 6100 1550
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L video_schlib:74LS245 U3
|
||||
U 1 1 33A7E303
|
||||
P 3300 1600
|
||||
F 0 "U3" H 3300 1400 60 0000 C CNN
|
||||
F 1 "74LS245" H 3300 1300 60 0000 C CNN
|
||||
F 2 "Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm" H 3300 1600 60 0001 C CNN
|
||||
F 3 "" H 3300 1600 60 0001 C CNN
|
||||
1 3300 1600
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L video_schlib:74LS245 U4
|
||||
U 1 1 4BF036D7
|
||||
P 3300 2800
|
||||
F 0 "U4" H 3300 2600 60 0000 C CNN
|
||||
F 1 "74LS245" H 3300 2500 60 0000 C CNN
|
||||
F 2 "Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm" H 3300 2800 60 0001 C CNN
|
||||
F 3 "" H 3300 2800 60 0001 C CNN
|
||||
1 3300 2800
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L video_schlib:74LS245 U5
|
||||
U 1 1 4BF036D6
|
||||
P 3300 4000
|
||||
F 0 "U5" H 3300 3800 60 0000 C CNN
|
||||
F 1 "74LS245" H 3300 3700 60 0000 C CNN
|
||||
F 2 "Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm" H 3300 4000 60 0001 C CNN
|
||||
F 3 "" H 3300 4000 60 0001 C CNN
|
||||
1 3300 4000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L video_schlib:74LS245 U6
|
||||
U 1 1 4BF036D5
|
||||
P 3300 5200
|
||||
F 0 "U6" H 3300 5000 60 0000 C CNN
|
||||
F 1 "74LS245" H 3300 4900 60 0000 C CNN
|
||||
F 2 "Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm" H 3300 5200 60 0001 C CNN
|
||||
F 3 "" H 3300 5200 60 0001 C CNN
|
||||
1 3300 5200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L video_schlib:XC4003-VQ100 U22
|
||||
U 1 1 33A567B8
|
||||
P 7050 3850
|
||||
F 0 "U22" H 7050 3950 70 0000 C CNN
|
||||
F 1 "XC4003-VQ100" H 7050 3750 70 0000 C CNN
|
||||
F 2 "Package_QFP:TQFP-100_14x14mm_P0.5mm" H 7050 3850 60 0001 C CNN
|
||||
F 3 "" H 7050 3850 60 0001 C CNN
|
||||
1 7050 3850
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$EndSCHEMATC
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,3 @@
|
|||
(sym_lib_table
|
||||
(lib (name video_schlib)(type Legacy)(uri ${KIPRJMOD}/libs/video_schlib.lib)(options "")(descr ""))
|
||||
)
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,283 @@
|
|||
update=15/04/2020 18:01:37
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=video.sch
|
||||
BoardNm=video.brd
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[cvpcb/libraries]
|
||||
EquName1=devcms
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_WriteFile=0
|
||||
ERC_TestSimilarLabels=1
|
||||
ERC_CheckUniqueGlobalLabels=1
|
||||
ERC_CheckBusDriverConflicts=1
|
||||
ERC_CheckBusEntryConflicts=1
|
||||
ERC_CheckBusToBusConflicts=1
|
||||
ERC_CheckBusToNetConflicts=1
|
||||
[sheetnames]
|
||||
1=00000000-0000-0000-0000-00005e977db2:
|
||||
2=00000000-0000-0000-0000-00004bf03681:pal-ntsc.sch
|
||||
3=00000000-0000-0000-0000-00004bf03689:ESVIDEO-RVB
|
||||
4=00000000-0000-0000-0000-00004bf03685:RAMS
|
||||
5=00000000-0000-0000-0000-00004bf0367f:modul
|
||||
6=00000000-0000-0000-0000-00004bf0367d:muxdata
|
||||
7=00000000-0000-0000-0000-00004bf03683:graphic
|
||||
8=00000000-0000-0000-0000-00004bf03687:buspci.sch
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=video.net
|
||||
LastSTEPExportPath=
|
||||
LastIDFExportPath=
|
||||
LastVRMLExportPath=
|
||||
LastSpecctraDSNExportPath=
|
||||
LastGenCADExportPath=
|
||||
CopperLayerCount=4
|
||||
BoardThickness=1.6002
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
MinTrackWidth=0.2
|
||||
MinViaDiameter=0.7999999999999999
|
||||
MinViaDrill=0.4
|
||||
MinMicroViaDiameter=0.508
|
||||
MinMicroViaDrill=0.127
|
||||
MinHoleToHole=0.25
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
CopperEdgeClearance=0.01
|
||||
TrackWidth1=0.2
|
||||
ViaDiameter1=0.889
|
||||
ViaDrill1=0.4
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.3048
|
||||
SilkTextSizeV=1.27
|
||||
SilkTextSizeH=1.27
|
||||
SilkTextSizeThickness=0.2032
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.3048
|
||||
CopperTextSizeV=1.524
|
||||
CopperTextSizeH=1.524
|
||||
CopperTextThickness=0.2032
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.2032
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.09999999999999999
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
DimensionUnits=0
|
||||
DimensionPrecision=1
|
||||
SolderMaskClearance=0.254
|
||||
SolderMaskMinWidth=0.25
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=top_copper
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=GND_layer
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=VCC_layer
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=bottom_copper
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.2
|
||||
TrackWidth=0.2
|
||||
ViaDiameter=0.889
|
||||
ViaDrill=0.4
|
||||
uViaDiameter=0.508
|
||||
uViaDrill=0.127
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
[pcbnew/Netclasses/1]
|
||||
Name=pwr
|
||||
Clearance=0.2
|
||||
TrackWidth=0.23
|
||||
ViaDiameter=0.889
|
||||
ViaDrill=0.4
|
||||
uViaDiameter=0.508
|
||||
uViaDrill=0.127
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -80,6 +80,7 @@ if __name__ == '__main__':
|
|||
parser = argparse.ArgumentParser(description='Compare KiCad netlists')
|
||||
parser.add_argument('first_netlist')
|
||||
parser.add_argument('second_netlist')
|
||||
parser.add_argument('--quiet', action='store_true')
|
||||
|
||||
args = parser.parse_args()
|
||||
|
||||
|
|
@ -97,12 +98,14 @@ if __name__ == '__main__':
|
|||
b = extract_nets(b)
|
||||
|
||||
if a is None:
|
||||
print("Could not read nets from {}".format(fn_a))
|
||||
sys.exit(1)
|
||||
if not args.quiet:
|
||||
print("Could not read nets from {}".format(fn_a))
|
||||
sys.exit(-1)
|
||||
|
||||
if b is None:
|
||||
print("Could not read nets from {}".format(fn_b))
|
||||
sys.exit(1)
|
||||
if not args.quiet:
|
||||
print("Could not read nets from {}".format(fn_b))
|
||||
sys.exit(-1)
|
||||
|
||||
nets_a = unpack(a)
|
||||
nets_b = unpack(b)
|
||||
|
|
@ -115,47 +118,51 @@ if __name__ == '__main__':
|
|||
both = sa & sb
|
||||
|
||||
if len(only_a) == len(only_b) == 0:
|
||||
print("{} and {} are identical".format(fn_a, fn_b))
|
||||
if not args.quiet:
|
||||
print("{} and {} are identical".format(fn_a, fn_b))
|
||||
sys.exit(0)
|
||||
|
||||
print("A: {}\nB: {}".format(fn_a, fn_b))
|
||||
if not args.quiet:
|
||||
print("A: {}\nB: {}".format(fn_a, fn_b))
|
||||
|
||||
changed_header = False
|
||||
changed_header = False
|
||||
|
||||
for net_name in sorted(both):
|
||||
if nets_a[net_name] != nets_b[net_name]:
|
||||
if not changed_header:
|
||||
print("\nChanged nets:\n")
|
||||
changed_header = True
|
||||
for net_name in sorted(both):
|
||||
if nets_a[net_name] != nets_b[net_name]:
|
||||
if not changed_header:
|
||||
print("\nChanged nets:\n")
|
||||
changed_header = True
|
||||
|
||||
print("{}: {} => {}".format(net_name, nets_a[net_name],
|
||||
nets_b[net_name]))
|
||||
print("{}: {} => {}".format(net_name, nets_a[net_name],
|
||||
nets_b[net_name]))
|
||||
|
||||
discards_a = set()
|
||||
discards_b = set()
|
||||
discards_a = set()
|
||||
discards_b = set()
|
||||
|
||||
renamed_header = False
|
||||
renamed_header = False
|
||||
|
||||
for net_name in sorted(only_a):
|
||||
for candidate in only_b:
|
||||
if nets_a[net_name] == nets_b[candidate]:
|
||||
if not renamed_header:
|
||||
print("\nRenamed nets (no connection changes):\n")
|
||||
renamed_header = True
|
||||
for net_name in sorted(only_a):
|
||||
for candidate in only_b:
|
||||
if nets_a[net_name] == nets_b[candidate]:
|
||||
if not renamed_header:
|
||||
print("\nRenamed nets (no connection changes):\n")
|
||||
renamed_header = True
|
||||
|
||||
print("{} => {}".format(net_name, candidate))
|
||||
discards_a.add(net_name)
|
||||
discards_b.add(candidate)
|
||||
print("{} => {}".format(net_name, candidate))
|
||||
discards_a.add(net_name)
|
||||
discards_b.add(candidate)
|
||||
|
||||
only_a.difference_update(discards_a)
|
||||
only_b.difference_update(discards_b)
|
||||
only_a.difference_update(discards_a)
|
||||
only_b.difference_update(discards_b)
|
||||
|
||||
if len(only_a) > 0:
|
||||
print("\nOnly in {}:\n".format(fn_a))
|
||||
print('\n'.join(["{}: {}".format(el, nets_a[el])
|
||||
for el in sorted(only_a)]))
|
||||
if len(only_a) > 0:
|
||||
print("\nOnly in {}:\n".format(fn_a))
|
||||
print('\n'.join(["{}: {}".format(el, nets_a[el])
|
||||
for el in sorted(only_a)]))
|
||||
|
||||
if len(only_b) > 0:
|
||||
print("\nOnly in {}:\n".format(fn_b))
|
||||
print('\n'.join(["{}: {}".format(el, nets_b[el])
|
||||
for el in sorted(only_b)]))
|
||||
if len(only_b) > 0:
|
||||
print("\nOnly in {}:\n".format(fn_b))
|
||||
print('\n'.join(["{}: {}".format(el, nets_b[el])
|
||||
for el in sorted(only_b)]))
|
||||
|
||||
sys.exit(1)
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
# This program source code file is part of KiCad, a free EDA CAD application.
|
||||
#
|
||||
# Copyright (C) 2020 Jon Evans <jon@craftyjon.com>
|
||||
# Copyright (C) 2020 KiCad Developers, see AUTHORS.txt for contributors.
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify it
|
||||
# under the terms of the GNU General Public License as published by the
|
||||
# Free Software Foundation, either version 3 of the License, or (at your
|
||||
# option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful, but
|
||||
# WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
# General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License along
|
||||
# with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
|
||||
import argparse
|
||||
import os
|
||||
import subprocess
|
||||
import sys
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
|
||||
parser = argparse.ArgumentParser(description='Tests eeschema netlist generation')
|
||||
parser.add_argument('--initialize', action='store_true',
|
||||
help='Generates the "good" reference netlists for each test case')
|
||||
parser.add_argument('binary_dir', default='.')
|
||||
|
||||
args = parser.parse_args()
|
||||
|
||||
eeschema = os.path.abspath(os.path.join(args.binary_dir, 'eeschema/eeschema'))
|
||||
|
||||
print('eeschema binary: {}'.format(eeschema))
|
||||
|
||||
# The way we discover testcases is simple:
|
||||
#
|
||||
# The root directory is hardcoded as ./data/netlists
|
||||
# Inside that are testcases in folders.
|
||||
#
|
||||
# Each testcase must have the root sheet named the same as the folder, for example:
|
||||
# ./data/netlists/video/video.sch
|
||||
#
|
||||
# The good netlist will be stored as ./data/netlists/video/video.net
|
||||
# The test netlist will be generated as ./data/netlists/video/video_test.net
|
||||
|
||||
data_dir = os.path.join(os.getcwd(), 'data/netlists')
|
||||
|
||||
with os.scandir(data_dir) as it:
|
||||
for entry in it:
|
||||
if entry.is_dir():
|
||||
|
||||
project = entry.name
|
||||
project_dir = os.path.join(data_dir, project)
|
||||
|
||||
sch_file = os.path.join(project_dir, project + '.sch')
|
||||
good_net_file = os.path.join(project_dir, project + '.net')
|
||||
|
||||
net_file = good_net_file if args.initialize else os.path.join(
|
||||
project_dir, project + '_test.net')
|
||||
|
||||
if not os.path.exists(good_net_file) and not args.initialize:
|
||||
print("FAILED: {} missing good netlist file for comparison".format(project))
|
||||
sys.exit(-1)
|
||||
|
||||
subprocess.run([eeschema, '--netlist', net_file, sch_file], cwd=project_dir)
|
||||
|
||||
result = subprocess.run(['./netdiff.py', good_net_file, net_file],
|
||||
stdout=subprocess.PIPE)
|
||||
|
||||
if not args.initialize:
|
||||
os.remove(net_file)
|
||||
|
||||
if result.returncode != 0:
|
||||
print("FAILED: {} netlist does not match:".format(project))
|
||||
print(result.stdout)
|
||||
|
||||
sys.exit(result.returncode)
|
||||
|
||||
sys.exit(0)
|
||||
Loading…
Reference in New Issue