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DRC library parity attribute tests: disable DNP and EXCLUDE from BOM. 

They are related to a design, not to a footprint, and are tested in
schematic parity tests.
This commit is contained in:
jean-pierre charras 2024-02-12 10:55:56 +01:00
parent 2afe4db945
commit 7e4e80a2e5
1 changed files with 8 additions and 0 deletions
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8
pcbnew/drc/drc_test_provider_library_parity.cpp
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@ -561,17 +561,25 @@ bool FOOTPRINT::FootprintNeedsUpdate( const FOOTPRINT* aLibFP, REPORTER* aReport
wxString::Format( _( "'%s' settings differ." ),
_( "Exclude from position files" ) ) );
// this test is skipped: EXCLUDE_FROM_BOM attribute is related to a given design,
// not to a lib footprint. EXCLUDE_FROM_BOM must be tested only in Schematic Parity
#if 0
TEST_ATTR( GetAttributes(), aLibFP->GetAttributes(), FP_EXCLUDE_FROM_BOM,
wxString::Format( _( "'%s' settings differ." ),
_( "Exclude from bill of materials" ) ) );
#endif
TEST_ATTR( GetAttributes(), aLibFP->GetAttributes(), FP_ALLOW_MISSING_COURTYARD,
wxString::Format( _( "'%s' settings differ." ),
_( "Exempt From Courtyard Requirement" ) ) );
// this test is skipped: Do No Place attribute is related to a given design,
// not to a lib footprint. DNP must be tested only in Schematic Parity
#if 0
TEST_ATTR( GetAttributes(), aLibFP->GetAttributes(), FP_DNP,
wxString::Format( _( "'%s' settings differ." ),
_( "Do not populate" ) ) );
#endif
// Clearance and zone connection overrides are as likely to be set at the board level as in