Sim: Fix writing inferred model for tlines

This commit is contained in:
Mikolaj Wielgus 2022-10-25 07:49:09 +02:00
parent b058ef2d87
commit 80c426f577
2 changed files with 3 additions and 7 deletions

View File

@ -70,9 +70,7 @@ std::string SPICE_GENERATOR_TLINE::ModelLine( const SPICE_ITEM& aItem ) const
SIM_MODEL_TLINE::SIM_MODEL_TLINE( TYPE aType ) :
SIM_MODEL( aType,
std::make_unique<SPICE_GENERATOR_TLINE>( *this ) ),
m_isInferred( false )
SIM_MODEL( aType, std::make_unique<SPICE_GENERATOR_TLINE>( *this ) )
{
static std::vector<PARAM::INFO> z0 = makeZ0ParamInfos();
static std::vector<PARAM::INFO> rlgc = makeRlgcParamInfos();
@ -100,7 +98,7 @@ void SIM_MODEL_TLINE::WriteDataSchFields( std::vector<SCH_FIELD>& aFields ) cons
{
SIM_MODEL::WriteDataSchFields( aFields );
if( m_isInferred )
if( IsInferred() )
inferredWriteDataFields( aFields );
}
@ -109,7 +107,7 @@ void SIM_MODEL_TLINE::WriteDataLibFields( std::vector<LIB_FIELD>& aFields ) cons
{
SIM_MODEL::WriteDataLibFields( aFields );
if( m_isInferred )
if( IsInferred() )
inferredWriteDataFields( aFields );
}

View File

@ -54,8 +54,6 @@ private:
static std::vector<PARAM::INFO> makeZ0ParamInfos();
static std::vector<PARAM::INFO> makeRlgcParamInfos();
bool m_isInferred;
};
#endif // SIM_MODEL_TLINE_H