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Pcbnew: fix bug in export vrml (bad Z position of 3D shapes). Very minor code cleaning.

This commit is contained in:
jean-pierre charras 2013-03-08 08:29:30 +01:00
parent 2ab86e7400
commit 8306f4c65c
6 changed files with 17 additions and 10 deletions
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4
common/build_version.cpp
View File

@ -7,9 +7,9 @@
#ifndef KICAD_BUILD_VERSION #ifndef KICAD_BUILD_VERSION
#if defined KICAD_GOST #if defined KICAD_GOST
# define KICAD_BUILD_VERSION "(2013-mar-04 GOST)" # define KICAD_BUILD_VERSION "(2013-mar-08 GOST)"
#else #else
# define KICAD_BUILD_VERSION "(2013-mar-04)" # define KICAD_BUILD_VERSION "(2013-mar-08)"
#endif #endif
#endif #endif

9
include/wxPcbStruct.h
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@ -1544,7 +1544,14 @@ public:
*/ */
void Show_1_Ratsnest( EDA_ITEM* item, wxDC* DC ); void Show_1_Ratsnest( EDA_ITEM* item, wxDC* DC );
void Clean_Pcb( wxDC* DC ); /**
* Function Clean_Pcb
* Clean up the board (remove redundant vias, not connected tracks
* and merges collinear track segments)
* Install the cleanup dialog frame to know what should be cleaned
* and run the cleanup function
*/
void Clean_Pcb();
void InstallFindFrame(); void InstallFindFrame();

4
packaging/windows/nsis/install.nsi
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@ -17,7 +17,7 @@
; General Product Description Definitions ; General Product Description Definitions
!define PRODUCT_NAME "KiCad" !define PRODUCT_NAME "KiCad"
!define PRODUCT_VERSION "2013.03.06" !define PRODUCT_VERSION "2013.03.08"
!define PRODUCT_WEB_SITE "http://iut-tice.ujf-grenoble.fr/kicad/" !define PRODUCT_WEB_SITE "http://iut-tice.ujf-grenoble.fr/kicad/"
!define SOURCEFORGE_WEB_SITE "http://kicad.sourceforge.net/" !define SOURCEFORGE_WEB_SITE "http://kicad.sourceforge.net/"
!define COMPANY_NAME "" !define COMPANY_NAME ""
@ -36,7 +36,7 @@ SetCompressor /final /solid lzma
CRCCheck force CRCCheck force
XPStyle on XPStyle on
Name "${PRODUCT_NAME} ${PRODUCT_VERSION}" Name "${PRODUCT_NAME} ${PRODUCT_VERSION}"
OutFile "${PRODUCT_NAME}_stable-${PRODUCT_VERSION}-BZR3986_Win_full_version.exe" OutFile "${PRODUCT_NAME}_stable-${PRODUCT_VERSION}-BZR3989_Win_full_version.exe"
InstallDir "$PROGRAMFILES\KiCad" InstallDir "$PROGRAMFILES\KiCad"
ShowInstDetails hide ShowInstDetails hide
ShowUnInstDetails hide ShowUnInstDetails hide

4
pcbnew/clean.cpp
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@ -106,9 +106,9 @@ private:
TRACK* aCandidate, int aEndType ); TRACK* aCandidate, int aEndType );
}; };
/* Install the track operation dialog frame /* Install the cleanup dialog frame to know what should be cleaned
*/ */
void PCB_EDIT_FRAME::Clean_Pcb( wxDC* DC ) void PCB_EDIT_FRAME::Clean_Pcb()
{ {
DIALOG_CLEANING_OPTIONS dlg( this ); DIALOG_CLEANING_OPTIONS dlg( this );

2
pcbnew/edit.cpp
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@ -1120,7 +1120,7 @@ void PCB_EDIT_FRAME::Process_Special_Functions( wxCommandEvent& event )
break; break;
case ID_MENU_PCB_CLEAN: case ID_MENU_PCB_CLEAN:
Clean_Pcb( &dc ); Clean_Pcb();
break; break;
case ID_MENU_PCB_SWAP_LAYERS: case ID_MENU_PCB_SWAP_LAYERS:

4
pcbnew/export_vrml.cpp
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@ -347,7 +347,7 @@ static void compute_layer_Zs( BOARD* pcb ) //{{{
/* To avoid rounding interference, we apply an epsilon to each /* To avoid rounding interference, we apply an epsilon to each
* successive layer */ * successive layer */
const double epsilon_z = 1 * IU_PER_MILS; // That's 1 mils, about 1/50 mm const double epsilon_z = 0.02 * IU_PER_MM; // That's 1/50 mm
layer_z[SOLDERPASTE_N_BACK] = -half_thickness - epsilon_z * 4; layer_z[SOLDERPASTE_N_BACK] = -half_thickness - epsilon_z * 4;
layer_z[ADHESIVE_N_BACK] = -half_thickness - epsilon_z * 3; layer_z[ADHESIVE_N_BACK] = -half_thickness - epsilon_z * 3;
layer_z[SILKSCREEN_N_BACK] = -half_thickness - epsilon_z * 2; layer_z[SILKSCREEN_N_BACK] = -half_thickness - epsilon_z * 2;
@ -1127,7 +1127,7 @@ static void export_vrml_module( BOARD* aPcb, MODULE* aModule,
fprintf( aOutputFile, " translation %g %g %g\n", fprintf( aOutputFile, " translation %g %g %g\n",
(offsetx + aModule->m_Pos.x) * boardIU2WRML, (offsetx + aModule->m_Pos.x) * boardIU2WRML,
- (offsety + aModule->m_Pos.y) * boardIU2WRML, // Y axis is reversed in Pcbnew - (offsety + aModule->m_Pos.y) * boardIU2WRML, // Y axis is reversed in Pcbnew
offsetz + layer_z[aModule->GetLayer()] * boardIU2WRML); (offsetz + layer_z[aModule->GetLayer()]) * boardIU2WRML);
fprintf( aOutputFile, " scale %g %g %g\n", fprintf( aOutputFile, " scale %g %g %g\n",
vrmlm->m_MatScale.x * aVRMLModelsToBiu, vrmlm->m_MatScale.x * aVRMLModelsToBiu,