fixed libedit regression
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commit
84ce064e3b
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@ -1005,7 +1005,9 @@ void LIB_COMPONENT::SetFields( const std::vector <LIB_FIELD>& aFields )
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drawings.push_back( field );
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}
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drawings.sort(); // would be nice to know why...
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// Reorder drawings: transparent polygons first, pins and text last.
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// so texts have priority on sreen.
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drawings.sort();
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}
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@ -263,6 +263,9 @@ An alias %s already exists!\nCannot update this component" ),
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// copy all the fields back, fully replacing any previous fields
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m_LibEntry->SetFields( m_FieldsBuf );
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// We need to keep the name and the value the same at the moment!
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SetName(m_LibEntry->GetValueField().m_Text);
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m_Parent->OnModify( );
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EndModal( 0 );
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@ -19,20 +19,21 @@
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<xsl:text>.HEA&nl;</xsl:text>
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<xsl:apply-templates select="design/date"/> <!-- Generate line .TIM <time> -->
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<xsl:apply-templates select="design/tool"/> <!-- Generate line .APP <eeschema version> -->
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<xsl:text>&nl;</xsl:text>
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<xsl:apply-templates select="components/comp"/> <!-- Generate list of components -->
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<xsl:text>&nl;&nl;</xsl:text>
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<xsl:apply-templates select="nets/net"/> <!-- Generate list of nets and connections -->
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<xsl:text>&nl;.END&nl;</xsl:text>
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</xsl:template>
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<!-- Generate line .TIM 20/08/2010 10:45:33 -->
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<!-- Generate line .APP "eeschema (2010-08-17 BZR 2450)-unstable" -->
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<xsl:template match="tool">
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<xsl:text>.APP "</xsl:text>
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<xsl:apply-templates/>
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<xsl:text>"&nl;</xsl:text>
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</xsl:template>
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<!-- Generate line .APP "eeschema (2010-08-17 BZR 2450)-unstable" -->
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<!-- Generate line .TIM 20/08/2010 10:45:33 -->
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<xsl:template match="date">
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<xsl:text>.TIM </xsl:text>
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<xsl:apply-templates/>
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@ -40,6 +41,10 @@
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</xsl:template>
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<!-- for each component -->
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<!-- create lines like
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.ADD_COM U3 "74LS541" (when no footprint name specified)
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.ADD_COM JP1 "CONN_8X2" "pin_array_8x2" "pin_array_8x2" (with a specified footprint name)
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-->
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<xsl:template match="comp">
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<xsl:text>.ADD_COM </xsl:text>
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<xsl:value-of select="@ref"/>
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@ -56,6 +61,13 @@
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</xsl:template>
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<!-- for each net -->
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<!-- create lines like
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.ADD_TER U3.9 "/PC-RST"
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.TER U3.8
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BUS1.2
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.ADD_TER BUS1.14 "/PC-IOR"
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.TER U3.7
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-->
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<xsl:template match="net">
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<!-- nets are output only if there is more than one pin in net -->
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<xsl:if test="count(node)>1">
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