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Add regression test and example rule. 

Fixes https://gitlab.com/kicad/code/kicad/-/issues/18142
This commit is contained in:
Jeff Young 2024-06-04 10:58:16 +01:00
parent bc3ae8ca51
commit 855c972156
5 changed files with 1486 additions and 2 deletions
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9
pcbnew/dialogs/panel_setup_rules_help.md
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@ -298,12 +298,19 @@ For the latter use a `(layer "layer_name")` clause in the rule.
(rule "Plated through-hole size"
(constraint hole_size (min 0.2mm) (max 6.35mm))
(condition "A.isPlated() && A.Hole_Size_X == A.Hole_Size_Y"))
(rule "Plated slot size"
(constraint hole_size (min 0.5mm))
(condition "A.isPlated() && A.Hole_Size_X != A.Hole_Size_Y"))
# Allow blind/buried to micro-via hole-to-hole violations when it is known that
# the fab will mechanically drill blind/buried via holes -before- laser drilling
# micro-vias.
(rule hole_to_hole_uvia_exclusion
(condition "A.Via_Type == 'Blind/buried' && B.Via_Type == 'Micro'")
(constraint hole_to_hole)
(severity ignore))
### Documentation
For the full documentation see [https://docs.kicad.org](https://docs.kicad.org/GetMajorMinorVersion/en/pcbnew/pcbnew.html#custom_design_rules).

9
pcbnew/dialogs/panel_setup_rules_help_md.h
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@ -299,12 +299,19 @@ _HKI( "### Top-level Clauses\n"
" (rule \"Plated through-hole size\"\n"
" (constraint hole_size (min 0.2mm) (max 6.35mm))\n"
" (condition \"A.isPlated() && A.Hole_Size_X == A.Hole_Size_Y\"))\n"
"\n"
" (rule \"Plated slot size\"\n"
" (constraint hole_size (min 0.5mm))\n"
" (condition \"A.isPlated() && A.Hole_Size_X != A.Hole_Size_Y\"))\n"
"\n"
"\n"
" # Allow blind/buried to micro-via hole-to-hole violations when it is known that\n"
" # the fab will mechanically drill blind/buried via holes -before- laser drilling \n"
" # micro-vias.\n"
" (rule hole_to_hole_uvia_exclusion\n"
" (condition \"A.Via_Type == 'Blind/buried' && B.Via_Type == 'Micro'\")\n"
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad.org/GetMajorMinorVersion/en/pcbnew/pcbnew.html#custom_design_rules)." );

442
qa/data/pcbnew/issue18142.kicad_pcb Normal file
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@ -0,0 +1,442 @@
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(company "epyMetrics AG")
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(32 "B.Adhes" user "B.Adhesive")
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(34 "B.Paste" user)
(35 "F.Paste" user)
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(37 "F.SilkS" user "F.Silkscreen")
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(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
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(53 "User.4" user "Non-bending flex Area")
(54 "User.5" user "Impedance Control F")
(55 "User.6" user "Impedance Control B")
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(pad_to_mask_clearance 0)
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(pdf_front_fp_property_popups yes)
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(net 0 "")
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(gr_rect
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(via micro
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(size 0.225)
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(teardrops
(best_length_ratio 0.2)
(max_length 1)
(best_width_ratio 1)
(max_width 2)
(curve_points 0)
(filter_ratio 0.9)
(enabled yes)
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(net 1)
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(net 1)
(uuid "5022bf5b-2165-4254-bf12-9b859e53d93b")
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(segment
(start 154.375 90.35)
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(layer "In2.Cu")
(net 1)
(uuid "f01ae2d9-9cac-4701-9bc1-60686c429052")
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(size 0.3)
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(uuid "fe454a03-5137-4866-b063-1566ba7f2e98")
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(net_name "/core/FLASH_QSPI_IO3")
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(uuid "57fd00dd-207e-4e91-8811-c29c74d3bf3a")
(name "$teardrop_padvia$")
(hatch full 0.1)
(priority 30004)
(attr
(teardrop
(type padvia)
)
)
(connect_pads yes
(clearance 0)
)
(min_thickness 0.0254)
(filled_areas_thickness no)
(fill yes
(thermal_gap 0.5)
(thermal_bridge_width 0.5)
(island_removal_mode 1)
(island_area_min 10)
)
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(filled_polygon
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(island_removal_mode 1)
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(filled_areas_thickness no)
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1027
qa/data/pcbnew/issue18142.kicad_pro Normal file
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1
qa/tests/pcbnew/drc/test_drc_regressions.cpp
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@ -139,6 +139,7 @@ BOOST_FIXTURE_TEST_CASE( DRCFalseNegativeRegressions, DRC_REGRESSION_TEST_FIXTUR
{ "issue12109", 8 }, // Pads fail annular width test
{ "issue14334", 2 }, // Thermal spoke to otherwise unconnected island
{ "issue16566", 6 }, // Pad_Shape vs Shape property
{ "issue18142", 1 }, // blind/buried via to micro-via hole-to-hole
{ "reverse_via", 3 }, // Via/track ordering
{ "intersectingzones", 1 }, // zones are too close to each other
{ "fill_bad", 1 }, // zone max BBox was too small