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Fix typo

This commit is contained in:
Seth Hillbrand 2020-09-23 14:00:39 -07:00
parent b31eafdfa8
commit 856cf51fc8
3 changed files with 154 additions and 7 deletions
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2
pcbnew/connectivity/connectivity_algo.cpp
View File

@ -657,7 +657,7 @@ void CN_VISITOR::checkZoneZoneConnection( CN_ZONE_LAYER* aZoneLayerA, CN_ZONE_LA
const auto zoneA = static_cast<const ZONE_CONTAINER*>( aZoneLayerA->Parent() );
const auto zoneB = static_cast<const ZONE_CONTAINER*>( aZoneLayerB->Parent() );
if( aZoneA->Layer() != aZoneB->Layer() )
if( aZoneLayerA->Layer() != aZoneLayerB->Layer() )
return;
if( aZoneLayerB->Net() != aZoneLayerA->Net() )

1
qa/data/complex_hierarchy.kicad_prl
View File

@ -11,6 +11,7 @@
"vias": 1.0,
"zones": 1.0
},
"ratsnest_display_mode": 0,
"selection_filter": {
"dimensions": true,
"footprints": true,

158
qa/data/complex_hierarchy.kicad_pro
View File

@ -1,5 +1,127 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.2032,
"copper_line_width": 0.381,
"copper_text_italic": false,
"copper_text_size_h": 1.524,
"copper_text_size_v": 2.032,
"copper_text_thickness": 0.30479999999999996,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.8128,
"height": 2.286,
"width": 2.286
},
"silk_line_width": 0.381,
"silk_text_italic": false,
"silk_text_size_h": 1.524,
"silk_text_size_v": 1.524,
"silk_text_thickness": 0.30479999999999996,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.508
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 1
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"drill_too_small": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"keepout": "error",
"malformed_courtyard": "error",
"microvia_drill_too_small": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"via_hole_larger_than_pad": "error",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.01,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.508,
"min_microvia_drill": 0.2032,
"min_through_hole_diameter": 0.508,
"min_track_width": 0.2032,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.889,
"solder_mask_clearance": 0.254,
"solder_mask_min_width": 0.0,
"solder_paste_clearance": 0.0,
"solder_paste_margin_ratio": 0.0
},
"track_widths": [
0.25
],
"via_dimensions": [
{
"diameter": 0.8,
"drill": 0.4
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
@ -18,19 +140,43 @@
"classes": [
{
"bus_width": 12.0,
"clearance": 0.2,
"clearance": 0.2794,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"microvia_diameter": 0.508,
"microvia_drill": 0.2032,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"track_width": 0.4318,
"via_diameter": 1.651,
"via_drill": 0.635,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 0.381,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.508,
"microvia_drill": 0.2032,
"name": "power",
"nets": [
"-VAA",
"/12Vext",
"GND",
"HT",
"VCC"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.6096,
"via_diameter": 1.651,
"via_drill": 0.635,
"wire_width": 6.0
}
],