CADSTAR PCB: Ensure continuous track routes
When route offsetting, add an additional thin track to ensure end point of one track and start point of the next are at the same location. Fixes https://gitlab.com/kicad/code/kicad/-/issues/8131
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@ -2204,44 +2204,32 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadNetTracks( const NET_ID& aCadstarNe
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const NET_PCB::ROUTE& aCadstarRoute,
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long aStartWidth, long aEndWidth )
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{
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if( aCadstarRoute.RouteVertices.size() == 0 )
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return;
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std::vector<PCB_SHAPE*> shapes;
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std::vector<NET_PCB::ROUTE_VERTEX> routeVertices = aCadstarRoute.RouteVertices;
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std::vector<NET_PCB::ROUTE_VERTEX> offsetedVertices = aCadstarRoute.RouteVertices;
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POINT newStartPoint = aCadstarRoute.StartPoint;
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auto begin = offsetedVertices.begin();
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// First iterate through the points and apply route offset to start and end points only
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// the rest of route offseting will happen in makeTracksFromDrawsegments
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for( auto it = begin, end = offsetedVertices.end(); it != end; ++it )
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// Add thin route at front so that route offseting works as expected
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if( aStartWidth < routeVertices.front().RouteWidth )
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{
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auto next = std::next( it );
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if( it == offsetedVertices.begin() )
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{
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// second point of the route (first point is given by aCadstarRoute.StartPoint)
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int offsetAmount = ( it->RouteWidth / 2 ) - ( aStartWidth / 2 );
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if( aStartWidth < it->RouteWidth )
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applyRouteOffset( &newStartPoint, it->Vertex.End, offsetAmount );
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NET_PCB::ROUTE_VERTEX newFrontVertex = aCadstarRoute.RouteVertices.front();
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newFrontVertex.RouteWidth = aStartWidth;
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newFrontVertex.Vertex.End = aCadstarRoute.StartPoint;
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routeVertices.insert( routeVertices.begin(), newFrontVertex );
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}
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if( next == end )
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// Add thin route at the back if required
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if( aEndWidth < routeVertices.back().RouteWidth )
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{
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// last point of the route
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int offsetAmount = ( it->RouteWidth / 2 ) - ( aEndWidth / 2 );
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POINT referencePoint = newStartPoint;
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if( it != begin )
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referencePoint = std::prev( it )->Vertex.End;
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if( aEndWidth < it->RouteWidth )
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applyRouteOffset( &it->Vertex.End, referencePoint, offsetAmount );
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}
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NET_PCB::ROUTE_VERTEX newBackVertex = aCadstarRoute.RouteVertices.back();
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newBackVertex.RouteWidth = aEndWidth;
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routeVertices.push_back( newBackVertex );
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}
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POINT prevEnd = newStartPoint;
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POINT prevEnd = aCadstarRoute.StartPoint;
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for( const NET_PCB::ROUTE_VERTEX& v : offsetedVertices )
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for( const NET_PCB::ROUTE_VERTEX& v : routeVertices )
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{
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PCB_SHAPE* shape = getDrawSegmentFromVertex( prevEnd, v.Vertex );
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shape->SetLayer( getKiCadLayer( aCadstarRoute.LayerID ) );
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@ -2251,9 +2239,8 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadNetTracks( const NET_ID& aCadstarNe
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prevEnd = v.Vertex.End;
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}
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//Todo add real netcode to the tracks
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std::vector<TRACK*> tracks =
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makeTracksFromDrawsegments( shapes, m_board, getKiCadNet( aCadstarNetID ) );
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NETINFO_ITEM* net = getKiCadNet( aCadstarNetID );
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std::vector<TRACK*> tracks = makeTracksFromDrawsegments( shapes, m_board, net );
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//cleanup
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for( PCB_SHAPE* shape : shapes )
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@ -2856,11 +2843,28 @@ std::vector<TRACK*> CADSTAR_PCB_ARCHIVE_LOADER::makeTracksFromDrawsegments(
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{
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std::vector<TRACK*> tracks;
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TRACK* prevTrack = nullptr;
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TRACK* track = nullptr;
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auto addTrack = [&]( TRACK* aTrack )
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{
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// Ignore zero length tracks in the same way as the CADSTAR postprocessor
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// does when generating gerbers. Note that CADSTAR reports these as "Route
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// offset errors" when running a DRC within CADSTAR, so we shouldn't be
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// getting this in general, however it is used to remove any synthetic
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// points added to aDrawSegments by the caller of this function.
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if( aTrack->GetLength() != 0 )
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{
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tracks.push_back( aTrack );
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aParentContainer->Add( aTrack, ADD_MODE::APPEND );
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}
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else
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{
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delete aTrack;
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}
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};
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for( PCB_SHAPE* ds : aDrawsegments )
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{
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TRACK* track;
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switch( ds->GetShape() )
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{
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case S_ARC:
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@ -2933,13 +2937,33 @@ std::vector<TRACK*> CADSTAR_PCB_ARCHIVE_LOADER::makeTracksFromDrawsegments(
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applyRouteOffset( &newEnd, prevTrack->GetStart(), -offsetAmount );
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prevTrack->SetEnd( newEnd );
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} // don't do anything if offsetAmount == 0
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// Add a synthetic track of the thinnest width between the tracks
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// to ensure KiCad features works as expected on the imported design
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// (KiCad expects tracks are contigous segments)
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if( track->GetStart() != prevTrack->GetEnd() )
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{
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int minWidth = std::min( track->GetWidth(), prevTrack->GetWidth() );
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TRACK* synthTrack = new TRACK( aParentContainer );
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synthTrack->SetStart( prevTrack->GetEnd() );
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synthTrack->SetEnd( track->GetStart() );
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synthTrack->SetWidth( minWidth );
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synthTrack->SetLocked( track->IsLocked() );
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synthTrack->SetNet( track->GetNet() );
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synthTrack->SetLayer( track->GetLayer() );
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addTrack( synthTrack );
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}
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}
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if( prevTrack )
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addTrack( prevTrack );
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prevTrack = track;
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tracks.push_back( track );
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aParentContainer->Add( track, ADD_MODE::APPEND );
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}
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if( track )
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addTrack( track );
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return tracks;
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}
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