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Apply same nettie hack to zone filler 

The nettie hack is used in DRC but we also need to use it in zone filler
to allow zones to be used with netties.  We limit this to the
appropriate nets in the nettie

Fixes https://gitlab.com/kicad/code/kicad/issues/7351
This commit is contained in:
Seth Hillbrand 2021-01-31 16:15:24 -08:00
parent b17ba9d632
commit 8778599c0d
3 changed files with 26 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
pcbnew/zone_filler.cpp
View File

@ -817,9 +817,28 @@ void ZONE_FILLER::buildCopperItemClearances( const ZONE* aZone, PCB_LAYER_ID aLa
for( FOOTPRINT* footprint : m_board->Footprints() )
{
bool skipFootprint = false;
knockoutGraphicClearance( &footprint->Reference() );
knockoutGraphicClearance( &footprint->Value() );
// Don't knock out holes in zones that share a net
// with a nettie footprint
if( footprint->IsNetTie() )
{
for( PAD* pad : footprint->Pads() )
{
if( aZone->GetNetCode() == pad->GetNetCode() )
{
skipFootprint = true;
break;
}
}
}
if( skipFootprint )
continue;
for( BOARD_ITEM* item : footprint->GraphicalItems() )
{
if( checkForCancel( m_progressReporter ) )

5
qa/data/complex_hierarchy.kicad_prl
View File

@ -58,8 +58,9 @@
28,
29,
30,
37,
38
31,
39,
40
],
"visible_layers": "007ffff_ffffffff",
"zone_display_mode": 0

20
qa/data/complex_hierarchy.kicad_pro
View File

@ -48,15 +48,10 @@
"min_clearance": 0.508
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"filename": "board_design_settings.json",
"version": 1
},
"rule_severities": {
@ -117,15 +112,8 @@
"solder_paste_clearance": 0.0,
"solder_paste_margin_ratio": 0.0
},
"track_widths": [
0.25
],
"via_dimensions": [
{
"diameter": 0.8,
"drill": 0.4
}
],
"track_widths": [],
"via_dimensions": [],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},