drc_proto: initial version of legacy rule import (without overrides yet)
This commit is contained in:
Tomasz Wlostowski
parent
05b88acf16
commit
8a5297180e
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@ -123,19 +123,300 @@ bool test::DRC_ENGINE::LoadRules( wxFileName aPath )
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}
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test::DRC_TEST_PROVIDER *drcCreateClearanceTestProvider( test::DRC_ENGINE *engine );
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void test::DRC_ENGINE::inferImplicitRules()
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test::DRC_RULE* test::DRC_ENGINE::createInferredRule( const wxString& name, std::set<BOARD_ITEM*> items, int priority )
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{
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DRC_RULE *rule = new DRC_RULE;
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rule->SetName( name );
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if (! items.empty() )
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rule->FillSpecificItemSet( items );
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rule->SetPriority( priority );
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addRule( rule );
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return rule;
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}
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#if 0
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int BOARD_CONNECTED_ITEM::GetClearance( PCB_LAYER_ID aLayer, BOARD_ITEM* aItem,
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wxString* aSource ) const
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{
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BOARD* board = GetBoard();
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int clearance = 0;
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wxString source;
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wxString* localSource = aSource ? &source : nullptr;
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BOARD_CONNECTED_ITEM* second = dynamic_cast<BOARD_CONNECTED_ITEM*>( aItem );
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// No clearance if "this" is not (yet) linked to a board therefore no available netclass
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if( !board )
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return clearance;
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// LEVEL 1: local overrides (pad, footprint, etc.)
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//
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if( GetLocalClearanceOverrides() > clearance )
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clearance = GetLocalClearanceOverrides( localSource );
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if( second && second->GetLocalClearanceOverrides() > clearance )
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clearance = second->GetLocalClearanceOverrides( localSource );
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if( clearance )
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{
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if( aSource )
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*aSource = *localSource;
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return clearance;
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}
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// LEVEL 2: Rules
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//
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if( GetRuleClearance( aItem, aLayer, &clearance, aSource ) )
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return clearance;
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// LEVEL 3: Accumulated local settings, netclass settings, & board design settings
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//
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BOARD_DESIGN_SETTINGS& bds = board->GetDesignSettings();
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NETCLASS* netclass = GetEffectiveNetclass();
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NETCLASS* secondNetclass = second ? second->GetEffectiveNetclass() : nullptr;
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if( bds.m_MinClearance > clearance )
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{
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if( aSource )
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*aSource = _( "board minimum" );
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clearance = bds.m_MinClearance;
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}
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if( netclass && netclass->GetClearance() > clearance )
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clearance = netclass->GetClearance( aSource );
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if( secondNetclass && secondNetclass->GetClearance() > clearance )
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clearance = secondNetclass->GetClearance( aSource );
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if( aItem && aItem->GetLayer() == Edge_Cuts && bds.m_CopperEdgeClearance > clearance )
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{
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if( aSource )
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*aSource = _( "board edge" );
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clearance = bds.m_CopperEdgeClearance;
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}
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if( GetLocalClearance() > clearance )
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clearance = GetLocalClearance( aSource );
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if( second && second->GetLocalClearance() > clearance )
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clearance = second->GetLocalClearance( aSource );
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return clearance;
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}
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#endif
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void test::DRC_ENGINE::inferLegacyRules()
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{
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int priorityRangeMin = INT_MIN + 10000;
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int priorityRangeMax = INT_MAX - 10000;
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ReportAux( wxString::Format( "Inferring implicit rules (per-item/class overrides, etc...)" ) );
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// 1) global defaults
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test::DRC_RULE* rule = createInferredRule( "inferred-defaults", {}, priorityRangeMin );
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BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
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DRC_CONSTRAINT clearanceConstraint( test::DRC_CONSTRAINT_TYPE_T::DRC_CONSTRAINT_TYPE_CLEARANCE );
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clearanceConstraint.Value().SetMin( bds.m_MinClearance );
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rule->AddConstraint( clearanceConstraint );
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DRC_CONSTRAINT widthConstraint( test::DRC_CONSTRAINT_TYPE_T::DRC_CONSTRAINT_TYPE_TRACK_WIDTH );
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widthConstraint.Value().SetMin( bds.m_TrackMinWidth );
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rule->AddConstraint( widthConstraint );
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DRC_CONSTRAINT drillConstraint( test::DRC_CONSTRAINT_TYPE_T::DRC_CONSTRAINT_TYPE_HOLE_SIZE );
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drillConstraint.Value().SetMin( bds.m_MinThroughDrill );
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rule->AddConstraint( drillConstraint );
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DRC_CONSTRAINT annulusConstraint( test::DRC_CONSTRAINT_TYPE_T::DRC_CONSTRAINT_TYPE_ANNULUS_WIDTH );
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annulusConstraint.Value().SetMin( bds.m_ViasMinAnnulus );
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rule->AddConstraint( annulusConstraint );
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DRC_CONSTRAINT diameterConstraint( test::DRC_CONSTRAINT_TYPE_T::DRC_CONSTRAINT_TYPE_VIA_DIAMETER );
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diameterConstraint.Value().SetMin( bds.m_ViasMinSize );
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rule->AddConstraint( diameterConstraint );
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DRC_CONSTRAINT edgeClearanceConstraint( test::DRC_CONSTRAINT_TYPE_T::DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE );
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edgeClearanceConstraint.Value().SetMin( bds.m_CopperEdgeClearance );
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rule->AddConstraint( edgeClearanceConstraint );
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DRC_CONSTRAINT holeClearanceConstraint( test::DRC_CONSTRAINT_TYPE_T::DRC_CONSTRAINT_TYPE_HOLE_CLEARANCE );
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holeClearanceConstraint.Value().SetMin( bds.m_HoleToHoleMin );
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rule->AddConstraint( holeClearanceConstraint );
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// 2) micro-via specific defaults (new DRC doesn't treat microvias in any special way)
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priorityRangeMin++;
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auto isMicroViaCondition = new DRC_RULE_CONDITION ( "A.type == 'Via' && A.isMicroVia()" );
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test::DRC_RULE* uViaRule = createInferredRule( "inferred-microvia-defaults", {}, priorityRangeMin );
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uViaRule->SetCondition( isMicroViaCondition );
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DRC_CONSTRAINT uViaDrillConstraint( test::DRC_CONSTRAINT_TYPE_T::DRC_CONSTRAINT_TYPE_HOLE_SIZE );
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uViaDrillConstraint.Value().SetMin( bds.m_MicroViasMinDrill );
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uViaRule->AddConstraint( uViaDrillConstraint );
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DRC_CONSTRAINT uViaDiameterConstraint( test::DRC_CONSTRAINT_TYPE_T::DRC_CONSTRAINT_TYPE_VIA_DIAMETER );
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uViaDiameterConstraint.Value().SetMin( bds.m_MicroViasMinSize );
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uViaRule->AddConstraint( uViaDiameterConstraint );
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auto isBlindBuriedViaCondition = new DRC_RULE_CONDITION ( "A.type == 'Via' && A.isBlindBuriedVia()" );
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test::DRC_RULE* blindBuriedViaRule = createInferredRule( "inferred-blind-buried-via-defaults", {}, priorityRangeMin );
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DRC_CONSTRAINT disallowConstraint( test::DRC_CONSTRAINT_TYPE_T::DRC_CONSTRAINT_TYPE_DISALLOW );
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blindBuriedViaRule->SetCondition ( isBlindBuriedViaCondition );
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if( !bds.m_MicroViasAllowed )
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{
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uViaRule->AddConstraint( disallowConstraint );
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}
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if( !bds.m_BlindBuriedViaAllowed )
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{
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blindBuriedViaRule->AddConstraint( disallowConstraint );
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}
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// 3) per-netclass rules
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struct NETCLASS_ENTRY
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{
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wxString name;
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int clearance;
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int width;
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};
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std::vector<NETCLASS_ENTRY> netclassesByClearance, netclassesByWidth;
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for( auto netclass : bds.GetNetClasses() )
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{
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auto className = netclass.second->GetName();
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NETCLASS_ENTRY ent;
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ent.name = className;
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ent.clearance = netclass.second->GetClearance();
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ent.width = netclass.second->GetTrackWidth();
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netclassesByClearance.push_back( ent );
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netclassesByWidth.push_back( ent );
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}
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// create clearance rules
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std::sort( netclassesByClearance.begin(), netclassesByClearance.end(), [] ( const NETCLASS_ENTRY& a, const NETCLASS_ENTRY& b ) -> bool
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{
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return a.clearance < b.clearance;
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} );
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std::sort( netclassesByWidth.begin(), netclassesByWidth.end(), [] ( const NETCLASS_ENTRY& a, const NETCLASS_ENTRY& b ) -> bool
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{
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return a.width > b.width;
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} );
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for( int i = 0; i < netclassesByClearance.size(); i++ )
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{
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wxString className = netclassesByClearance[i].name;
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const auto expr = wxString::Format( "A.NetClass == '%s' || B.NetClass == '%s'", className, className );
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auto inNetclassCondition = new DRC_RULE_CONDITION ( expr );
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test::DRC_RULE* netclassRule = createInferredRule( wxString::Format( "inferred-netclass-clearance-%s", className ),
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{}, priorityRangeMin + i );
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netclassRule->SetCondition( inNetclassCondition );
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DRC_CONSTRAINT ncClearanceConstraint ( DRC_CONSTRAINT_TYPE_CLEARANCE );
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ncClearanceConstraint.Value().SetMin( netclassesByClearance[i].clearance );
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netclassRule->AddConstraint( ncClearanceConstraint );
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className = netclassesByWidth[i].name;
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netclassRule = createInferredRule( wxString::Format( "inferred-netclass-width-%s", className ),
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{}, priorityRangeMin + i );
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netclassRule->SetCondition( inNetclassCondition );
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DRC_CONSTRAINT ncWidthConstraint ( DRC_CONSTRAINT_TYPE_TRACK_WIDTH );
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ncWidthConstraint.Value().SetMin( netclassesByWidth[i].width );
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netclassRule->AddConstraint( ncWidthConstraint );
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// TODO: should we import diff pair gaps/widths here?
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}
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//clearanceConstraint.SetMin( )
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//rule->AddConstraint( )
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}
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static wxString formatConstraint( const test::DRC_CONSTRAINT& constraint )
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{
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struct Formatter
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{
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test::DRC_CONSTRAINT_TYPE_T type;
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wxString name;
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std::function<wxString(const test::DRC_CONSTRAINT&)> formatter;
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};
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auto formatMinMax = []( const test::DRC_CONSTRAINT& c ) -> wxString {
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wxString str;
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const auto value = c.GetValue();
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if ( value.HasMin() )
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str += wxString::Format(" min: %d", value.Min() );
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if ( value.HasOpt() )
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str += wxString::Format(" opt: %d", value.Opt() );
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if ( value.HasMax() )
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str += wxString::Format(" max: %d", value.Max() );
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return str;
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};
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std::vector<Formatter> formats = {
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{ test::DRC_CONSTRAINT_TYPE_UNKNOWN, "unknown", nullptr },
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{ test::DRC_CONSTRAINT_TYPE_CLEARANCE, "clearance", formatMinMax },
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{ test::DRC_CONSTRAINT_TYPE_HOLE_CLEARANCE, "hole_clearance", formatMinMax },
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{ test::DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE, "edge_clearance", formatMinMax },
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{ test::DRC_CONSTRAINT_TYPE_HOLE_SIZE, "hole_size", formatMinMax },
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{ test::DRC_CONSTRAINT_TYPE_COURTYARD_CLEARANCE, "courtyard_clearance", formatMinMax },
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{ test::DRC_CONSTRAINT_TYPE_SILK_TO_PAD, "silk_to_pad", formatMinMax },
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{ test::DRC_CONSTRAINT_TYPE_SILK_TO_SILK, "silk_to_silk", formatMinMax },
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{ test::DRC_CONSTRAINT_TYPE_TRACK_WIDTH, "track_width", formatMinMax },
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{ test::DRC_CONSTRAINT_TYPE_ANNULUS_WIDTH, "annulus_with", formatMinMax },
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{ test::DRC_CONSTRAINT_TYPE_DISALLOW, "disallow", nullptr }, // fixme
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{ test::DRC_CONSTRAINT_TYPE_VIA_DIAMETER, "via_diameter", formatMinMax }
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};
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for( auto& fmt : formats)
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{
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if( fmt.type == constraint.GetType() )
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{
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wxString rv = fmt.name + " ";
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if( fmt.formatter )
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rv += fmt.formatter( constraint );
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return rv;
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}
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}
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return "?";
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}
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bool test::DRC_ENGINE::CompileRules()
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{
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ReportAux( wxString::Format( "Compiling Rules (%d rules, %d conditions): ", m_rules.size(), m_ruleConditions.size() ) );
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ReportAux( wxString::Format( "Compiling Rules (%d rules, %d conditions): ", (int)m_rules.size(), (int)m_ruleConditions.size() ) );
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for( auto provider : m_testProviders )
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{
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@ -152,36 +433,56 @@ bool test::DRC_ENGINE::CompileRules()
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for( auto rule : m_rules )
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{
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test::DRC_RULE_CONDITION* condition = nullptr;
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bool compileOk = false;
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std::vector<test::DRC_CONSTRAINT> matchingConstraints;
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drc_dbg(7, "Scan provider %s, rule %s", provider->GetName(), rule->GetName() );
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if( ! rule->IsEnabled() )
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continue;
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if( rule->IsConditional() )
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{
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condition = rule->Condition();
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compileOk = condition->Compile( nullptr, 0, 0 ); // fixme
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}
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for( auto& constraint : rule->Constraints() )
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{
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drc_dbg(7, "scan constraint id %d\n", constraint.GetType() );
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if( constraint.GetType() != id )
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continue;
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ReportAux( wxString::Format( " |- Rule: '%s' ", rule->GetName() ) );
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auto rcons = new CONSTRAINT_WITH_CONDITIONS;
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if( rule->IsConditional() )
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if( condition )
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{
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test::DRC_RULE_CONDITION* condition = rule->Condition();
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rcons->conditions.push_back( condition );
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bool compileOk = condition->Compile( nullptr, 0, 0 ); // fixme
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ReportAux( wxString::Format( " |- condition: '%s' compile: %s", condition->GetExpression(), compileOk ? "OK" : "ERROR") );
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}
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matchingConstraints.push_back( constraint );
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rcons->constraint = constraint;
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rcons->parentRule = rule;
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m_constraintMap[ id ]->sortedConstraints.push_back( rcons );
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}
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if( !matchingConstraints.empty() )
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{
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ReportAux( wxString::Format( " |- Rule: '%s' ", rule->GetName() ) );
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if( condition )
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ReportAux( wxString::Format( " |- condition: '%s' compile: %s", condition->GetExpression(), compileOk ? "OK" : "ERROR") );
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for (const auto& constraint : matchingConstraints )
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{
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ReportAux( wxString::Format( " |- constraint: %s", formatConstraint( constraint ) ) );
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}
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}
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}
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}
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}
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@ -202,7 +503,7 @@ void test::DRC_ENGINE::RunTests( )
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}
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inferImplicitRules();
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inferLegacyRules();
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CompileRules();
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for( auto provider : m_testProviders )
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@ -319,7 +620,9 @@ void test::DRC_ENGINE::ReportStage ( const wxString& aStageName, int index, int
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if( !m_progressReporter )
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return;
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m_progressReporter->SetNumPhases( total );
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m_progressReporter->BeginPhase( index ); // fixme: coalesce all stages/test providers
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m_progressReporter->Report( aStageName );
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}
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@ -240,6 +240,10 @@ public:
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private:
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void addRule( test::DRC_RULE* rule )
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{
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m_rules.push_back(rule);
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}
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void freeCompiledRules();
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@ -259,8 +263,9 @@ private:
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typedef std::unordered_map<test::DRC_CONSTRAINT_TYPE_T, CONSTRAINT_SET*> CONSTRAINT_MAP;
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void inferImplicitRules();
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void inferLegacyRules();
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void loadTestProviders();
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test::DRC_RULE* createInferredRule( const wxString& name, std::set<BOARD_ITEM*> items, int priority );
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BOARD_DESIGN_SETTINGS* m_designSettings;
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BOARD* m_board;
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