export_vrml: more code cleanup and export solder mask
This commit is contained in:
jean-pierre charras
parent
95051c4786
commit
8d5161dae2
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@ -82,8 +82,11 @@ MODEL_VRML::MODEL_VRML() :
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vrml_colors_list[VRML_COLOR_SILK] = VRML_COLOR(
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0.9f, 0.9f, 0.9f, 0.1f, 0.1f, 0.1f, 0.0f, 0.0f, 0.0f, 0.9f, 0.0f, 0.02f );
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// solder paste silver
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vrml_colors_list[VRML_COLOR_TIN] = VRML_COLOR( 0.749f, 0.756f, 0.761f, 0.749f, 0.756f, 0.761f, 0.0f,
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vrml_colors_list[VRML_COLOR_PASTE] = VRML_COLOR( 0.749f, 0.756f, 0.761f, 0.749f, 0.756f, 0.761f, 0.0f,
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0.0f, 0.0f, 0.8f, 0.0f, 0.8f );
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// solder mask green with transparency
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vrml_colors_list[VRML_COLOR_SOLDMASK] = VRML_COLOR(
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0.07f, 0.3f, 0.12f, 0.01f, 0.03f, 0.01f, 0.0f, 0.0f, 0.0f, 0.8f, 0.25f, 0.02f );
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m_plainPCB = false;
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SetOffset( 0.0, 0.0 );
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@ -144,8 +147,10 @@ void MODEL_VRML::SetOffset( double aXoff, double aYoff )
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m_bot_copper.SetVertexOffsets( aXoff, aYoff );
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m_top_silk.SetVertexOffsets( aXoff, aYoff );
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m_bot_silk.SetVertexOffsets( aXoff, aYoff );
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m_top_tin.SetVertexOffsets( aXoff, aYoff );
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m_bot_tin.SetVertexOffsets( aXoff, aYoff );
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m_top_paste.SetVertexOffsets( aXoff, aYoff );
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m_bot_paste.SetVertexOffsets( aXoff, aYoff );
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m_top_soldermask.SetVertexOffsets( aXoff, aYoff );
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m_bot_soldermask.SetVertexOffsets( aXoff, aYoff );
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m_plated_holes.SetVertexOffsets( aXoff, aYoff );
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}
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@ -160,13 +165,35 @@ bool MODEL_VRML::GetLayer3D( LAYER_NUM layer, VRML_LAYER** vlayer )
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case F_Cu: *vlayer = &m_top_copper; return true;
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case B_SilkS: *vlayer = &m_bot_silk; return true;
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case F_SilkS: *vlayer = &m_top_silk; return true;
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case B_Mask: *vlayer = &m_bot_soldermask; return true;
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case F_Mask: *vlayer = &m_top_soldermask; return true;
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case B_Paste: *vlayer = &m_bot_paste; return true;
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case F_Paste: *vlayer = &m_top_paste; return true;
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default: return false;
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}
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}
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void MODEL_VRML::ExportVrmlSolderMask( BOARD* aPcb )
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void MODEL_VRML::ExportVrmlSolderMask()
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{
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//TODO
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SHAPE_POLY_SET holes, outlines = m_pcbOutlines;
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// Build the solder mask opening. the actual shape is the negative shape
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PCB_LAYER_ID layer = F_Mask;
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VRML_LAYER* vrmllayer = &m_top_soldermask;
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for( int lcnt = 0; lcnt < 2; lcnt++ )
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{
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holes.RemoveAllContours();
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outlines.RemoveAllContours();
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outlines = m_pcbOutlines;
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m_Pcb->ConvertBrdLayerToPolygonalContours( layer, holes );
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outlines.BooleanSubtract( holes, SHAPE_POLY_SET::PM_FAST );
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outlines.Fracture( SHAPE_POLY_SET::PM_FAST );
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ExportVrmlPolyPolygon( vrmllayer, outlines, 0.0, wxPoint( 0, 0 ) );
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layer = B_Mask;
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vrmllayer = &m_bot_soldermask;
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}
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}
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@ -278,7 +305,7 @@ void MODEL_VRML::write_triangle_bag( std::ostream& aOut_file, const VRML_COLOR&
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}
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void MODEL_VRML::writeLayers( BOARD* aPcb, const char* aFileName,
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void MODEL_VRML::writeLayers( const char* aFileName,
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OSTREAM* aOutputFile )
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{
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// VRML_LAYER board;
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@ -318,19 +345,36 @@ void MODEL_VRML::writeLayers( BOARD* aPcb, const char* aFileName,
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GetLayerZ( F_Cu ), true );
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}
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// VRML_LAYER m_top_tin;
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m_top_tin.Tesselate( &m_holes );
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// VRML_LAYER m_top_paste;
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m_top_paste.Tesselate( &m_holes );
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if( m_UseInlineModelsInBrdfile )
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{
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write_triangle_bag( *aOutputFile, GetColor( VRML_COLOR_TIN ),
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&m_top_tin, true, true,
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write_triangle_bag( *aOutputFile, GetColor( VRML_COLOR_PASTE ),
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&m_top_paste, true, true,
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GetLayerZ( F_Cu ) + Millimeter2iu( ART_OFFSET / 2.0 ) * m_BoardToVrmlScale,
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0 );
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}
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else
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{
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create_vrml_plane( m_OutputPCB, VRML_COLOR_TIN, &m_top_tin,
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create_vrml_plane( m_OutputPCB, VRML_COLOR_PASTE, &m_top_paste,
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GetLayerZ( F_Cu ) + Millimeter2iu( ART_OFFSET / 2.0 ) * m_BoardToVrmlScale,
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true );
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}
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// VRML_LAYER m_top_soldermask;
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m_top_soldermask.Tesselate( &m_holes );
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if( m_UseInlineModelsInBrdfile )
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{
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write_triangle_bag( *aOutputFile, GetColor( VRML_COLOR_SOLDMASK ),
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&m_top_soldermask, true, true,
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GetLayerZ( F_Cu ) + Millimeter2iu( ART_OFFSET / 2.0 ) * m_BoardToVrmlScale,
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0 );
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}
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else
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{
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create_vrml_plane( m_OutputPCB, VRML_COLOR_SOLDMASK, &m_top_soldermask,
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GetLayerZ( F_Cu ) + Millimeter2iu( ART_OFFSET / 2.0 ) * m_BoardToVrmlScale,
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true );
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}
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@ -349,20 +393,37 @@ void MODEL_VRML::writeLayers( BOARD* aPcb, const char* aFileName,
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GetLayerZ( B_Cu ), false );
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}
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// VRML_LAYER m_bot_tin;
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m_bot_tin.Tesselate( &m_holes );
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// VRML_LAYER m_bot_paste;
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m_bot_paste.Tesselate( &m_holes );
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if( m_UseInlineModelsInBrdfile )
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{
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write_triangle_bag( *aOutputFile, GetColor( VRML_COLOR_TIN ),
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&m_bot_tin, true, false,
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write_triangle_bag( *aOutputFile, GetColor( VRML_COLOR_PASTE ),
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&m_bot_paste, true, false,
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GetLayerZ( B_Cu )
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- Millimeter2iu( ART_OFFSET / 2.0 ) * m_BoardToVrmlScale,
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0 );
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}
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else
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{
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create_vrml_plane( m_OutputPCB, VRML_COLOR_TIN, &m_bot_tin,
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create_vrml_plane( m_OutputPCB, VRML_COLOR_PASTE, &m_bot_paste,
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GetLayerZ( B_Cu ) - Millimeter2iu( ART_OFFSET / 2.0 ) * m_BoardToVrmlScale,
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false );
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}
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// VRML_LAYER m_bot_mask:
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m_bot_soldermask.Tesselate( &m_holes );
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if( m_UseInlineModelsInBrdfile )
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{
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write_triangle_bag( *aOutputFile, GetColor( VRML_COLOR_SOLDMASK ),
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&m_bot_soldermask, true, false,
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GetLayerZ( B_Cu ) - Millimeter2iu( ART_OFFSET / 2.0 ) * m_BoardToVrmlScale,
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0 );
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}
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else
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{
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create_vrml_plane( m_OutputPCB, VRML_COLOR_SOLDMASK, &m_bot_soldermask,
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GetLayerZ( B_Cu ) - Millimeter2iu( ART_OFFSET / 2.0 ) * m_BoardToVrmlScale,
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false );
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}
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@ -372,14 +433,14 @@ void MODEL_VRML::writeLayers( BOARD* aPcb, const char* aFileName,
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if( m_UseInlineModelsInBrdfile )
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{
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write_triangle_bag( *aOutputFile, GetColor( VRML_COLOR_TIN ),
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write_triangle_bag( *aOutputFile, GetColor( VRML_COLOR_PASTE ),
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&m_plated_holes, false, false,
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GetLayerZ( F_Cu ) + Millimeter2iu( ART_OFFSET / 2.0 ) * m_BoardToVrmlScale,
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GetLayerZ( B_Cu ) - Millimeter2iu( ART_OFFSET / 2.0 ) * m_BoardToVrmlScale );
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}
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else
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{
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create_vrml_shell( m_OutputPCB, VRML_COLOR_TIN, &m_plated_holes,
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create_vrml_shell( m_OutputPCB, VRML_COLOR_PASTE, &m_plated_holes,
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GetLayerZ( F_Cu ) + Millimeter2iu( ART_OFFSET / 2.0 ) * m_BoardToVrmlScale,
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GetLayerZ( B_Cu ) - Millimeter2iu( ART_OFFSET / 2.0 ) * m_BoardToVrmlScale );
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}
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@ -417,12 +478,12 @@ void MODEL_VRML::writeLayers( BOARD* aPcb, const char* aFileName,
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}
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void MODEL_VRML::ComputeLayer3D_Zpos( BOARD* pcb )
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void MODEL_VRML::ComputeLayer3D_Zpos()
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{
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int copper_layers = pcb->GetCopperLayerCount();
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int copper_layers = m_Pcb->GetCopperLayerCount();
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// We call it 'layer' thickness, but it's the whole board thickness!
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m_brd_thickness = pcb->GetDesignSettings().GetBoardThickness() * m_BoardToVrmlScale;
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m_brd_thickness = m_Pcb->GetDesignSettings().GetBoardThickness() * m_BoardToVrmlScale;
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double half_thickness = m_brd_thickness / 2;
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// Compute each layer's Z value, more or less like the 3d view
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@ -438,14 +499,14 @@ void MODEL_VRML::ComputeLayer3D_Zpos( BOARD* pcb )
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// To avoid rounding interference, we apply an epsilon to each successive layer
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double epsilon_z = Millimeter2iu( ART_OFFSET ) * m_BoardToVrmlScale;
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SetLayerZ( B_Paste, -half_thickness - epsilon_z * 4 );
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SetLayerZ( B_Adhes, -half_thickness - epsilon_z * 3 );
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SetLayerZ( B_SilkS, -half_thickness - epsilon_z * 2 );
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SetLayerZ( B_Mask, -half_thickness - epsilon_z );
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SetLayerZ( F_Mask, half_thickness + epsilon_z );
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SetLayerZ( F_SilkS, half_thickness + epsilon_z * 2 );
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SetLayerZ( F_Adhes, half_thickness + epsilon_z * 3 );
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SetLayerZ( F_Paste, half_thickness + epsilon_z * 4 );
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SetLayerZ( B_Paste, -half_thickness - epsilon_z );
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SetLayerZ( B_Adhes, -half_thickness - epsilon_z );
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SetLayerZ( B_SilkS, -half_thickness - epsilon_z * 3 );
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SetLayerZ( B_Mask, -half_thickness - epsilon_z * 2 );
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SetLayerZ( F_Mask, half_thickness + epsilon_z * 2 );
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SetLayerZ( F_SilkS, half_thickness + epsilon_z * 3 );
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SetLayerZ( F_Adhes, half_thickness + epsilon_z );
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SetLayerZ( F_Paste, half_thickness + epsilon_z );
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SetLayerZ( Dwgs_User, half_thickness + epsilon_z * 5 );
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SetLayerZ( Cmts_User, half_thickness + epsilon_z * 6 );
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SetLayerZ( Eco1_User, half_thickness + epsilon_z * 7 );
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@ -568,6 +629,30 @@ void MODEL_VRML::ExportVrmlPolygon( LAYER_NUM layer, PCB_SHAPE *aOutline,
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}
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void MODEL_VRML::ExportVrmlPolyPolygon( VRML_LAYER* aVlayer, SHAPE_POLY_SET& aOutlines,
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double aOrientation, wxPoint aPos )
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{
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aOutlines.Rotate( -aOrientation, VECTOR2I( 0, 0 ) );
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aOutlines.Move( aPos );
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for( int icnt = 0; icnt < aOutlines.OutlineCount(); icnt++ )
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{
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const SHAPE_LINE_CHAIN& outline = aOutlines.COutline( icnt );
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int seg = aVlayer->NewContour();
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for( int jj = 0; jj < outline.PointCount(); jj++ )
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{
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if( !aVlayer->AddVertex( seg, outline.CPoint( jj ).x * m_BoardToVrmlScale,
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-outline.CPoint( jj ).y * m_BoardToVrmlScale ) )
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throw( std::runtime_error( aVlayer->GetError() ) );
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}
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aVlayer->EnsureWinding( seg, false );
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}
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}
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void MODEL_VRML::ExportVrmlDrawsegment( PCB_SHAPE* drawseg )
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{
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LAYER_NUM layer = drawseg->GetLayer();
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@ -700,10 +785,10 @@ void MODEL_VRML::ExportVrmlPcbtext( PCB_TEXT* text )
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}
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void MODEL_VRML::ExportVrmlDrawings( BOARD* pcb )
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void MODEL_VRML::ExportVrmlDrawings()
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{
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// draw graphic items
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for( auto drawing : pcb->Drawings() )
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for( auto drawing : m_Pcb->Drawings() )
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{
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PCB_LAYER_ID layer = drawing->GetLayer();
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@ -728,9 +813,9 @@ void MODEL_VRML::ExportVrmlDrawings( BOARD* pcb )
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// board edges and cutouts
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void MODEL_VRML::ExportVrmlBoard( BOARD* aPcb )
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void MODEL_VRML::ExportVrmlBoard()
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{
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if( !aPcb->GetBoardPolygonOutlines( m_pcbOutlines ) )
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if( !m_Pcb->GetBoardPolygonOutlines( m_pcbOutlines ) )
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{
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wxLogWarning( _( "Board outline is malformed. Run DRC for a full analysis." ) );
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}
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@ -777,10 +862,9 @@ void MODEL_VRML::ExportVrmlBoard( BOARD* aPcb )
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}
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void MODEL_VRML::ExportRoundPadstack( BOARD* pcb,
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double x, double y, double r,
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LAYER_NUM bottom_layer, LAYER_NUM top_layer,
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double hole )
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void MODEL_VRML::ExportRoundPadstack( double x, double y, double r,
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LAYER_NUM bottom_layer, LAYER_NUM top_layer,
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double hole )
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{
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LAYER_NUM layer = top_layer;
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bool thru = true;
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@ -822,7 +906,7 @@ void MODEL_VRML::ExportRoundPadstack( BOARD* pcb,
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}
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void MODEL_VRML::ExportVrmlVia( BOARD* aPcb, const VIA* aVia )
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void MODEL_VRML::ExportVrmlVia( const VIA* aVia )
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{
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double x, y, r, hole;
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PCB_LAYER_ID top_layer, bottom_layer;
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@ -838,17 +922,17 @@ void MODEL_VRML::ExportVrmlVia( BOARD* aPcb, const VIA* aVia )
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return;
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// Export the via padstack
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ExportRoundPadstack( aPcb, x, y, r, bottom_layer, top_layer, hole );
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ExportRoundPadstack( x, y, r, bottom_layer, top_layer, hole );
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}
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void MODEL_VRML::ExportVrmlTracks( BOARD* pcb )
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void MODEL_VRML::ExportVrmlTracks()
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{
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for( TRACK* track : pcb->Tracks() )
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for( TRACK* track : m_Pcb->Tracks() )
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{
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if( track->Type() == PCB_VIA_T )
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{
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ExportVrmlVia( pcb, (const VIA*) track );
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ExportVrmlVia( (const VIA*) track );
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}
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else if( ( track->GetLayer() == B_Cu || track->GetLayer() == F_Cu ) && !m_plainPCB )
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{
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@ -893,9 +977,9 @@ void MODEL_VRML::ExportVrmlTracks( BOARD* pcb )
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}
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void MODEL_VRML::ExportVrmlZones( BOARD* aPcb )
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void MODEL_VRML::ExportVrmlZones()
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{
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for( ZONE* zone : aPcb->Zones() )
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for( ZONE* zone : m_Pcb->Zones() )
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{
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for( PCB_LAYER_ID layer : zone->GetLayerSet().Seq() )
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{
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@ -1018,7 +1102,7 @@ void MODEL_VRML::ExportVrmlFpShape( FP_SHAPE* aOutline, FOOTPRINT* aFootprint )
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}
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void MODEL_VRML::ExportVrmlPadshape( VRML_LAYER* aTinLayer, PAD* aPad )
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void MODEL_VRML::ExportVrmlPadshape( VRML_LAYER* aTinLayer, PCB_LAYER_ID aPcbLayer, PAD* aPad )
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{
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// The (maybe offset) pad position
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wxPoint pad_pos = aPad->ShapePos();
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@ -1159,7 +1243,7 @@ void MODEL_VRML::ExportVrmlPadshape( VRML_LAYER* aTinLayer, PAD* aPad )
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}
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void MODEL_VRML::ExportVrmlPad( BOARD* aPcb, PAD* aPad )
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void MODEL_VRML::ExportVrmlPad( PAD* aPad )
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{
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double hole_drill_w = (double) aPad->GetDrillSize().x * m_BoardToVrmlScale / 2.0;
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double hole_drill_h = (double) aPad->GetDrillSize().y * m_BoardToVrmlScale / 2.0;
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@ -1219,21 +1303,17 @@ void MODEL_VRML::ExportVrmlPad( BOARD* aPcb, PAD* aPad )
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// The pad proper, on the selected layers
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LSET layer_mask = aPad->GetLayerSet();
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if( layer_mask[B_Cu] )
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{
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if( layer_mask[B_Paste] )
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ExportVrmlPadshape( &m_bot_tin, aPad );
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else
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ExportVrmlPadshape( &m_bot_copper, aPad );
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}
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if( layer_mask[F_Cu] )
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{
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if( layer_mask[F_Paste] )
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ExportVrmlPadshape( &m_top_tin, aPad );
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else
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ExportVrmlPadshape( &m_top_copper, aPad );
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}
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if( layer_mask[B_Paste] )
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ExportVrmlPadshape( &m_bot_paste, B_Paste, aPad );
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if( layer_mask[B_Cu] )
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ExportVrmlPadshape( &m_bot_copper, B_Cu, aPad );
|
||||
|
||||
if( layer_mask[F_Paste] )
|
||||
ExportVrmlPadshape( &m_top_paste, F_Paste, aPad );
|
||||
|
||||
if( layer_mask[F_Cu] )
|
||||
ExportVrmlPadshape( &m_top_copper, F_Cu, aPad );
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1276,8 +1356,8 @@ static void compose_quat( double q1[4], double q2[4], double qr[4] )
|
|||
}
|
||||
|
||||
|
||||
void MODEL_VRML::ExportVrmlFootprint( BOARD* aPcb, FOOTPRINT* aFootprint,
|
||||
std::ostream* aOutputFile )
|
||||
void MODEL_VRML::ExportVrmlFootprint( FOOTPRINT* aFootprint,
|
||||
std::ostream* aOutputFile )
|
||||
{
|
||||
if( !m_plainPCB )
|
||||
{
|
||||
|
|
@ -1310,7 +1390,7 @@ void MODEL_VRML::ExportVrmlFootprint( BOARD* aPcb, FOOTPRINT* aFootprint,
|
|||
|
||||
// Export pads
|
||||
for( PAD* pad : aFootprint->Pads() )
|
||||
ExportVrmlPad( aPcb, pad );
|
||||
ExportVrmlPad( pad );
|
||||
|
||||
bool isFlipped = aFootprint->GetLayer() == B_Cu;
|
||||
|
||||
|
|
@ -1489,6 +1569,7 @@ bool PCB_EDIT_FRAME::ExportVRML_File( const wxString& aFullFileName, double aMMt
|
|||
|
||||
MODEL_VRML model3d;
|
||||
model_vrml = &model3d;
|
||||
model3d.m_Pcb = GetBoard();
|
||||
model3d.SetScale( aMMtoWRMLunit );
|
||||
model3d.m_UseInlineModelsInBrdfile = aExport3DFiles;
|
||||
model3d.m_Subdir3DFpModels = a3D_Subdir;
|
||||
|
|
@ -1512,40 +1593,40 @@ bool PCB_EDIT_FRAME::ExportVRML_File( const wxString& aFullFileName, double aMMt
|
|||
try
|
||||
{
|
||||
// Preliminary computation: the z value for each layer
|
||||
model3d.ComputeLayer3D_Zpos( pcb );
|
||||
model3d.ComputeLayer3D_Zpos();
|
||||
|
||||
// board edges and cutouts
|
||||
model3d.ExportVrmlBoard( pcb );
|
||||
model3d.ExportVrmlBoard();
|
||||
|
||||
// Drawing and text on the board
|
||||
if( !aUsePlainPCB )
|
||||
model3d.ExportVrmlSolderMask( pcb );
|
||||
model3d.ExportVrmlSolderMask();
|
||||
|
||||
// Drawing and text on the board
|
||||
if( !aUsePlainPCB )
|
||||
model3d.ExportVrmlDrawings( pcb );
|
||||
model3d.ExportVrmlDrawings();
|
||||
|
||||
// Export vias and trackage
|
||||
model3d.ExportVrmlTracks( pcb );
|
||||
model3d.ExportVrmlTracks();
|
||||
|
||||
// Export zone fills
|
||||
if( !aUsePlainPCB )
|
||||
model3d.ExportVrmlZones( pcb );
|
||||
model3d.ExportVrmlZones();
|
||||
|
||||
if( model3d.m_UseInlineModelsInBrdfile )
|
||||
{
|
||||
// Copy fp 3D models in a folder, and link these files in
|
||||
// the board .vrml file
|
||||
model3d.ExportFp3DModelsAsLinkedFile( pcb, aFullFileName );
|
||||
model3d.ExportFp3DModelsAsLinkedFile( aFullFileName );
|
||||
}
|
||||
else
|
||||
{
|
||||
// merge footprints in the .vrml board file
|
||||
for( FOOTPRINT* footprint : pcb->Footprints() )
|
||||
model3d.ExportVrmlFootprint( pcb, footprint, NULL );
|
||||
model3d.ExportVrmlFootprint( footprint, NULL );
|
||||
|
||||
// write out the board and all layers
|
||||
model3d.writeLayers( pcb, TO_UTF8( aFullFileName ), NULL );
|
||||
model3d.writeLayers( TO_UTF8( aFullFileName ), NULL );
|
||||
}
|
||||
}
|
||||
catch( const std::exception& e )
|
||||
|
|
@ -1560,7 +1641,7 @@ bool PCB_EDIT_FRAME::ExportVRML_File( const wxString& aFullFileName, double aMMt
|
|||
return success;
|
||||
}
|
||||
|
||||
void MODEL_VRML::ExportFp3DModelsAsLinkedFile( BOARD* aPcb, const wxString& aFullFileName )
|
||||
void MODEL_VRML::ExportFp3DModelsAsLinkedFile( const wxString& aFullFileName )
|
||||
{
|
||||
// check if the 3D Subdir exists - create if not
|
||||
wxFileName subdir( m_Subdir3DFpModels, "" );
|
||||
|
|
@ -1597,11 +1678,11 @@ void MODEL_VRML::ExportFp3DModelsAsLinkedFile( BOARD* aPcb, const wxString& aFul
|
|||
output_file << " children [\n";
|
||||
|
||||
// Export footprints
|
||||
for( FOOTPRINT* footprint : aPcb->Footprints() )
|
||||
ExportVrmlFootprint( aPcb, footprint, &output_file );
|
||||
for( FOOTPRINT* footprint : m_Pcb->Footprints() )
|
||||
ExportVrmlFootprint( footprint, &output_file );
|
||||
|
||||
// write out the board and all layers
|
||||
writeLayers( aPcb, TO_UTF8( aFullFileName ), &output_file );
|
||||
writeLayers( TO_UTF8( aFullFileName ), &output_file );
|
||||
|
||||
// Close the outer 'transform' node
|
||||
output_file << "]\n}\n";
|
||||
|
|
|
|||
|
|
@ -37,9 +37,10 @@ enum VRML_COLOR_INDEX
|
|||
VRML_COLOR_NONE = -1,
|
||||
VRML_COLOR_PCB = 0,
|
||||
VRML_COLOR_COPPER,
|
||||
VRML_COLOR_SOLDMASK,
|
||||
VRML_COLOR_PASTE,
|
||||
VRML_COLOR_SILK,
|
||||
VRML_COLOR_TIN,
|
||||
VRML_COLOR_LAST
|
||||
VRML_COLOR_LAST // Sentinel
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -123,12 +124,15 @@ public:
|
|||
VRML_LAYER m_bot_copper;
|
||||
VRML_LAYER m_top_silk;
|
||||
VRML_LAYER m_bot_silk;
|
||||
VRML_LAYER m_top_tin;
|
||||
VRML_LAYER m_bot_tin;
|
||||
VRML_LAYER m_top_soldermask;
|
||||
VRML_LAYER m_bot_soldermask;
|
||||
VRML_LAYER m_top_paste;
|
||||
VRML_LAYER m_bot_paste;
|
||||
VRML_LAYER m_plated_holes;
|
||||
|
||||
std::list< SGNODE* > m_components;
|
||||
S3D_CACHE* m_Cache3Dmodels;
|
||||
BOARD* m_Pcb;
|
||||
|
||||
|
||||
bool m_plainPCB;
|
||||
|
|
@ -192,16 +196,16 @@ public:
|
|||
bool SetScale( double aWorldScale );
|
||||
|
||||
// Build and export the solder mask layer
|
||||
void ExportVrmlSolderMask( BOARD* aPcb );
|
||||
void ExportVrmlSolderMask();
|
||||
|
||||
// Build and exports the board outlines (board body)
|
||||
void ExportVrmlBoard( BOARD* aPcb );
|
||||
void ExportVrmlBoard();
|
||||
|
||||
void ExportVrmlZones( BOARD* aPcb );
|
||||
void ExportVrmlZones();
|
||||
|
||||
void ExportVrmlTracks( BOARD* pcb );
|
||||
void ExportVrmlTracks();
|
||||
|
||||
void ExportVrmlVia( BOARD* aPcb, const VIA* aVia );
|
||||
void ExportVrmlVia( const VIA* aVia );
|
||||
|
||||
void ExportVrmlDrawsegment( PCB_SHAPE* drawseg );
|
||||
|
||||
|
|
@ -209,12 +213,11 @@ public:
|
|||
|
||||
void ExportVrmlFpText( FP_TEXT* item );
|
||||
|
||||
void ExportFp3DModelsAsLinkedFile( BOARD* aPcb, const wxString& aFullFileName );
|
||||
void ExportFp3DModelsAsLinkedFile( const wxString& aFullFileName );
|
||||
|
||||
void ExportRoundPadstack( BOARD* pcb,
|
||||
double x, double y, double r,
|
||||
LAYER_NUM bottom_layer, LAYER_NUM top_layer,
|
||||
double hole );
|
||||
void ExportRoundPadstack( double x, double y, double r,
|
||||
LAYER_NUM bottom_layer, LAYER_NUM top_layer,
|
||||
double hole );
|
||||
|
||||
// Basic graphic shapes:
|
||||
void ExportVrmlLine( LAYER_NUM layer,
|
||||
|
|
@ -223,19 +226,18 @@ public:
|
|||
|
||||
void ExportVrmlFpShape( FP_SHAPE* aOutline, FOOTPRINT* aFootprint );
|
||||
|
||||
void ExportVrmlPad( BOARD* aPcb, PAD* aPad );
|
||||
void ExportVrmlPad( PAD* aPad );
|
||||
|
||||
void ExportVrmlFootprint( BOARD* aPcb, FOOTPRINT* aFootprint,
|
||||
std::ostream* aOutputFile );
|
||||
void ExportVrmlFootprint( FOOTPRINT* aFootprint, std::ostream* aOutputFile );
|
||||
|
||||
void ExportVrmlPadshape( VRML_LAYER* aTinLayer, PAD* aPad );
|
||||
void ExportVrmlPadshape( VRML_LAYER* aTinLayer, PCB_LAYER_ID aPcbLayer, PAD* aPad );
|
||||
|
||||
void ExportVrmlDrawings( BOARD* pcb );
|
||||
void ExportVrmlDrawings();
|
||||
|
||||
void ExportVrmlArc( LAYER_NUM layer,
|
||||
double centerx, double centery,
|
||||
double arc_startx, double arc_starty,
|
||||
double width, double arc_angle );
|
||||
double centerx, double centery,
|
||||
double arc_startx, double arc_starty,
|
||||
double width, double arc_angle );
|
||||
|
||||
void ExportVrmlCircle( LAYER_NUM layer,
|
||||
double startx, double starty,
|
||||
|
|
@ -244,14 +246,17 @@ public:
|
|||
void ExportVrmlPolygon( LAYER_NUM layer, PCB_SHAPE *aOutline,
|
||||
double aOrientation, wxPoint aPos );
|
||||
|
||||
void writeLayers( BOARD* aPcb, const char* aFileName, OSTREAM* aOutputFile );
|
||||
void ExportVrmlPolyPolygon( VRML_LAYER* aVlayer, SHAPE_POLY_SET& aOutlines,
|
||||
double aOrientation, wxPoint aPos );
|
||||
|
||||
void writeLayers( const char* aFileName, OSTREAM* aOutputFile );
|
||||
|
||||
// select the VRML layer object to draw on
|
||||
// return true if a layer has been selected.
|
||||
bool GetLayer3D( LAYER_NUM layer, VRML_LAYER** vlayer );
|
||||
|
||||
// Build the Z position of 3D layers
|
||||
void ComputeLayer3D_Zpos(BOARD* pcb );
|
||||
void ComputeLayer3D_Zpos();
|
||||
|
||||
private:
|
||||
void write_triangle_bag( std::ostream& aOut_file, const VRML_COLOR& aColor,
|
||||
|
|
|
|||
Loading…
Reference in New Issue