Modified Spice netlist exporter to run in two passes Now it creates a list of Spice items, so they can be used by other objects, instead of directly dumping them.
This commit is contained in:
Maciej Suminski
parent
a2b16ae640
commit
96dcee81fe
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@ -47,185 +47,76 @@ bool NETLIST_EXPORTER_PSPICE::WriteNetlist( const wxString& aOutFileName, unsign
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}
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bool NETLIST_EXPORTER_PSPICE::Format( OUTPUTFORMATTER* aFormatter, int aCtl )
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bool NETLIST_EXPORTER_PSPICE::Format( OUTPUTFORMATTER* aFormatter, unsigned aCtl )
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{
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std::vector<int> pinSequence; // numeric indices into m_SortedComponentPinList
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wxArrayString stdPinNameArray; // Array containing Standard Pin Names
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const wxString delimiters( "{:,; }" );
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SCH_SHEET_LIST sheetList( g_RootSheet );
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// Netlist options
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bool useNetcodeAsNetName = aCtl & NET_USE_NETCODES_AS_NETNAMES;
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const bool useNetcodeAsNetName = aCtl & NET_USE_NETCODES_AS_NETNAMES;
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// Prepare list of nets generation (not used here, but...
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for( unsigned ii = 0; ii < m_masterList->size(); ii++ )
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m_masterList->GetItem( ii )->m_Flag = 0;
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ProcessNetlist( aCtl );
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aFormatter->Print( 0, ".title KiCad schematic\n" );
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m_netMap.clear();
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// Ground net has to be always assigned to node 0
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m_netMap["GND"] = 0;
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UpdateDirectives( aCtl );
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m_ReferencesAlreadyFound.Clear();
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int curNetIndex = 1;
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for( unsigned sheet_idx = 0; sheet_idx < sheetList.size(); sheet_idx++ )
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for( const auto& item : m_spiceItems )
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{
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// Process component attributes to find Spice directives
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for( EDA_ITEM* item = sheetList[sheet_idx].LastDrawList(); item; item = item->Next() )
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aFormatter->Print( 0, "%c%s ", item.m_primitive, (const char*) item.m_refName.c_str() );
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// Pins to node mapping
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int activePinIndex = 0;
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for( unsigned ii = 0; ii < item.m_pins.size(); ii++ )
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{
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SCH_COMPONENT* comp = findNextComponentAndCreatePinList( item, &sheetList[sheet_idx] );
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if( !comp )
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break;
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item = comp;
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// Reset NodeSeqIndex Count:
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pinSequence.clear();
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// Obtain Spice fields
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SCH_FIELD* spicePrimitiveType = comp->FindField( wxT( "Spice_Primitive" ) );
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SCH_FIELD* spiceModel = comp->FindField( wxT( "Spice_Model" ) );
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SCH_FIELD* netlistEnabledField = comp->FindField( wxT( "Spice_Netlist_Enabled" ) );
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SCH_FIELD* spiceSeqField = comp->FindField( wxT( "Spice_Node_Sequence" ) );
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wxString model = spiceModel ? spiceModel->GetText()
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: GetSpiceFieldDefVal( "Spice_Model", comp, aCtl );
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wxString primType = spicePrimitiveType ? spicePrimitiveType->GetText()
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: GetSpiceFieldDefVal( "Spice_Primitive", comp, aCtl );
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const wxString& RefName = comp->GetRef( &sheetList[sheet_idx] );
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// Check to see if component should be removed from Spice Netlist:
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if( netlistEnabledField )
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// Case of Alt Sequence definition with Unused/Invalid Node index:
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// Valid used Node Indexes are in the set
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// {0,1,2,...m_SortedComponentPinList.size()-1}
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if( !item.m_pinSequence.empty() )
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{
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wxString netlistEnabled = netlistEnabledField->GetText();
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// Different ways of saying 'disabled' (no/false/0)
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if( netlistEnabled.CmpNoCase( "N" ) == 0
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|| netlistEnabled.CmpNoCase( "F" ) == 0
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|| netlistEnabled == "0" )
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// All Vector values must be less <= max package size
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// And Total Vector size should be <= package size
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if( ( (unsigned) item.m_pinSequence[ii] < m_SortedComponentPinList.size() )
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&& ( ii < item.m_pinSequence.size() ) )
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{
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// Case of Alt Pin Sequence in control good Index:
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activePinIndex = item.m_pinSequence[ii];
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}
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else
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{
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// Case of Alt Pin Sequence in control Bad Index or not using all
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// pins for simulation:
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wxASSERT_MSG( false, "Used an invalid pin number in node sequence" );
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continue;
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}
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}
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// Check if an alternative pin sequence is available:
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if( spiceSeqField )
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// Case of Standard Pin Sequence in control:
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else
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{
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// Get the string containing the sequence of nodes:
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wxString nodeSeqIndexLineStr = spiceSeqField->GetText();
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// Verify field exists and is not empty:
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if( !nodeSeqIndexLineStr.IsEmpty() )
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{
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// Create an array of standard pin names from part definition:
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stdPinNameArray.Clear();
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for( unsigned ii = 0; ii < m_SortedComponentPinList.size(); ii++ )
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{
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NETLIST_OBJECT* pin = m_SortedComponentPinList[ii];
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if( !pin )
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continue;
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stdPinNameArray.Add( pin->GetPinNumText() );
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}
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// Get Alt Pin Name Array From User:
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wxStringTokenizer tkz( nodeSeqIndexLineStr, delimiters );
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while( tkz.HasMoreTokens() )
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{
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wxString pinIndex = tkz.GetNextToken();
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int seq;
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// Find PinName In Standard List assign Standard List Index to Name:
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seq = stdPinNameArray.Index( pinIndex );
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if( seq != wxNOT_FOUND )
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pinSequence.push_back( seq );
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}
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}
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activePinIndex = ii;
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}
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int activePinIndex = 0;
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NETLIST_OBJECT* pin = item.m_pins[activePinIndex];
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assert( pin );
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wxString netName = pin->GetNetName();
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aFormatter->Print( 0, "%s%s ", (const char*) primType.c_str(), (const char*) RefName.c_str() );
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for( unsigned ii = 0; ii < m_SortedComponentPinList.size(); ii++ )
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if( useNetcodeAsNetName )
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{
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// Case of Alt Sequence definition with Unused/Invalid Node index:
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// Valid used Node Indexes are in the set
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// {0,1,2,...m_SortedComponentPinList.size()-1}
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if( pinSequence.size() )
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{
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// All Vector values must be less <= max package size
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// And Total Vector size should be <= package size
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if( ( (unsigned) pinSequence[ii] < m_SortedComponentPinList.size() )
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&& ( ii < pinSequence.size() ) )
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{
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// Case of Alt Pin Sequence in control good Index:
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activePinIndex = pinSequence[ii];
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}
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else
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{
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// Case of Alt Pin Sequence in control Bad Index or not using all
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// pins for simulation:
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wxASSERT_MSG( false, "Used an invalid pin number in node sequence" );
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continue;
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}
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}
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// Case of Standard Pin Sequence in control:
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else
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{
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activePinIndex = ii;
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}
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NETLIST_OBJECT* pin = m_SortedComponentPinList[activePinIndex];
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if( !pin )
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continue;
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wxString netName = pin->GetNetName();
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int netIdx;
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// Assign a node number (associated with net)
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if( m_netMap.find( netName ) == m_netMap.end() )
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{
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netIdx = curNetIndex++;
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m_netMap[netName] = netIdx;
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}
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else
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{
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netIdx = m_netMap[netName];
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}
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if( useNetcodeAsNetName )
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{
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aFormatter->Print( 0, "%d ", netIdx );
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}
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else
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{
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sprintPinNetName( netName , wxT( "N-%.6d" ), pin, useNetcodeAsNetName );
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//Replace parenthesis with underscore to prevent parse issues with simulators
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netName.Replace( wxT( "(" ), wxT( "_" ) );
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netName.Replace( wxT( ")" ), wxT( "_" ) );
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if( netName.IsEmpty() )
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netName = wxT( "?" );
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aFormatter->Print( 0, "%s ", TO_UTF8( netName ) );
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}
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assert( m_netMap.count( netName ) );
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aFormatter->Print( 0, "%d ", m_netMap[netName] );
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}
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else
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{
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sprintPinNetName( netName , wxT( "N-%.6d" ), pin, useNetcodeAsNetName );
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aFormatter->Print( 0, "%s\n", (const char*) model.c_str() );
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//Replace parenthesis with underscore to prevent parse issues with simulators
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netName.Replace( wxT( "(" ), wxT( "_" ) );
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netName.Replace( wxT( ")" ), wxT( "_" ) );
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if( netName.IsEmpty() )
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netName = wxT( "?" );
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aFormatter->Print( 0, "%s ", TO_UTF8( netName ) );
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}
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}
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aFormatter->Print( 0, "%s\n", (const char*) item.m_model.c_str() );
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}
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// Print out all directives found in the text fields on the schematics
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@ -238,7 +129,7 @@ bool NETLIST_EXPORTER_PSPICE::Format( OUTPUTFORMATTER* aFormatter, int aCtl )
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wxString NETLIST_EXPORTER_PSPICE::GetSpiceFieldDefVal( const wxString& aField,
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SCH_COMPONENT* aComponent, int aCtl )
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SCH_COMPONENT* aComponent, unsigned aCtl )
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{
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if( aField == "Spice_Primitive" )
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{
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@ -310,7 +201,117 @@ wxString NETLIST_EXPORTER_PSPICE::GetSpiceFieldDefVal( const wxString& aField,
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}
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void NETLIST_EXPORTER_PSPICE::UpdateDirectives( int aCtl )
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void NETLIST_EXPORTER_PSPICE::ProcessNetlist( unsigned aCtl )
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{
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const wxString delimiters( "{:,; }" );
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SCH_SHEET_LIST sheetList( g_RootSheet );
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// Prepare list of nets generation (not used here, but...
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for( unsigned ii = 0; ii < m_masterList->size(); ii++ )
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m_masterList->GetItem( ii )->m_Flag = 0;
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UpdateDirectives( aCtl );
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m_netMap.clear();
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// 0 is reserved for "GND"
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m_netMap["GND"] = 0;
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int netIdx = 1;
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m_ReferencesAlreadyFound.Clear();
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for( unsigned sheet_idx = 0; sheet_idx < sheetList.size(); sheet_idx++ )
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{
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// Process component attributes to find Spice directives
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for( EDA_ITEM* item = sheetList[sheet_idx].LastDrawList(); item; item = item->Next() )
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{
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SCH_COMPONENT* comp = findNextComponentAndCreatePinList( item, &sheetList[sheet_idx] );
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if( !comp )
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break;
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item = comp;
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SPICE_ITEM spiceItem;
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spiceItem.m_parent = comp;
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// Obtain Spice fields
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SCH_FIELD* fieldPrim = comp->FindField( wxT( "Spice_Primitive" ) );
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SCH_FIELD* fieldModel = comp->FindField( wxT( "Spice_Model" ) );
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SCH_FIELD* fieldEnabled = comp->FindField( wxT( "Spice_Netlist_Enabled" ) );
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SCH_FIELD* fieldSeq = comp->FindField( wxT( "Spice_Node_Sequence" ) );
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spiceItem.m_primitive = fieldPrim ? fieldPrim->GetText()[0]
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: GetSpiceFieldDefVal( "Spice_Primitive", comp, aCtl )[0];
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spiceItem.m_model = fieldModel ? fieldModel->GetText()
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: GetSpiceFieldDefVal( "Spice_Model", comp, aCtl );
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spiceItem.m_refName = comp->GetRef( &sheetList[sheet_idx] );
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// Check to see if component should be removed from Spice Netlist:
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spiceItem.m_enabled = true; // assume yes and then verify
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if( fieldEnabled )
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{
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wxString netlistEnabled = fieldEnabled->GetText();
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// Different ways of saying 'disabled' (no/false/0)
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if( netlistEnabled.CmpNoCase( "N" ) == 0
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|| netlistEnabled.CmpNoCase( "F" ) == 0
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|| netlistEnabled == "0" )
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spiceItem.m_enabled = false;
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}
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wxArrayString pinNames;
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// Store pin information
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for( unsigned ii = 0; ii < m_SortedComponentPinList.size(); ii++ )
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{
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NETLIST_OBJECT* pin = m_SortedComponentPinList[ii];
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assert( pin );
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spiceItem.m_pins.push_back( pin );
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pinNames.Add( pin->GetPinNumText() );
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// Create net mapping
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const wxString& netName = pin->GetNetName();
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if( m_netMap.count( netName ) == 0 )
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m_netMap[netName] = netIdx++;
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}
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// Check if an alternative pin sequence is available:
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if( fieldSeq )
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{
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// Get the string containing the sequence of nodes:
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wxString nodeSeqIndexLineStr = fieldSeq->GetText();
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// Verify field exists and is not empty:
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if( !nodeSeqIndexLineStr.IsEmpty() )
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{
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// Get Alt Pin Name Array From User:
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wxStringTokenizer tkz( nodeSeqIndexLineStr, delimiters );
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while( tkz.HasMoreTokens() )
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{
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wxString pinIndex = tkz.GetNextToken();
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int seq;
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// Find PinName In Standard List assign Standard List Index to Name:
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seq = pinNames.Index( pinIndex );
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if( seq != wxNOT_FOUND )
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spiceItem.m_pinSequence.push_back( seq );
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}
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}
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}
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m_spiceItems.push_back( spiceItem );
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}
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}
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}
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void NETLIST_EXPORTER_PSPICE::UpdateDirectives( unsigned aCtl )
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{
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const SCH_SHEET_LIST& sheetList = g_RootSheet;
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@ -354,7 +355,7 @@ void NETLIST_EXPORTER_PSPICE::UpdateDirectives( int aCtl )
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}
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void NETLIST_EXPORTER_PSPICE::writeDirectives( OUTPUTFORMATTER* aFormatter, int aCtl ) const
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void NETLIST_EXPORTER_PSPICE::writeDirectives( OUTPUTFORMATTER* aFormatter, unsigned aCtl ) const
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{
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for( auto& dir : m_directives )
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{
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@ -36,7 +36,8 @@ enum SPICE_NETLIST_OPTIONS {
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NET_USE_X_PREFIX = 2, // change "U" and "IC" reference prefix to "X"
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NET_USE_NETCODES_AS_NETNAMES = 4, // use netcode numbers as netnames
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NET_ADJUST_INCLUDE_PATHS = 8, // use full paths for included files (if they are in search path)
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NET_ADJUST_PASSIVE_VALS = 16 // reformat passive component values (e.g. 1M -> 1Meg)
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NET_ADJUST_PASSIVE_VALS = 16, // reformat passive component values (e.g. 1M -> 1Meg)
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NET_ALL_FLAGS = 0xffff
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};
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/// @todo add NET_ADJUST_INCLUDE_PATHS & NET_ADJUST_PASSIVE_VALS checkboxes in the netlist export dialog
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@ -58,16 +59,40 @@ public:
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{
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}
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struct SPICE_ITEM
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{
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SCH_COMPONENT* m_parent;
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wxChar m_primitive;
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wxString m_model;
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wxString m_refName;
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bool m_enabled;
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///> Array containing Standard Pin Name
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std::vector<NETLIST_OBJECT*> m_pins;
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///> Numeric indices into m_SortedComponentPinList
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std::vector<int> m_pinSequence;
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};
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typedef std::list<SPICE_ITEM> SPICE_ITEM_LIST;
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///> Net name to node number mapping
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typedef std::map<wxString, int> NET_INDEX_MAP;
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const SPICE_ITEM_LIST& GetSpiceItems() const
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{
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return m_spiceItems;
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}
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/**
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* Function WriteNetlist
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* writes to specified output file
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*/
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bool WriteNetlist( const wxString& aOutFileName, unsigned aNetlistOptions );
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bool Format( OUTPUTFORMATTER* aFormatter, int aCtl );
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bool Format( OUTPUTFORMATTER* aFormatter, unsigned aCtl );
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void ProcessNetlist( unsigned aCtl );
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const NET_INDEX_MAP& GetNetIndexMap() const
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{
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@ -79,9 +104,9 @@ public:
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return m_spiceFields;
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}
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static wxString GetSpiceFieldDefVal( const wxString& aField, SCH_COMPONENT* aComponent, int aCtl );
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static wxString GetSpiceFieldDefVal( const wxString& aField, SCH_COMPONENT* aComponent, unsigned aCtl );
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void UpdateDirectives( int aCtl );
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void UpdateDirectives( unsigned aCtl );
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const std::vector<wxString> GetDirectives() const
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{
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@ -89,7 +114,7 @@ public:
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}
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protected:
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virtual void writeDirectives( OUTPUTFORMATTER* aFormatter, int aCtl ) const;
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virtual void writeDirectives( OUTPUTFORMATTER* aFormatter, unsigned aCtl ) const;
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private:
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// Spice directives found in the processed schematic sheet
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@ -97,6 +122,8 @@ private:
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NET_INDEX_MAP m_netMap;
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SPICE_ITEM_LIST m_spiceItems;
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SEARCH_STACK* m_paths;
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// Component fields that are processed during netlist export & simulation
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