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Re-resolve netclasses after assigning netclass to pattern. 

Fixes https://gitlab.com/kicad/code/kicad/issues/12965
This commit is contained in:
Jeff Young 2022-11-22 14:24:20 +00:00
parent 62863d6c5b
commit 97fd99ec99
12 changed files with 27 additions and 23 deletions
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23
pcbnew/board.cpp
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@ -1467,7 +1467,7 @@ void BOARD::SynchronizeProperties()
} }
void BOARD::SynchronizeNetsAndNetClasses() void BOARD::SynchronizeNetsAndNetClasses( bool aResetTrackAndViaSizes )
{ {
if( !m_project ) if( !m_project )
return; return;
@ -1478,15 +1478,18 @@ void BOARD::SynchronizeNetsAndNetClasses()
for( NETINFO_ITEM* net : m_NetInfo ) for( NETINFO_ITEM* net : m_NetInfo )
net->SetNetClass( bds.m_NetSettings->GetEffectiveNetClass( net->GetNetname() ) ); net->SetNetClass( bds.m_NetSettings->GetEffectiveNetClass( net->GetNetname() ) );
// Set initial values for custom track width & via size to match the default if( aResetTrackAndViaSizes )
// netclass settings {
bds.UseCustomTrackViaSize( false ); // Set initial values for custom track width & via size to match the default
bds.SetCustomTrackWidth( defaultNetClass->GetTrackWidth() ); // netclass settings
bds.SetCustomViaSize( defaultNetClass->GetViaDiameter() ); bds.UseCustomTrackViaSize( false );
bds.SetCustomViaDrill( defaultNetClass->GetViaDrill() ); bds.SetCustomTrackWidth( defaultNetClass->GetTrackWidth() );
bds.SetCustomDiffPairWidth( defaultNetClass->GetDiffPairWidth() ); bds.SetCustomViaSize( defaultNetClass->GetViaDiameter() );
bds.SetCustomDiffPairGap( defaultNetClass->GetDiffPairGap() ); bds.SetCustomViaDrill( defaultNetClass->GetViaDrill() );
bds.SetCustomDiffPairViaGap( defaultNetClass->GetDiffPairViaGap() ); bds.SetCustomDiffPairWidth( defaultNetClass->GetDiffPairWidth() );
bds.SetCustomDiffPairGap( defaultNetClass->GetDiffPairGap() );
bds.SetCustomDiffPairViaGap( defaultNetClass->GetDiffPairViaGap() );
}
InvokeListeners( &BOARD_LISTENER::OnBoardNetSettingsChanged, *this ); InvokeListeners( &BOARD_LISTENER::OnBoardNetSettingsChanged, *this );
} }

2
pcbnew/board.h
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@ -869,7 +869,7 @@ public:
* the list of nets) Also this function removes the non existing nets in netclasses * the list of nets) Also this function removes the non existing nets in netclasses
* and add net nets in default netclass (this happens after reading a netlist) * and add net nets in default netclass (this happens after reading a netlist)
*/ */
void SynchronizeNetsAndNetClasses(); void SynchronizeNetsAndNetClasses( bool aResetTrackAndViaSizes );
/** /**
* Copy the current project's text variables into the boards property cache. * Copy the current project's text variables into the boards property cache.

2
pcbnew/drc/drc_engine.cpp
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@ -371,7 +371,7 @@ void DRC_ENGINE::loadImplicitRules()
} }
}; };
m_board->SynchronizeNetsAndNetClasses(); m_board->SynchronizeNetsAndNetClasses( false );
makeNetclassRules( bds.m_NetSettings->m_DefaultNetClass, true ); makeNetclassRules( bds.m_NetSettings->m_DefaultNetClass, true );
for( const auto& [ name, netclass ] : bds.m_NetSettings->m_NetClasses ) for( const auto& [ name, netclass ] : bds.m_NetSettings->m_NetClasses )

4
pcbnew/files.cpp
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@ -1062,7 +1062,7 @@ bool PCB_EDIT_FRAME::SavePcbFile( const wxString& aFileName, bool addToHistory,
SaveProjectSettings(); SaveProjectSettings();
GetBoard()->SynchronizeProperties(); GetBoard()->SynchronizeProperties();
GetBoard()->SynchronizeNetsAndNetClasses(); GetBoard()->SynchronizeNetsAndNetClasses( false );
} }
wxString tempFile = wxFileName::CreateTempFileName( "pcbnew" ); wxString tempFile = wxFileName::CreateTempFileName( "pcbnew" );
@ -1167,7 +1167,7 @@ bool PCB_EDIT_FRAME::SavePcbCopy( const wxString& aFileName, bool aCreateProject
// edited via the DRC dialog as well as the Board Setup dialog), DRC exclusions, etc. // edited via the DRC dialog as well as the Board Setup dialog), DRC exclusions, etc.
SaveProjectSettings(); SaveProjectSettings();
GetBoard()->SynchronizeNetsAndNetClasses(); GetBoard()->SynchronizeNetsAndNetClasses( false );
try try
{ {

2
pcbnew/initpcb.cpp
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@ -126,7 +126,7 @@ bool FOOTPRINT_EDIT_FRAME::Clear_Pcb( bool aQuery )
BOARD* board = new BOARD; BOARD* board = new BOARD;
board->GetDesignSettings() = GetDesignSettings(); board->GetDesignSettings() = GetDesignSettings();
board->SynchronizeNetsAndNetClasses(); board->SynchronizeNetsAndNetClasses( true );
SetBoard( board ); SetBoard( board );
// This board will only be used to hold a footprint for editing // This board will only be used to hold a footprint for editing

2
pcbnew/netinfo_list.cpp
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@ -164,7 +164,7 @@ void NETINFO_LIST::buildListOfNets()
for( NETINFO_ITEM* net : *this ) for( NETINFO_ITEM* net : *this )
net->Clear(); net->Clear();
m_parent->SynchronizeNetsAndNetClasses( ); m_parent->SynchronizeNetsAndNetClasses( false );
m_parent->SetAreasNetCodesFromNetNames(); m_parent->SetAreasNetCodesFromNetNames();
} }

2
pcbnew/netlist_reader/board_netlist_updater.cpp
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@ -1085,7 +1085,7 @@ bool BOARD_NETLIST_UPDATER::UpdateNetlist( NETLIST& aNetlist )
// * it is useless because zones will be refilled after placing new footprints // * it is useless because zones will be refilled after placing new footprints
m_commit.Push( _( "Update netlist" ), m_newFootprintsCount ? ZONE_FILL_OP : 0 ); m_commit.Push( _( "Update netlist" ), m_newFootprintsCount ? ZONE_FILL_OP : 0 );
m_board->SynchronizeNetsAndNetClasses(); m_board->SynchronizeNetsAndNetClasses( true );
m_frame->SaveProjectSettings(); m_frame->SaveProjectSettings();
} }

2
pcbnew/pcb_edit_frame.cpp
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@ -1123,7 +1123,7 @@ void PCB_EDIT_FRAME::ShowBoardSetupDialog( const wxString& aInitialPage )
if( dlg.ShowQuasiModal() == wxID_OK ) if( dlg.ShowQuasiModal() == wxID_OK )
{ {
GetBoard()->SynchronizeNetsAndNetClasses(); GetBoard()->SynchronizeNetsAndNetClasses( true );
SaveProjectSettings(); SaveProjectSettings();
Kiway().CommonSettingsChanged( false, true ); Kiway().CommonSettingsChanged( false, true );

4
pcbnew/python/scripting/pcbnew_scripting_helpers.cpp
View File

@ -189,7 +189,7 @@ BOARD* LoadBoard( wxString& aFileName, IO_MGR::PCB_FILE_T aFormat )
brd->BuildConnectivity(); brd->BuildConnectivity();
brd->BuildListOfNets(); brd->BuildListOfNets();
brd->SynchronizeNetsAndNetClasses(); brd->SynchronizeNetsAndNetClasses( false );
} }
return brd; return brd;
@ -241,7 +241,7 @@ BOARD* CreateEmptyBoard()
bool SaveBoard( wxString& aFileName, BOARD* aBoard, IO_MGR::PCB_FILE_T aFormat, bool aSkipSettings ) bool SaveBoard( wxString& aFileName, BOARD* aBoard, IO_MGR::PCB_FILE_T aFormat, bool aSkipSettings )
{ {
aBoard->BuildConnectivity(); aBoard->BuildConnectivity();
aBoard->SynchronizeNetsAndNetClasses(); aBoard->SynchronizeNetsAndNetClasses( false );
// Ensure the "C" locale is temporary set, before saving any file // Ensure the "C" locale is temporary set, before saving any file
// It also avoid wxWidget alerts about locale issues, later, when using Python 3 // It also avoid wxWidget alerts about locale issues, later, when using Python 3

2
pcbnew/specctra_import_export/specctra_export.cpp
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@ -130,7 +130,7 @@ void ExportBoardToSpecctraFile( BOARD* aBoard, const wxString& aFullFilename )
try try
{ {
aBoard->SynchronizeNetsAndNetClasses(); aBoard->SynchronizeNetsAndNetClasses( false );
db.FromBOARD( aBoard ); db.FromBOARD( aBoard );
db.ExportPCB( aFullFilename, true ); db.ExportPCB( aFullFilename, true );
db.RevertFOOTPRINTs( aBoard ); db.RevertFOOTPRINTs( aBoard );

3
pcbnew/tools/board_editor_control.cpp
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@ -1522,7 +1522,8 @@ int BOARD_EDITOR_CONTROL::AssignNetclass( const TOOL_EVENT& aEvent )
canvas()->ForceRefresh(); canvas()->ForceRefresh();
} ); } );
dlg.ShowModal(); if( dlg.ShowModal() == wxID_OK )
board()->SynchronizeNetsAndNetClasses( false );
return 0; return 0;
} }

2
pcbnew/tools/pcb_control.cpp
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@ -1279,7 +1279,7 @@ int PCB_CONTROL::AppendBoard( PLUGIN& pi, wxString& fileName )
// rebuild nets and ratsnest before any use of nets // rebuild nets and ratsnest before any use of nets
brd->BuildListOfNets(); brd->BuildListOfNets();
brd->SynchronizeNetsAndNetClasses(); brd->SynchronizeNetsAndNetClasses( true );
brd->BuildConnectivity(); brd->BuildConnectivity();
// Synchronize layers // Synchronize layers