Fix a bone-headed cause of non-determinism

eeschema/connection_graph.cpp

@@ -1864,12 +1864,13 @@ void CONNECTION_GRAPH::propagateToNeighbors( CONNECTION_SUBGRAPH* aSubgraph )
             if( ( priority >= CONNECTION_SUBGRAPH::PRIORITY::POWER_PIN ) ||
                 ( !originalStrong && candidateStrong ) ||
                 ( priority >= highest && candidateStrong &&
-                  subgraph->m_sheet.size() < aSubgraph->m_sheet.size() ) ||
+                  subgraph->m_sheet.size() < original->m_sheet.size() ) ||
-                ( !originalStrong && !candidateStrong && candidateName < originalName ) )
+                ( ( originalStrong == candidateStrong ) && candidateName < originalName ) )
             {
                 original       = subgraph;
                 highest        = priority;
                 originalStrong = candidateStrong;
+                originalName   = subgraph->m_driver_connection->Name();
             }
         }
     }

qa/eeschema/data/netlists/test_global_promotion_2/test_global_promotion_2.kicad_pro

@@ -29,6 +29,181 @@
   "cvpcb": {
     "equivalence_files": []
   },
+  "erc": {
+    "erc_exclusions": [],
+    "meta": {
+      "version": 0
+    },
+    "pin_map": [
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        1,
+        0,
+        1,
+        2
+      ],
+      [
+        0,
+        1,
+        0,
+        0,
+        0,
+        1,
+        1,
+        2,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        1,
+        1,
+        1,
+        1,
+        1,
+        1,
+        1,
+        1,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        1,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        2,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        1,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2
+      ]
+    ],
+    "rule_severities": {
+      "bus_definition_conflict": "error",
+      "bus_label_syntax": "error",
+      "bus_to_bus_conflict": "error",
+      "bus_to_net_conflict": "error",
+      "different_unit_footprint": "error",
+      "different_unit_net": "error",
+      "duplicate_sheet_names": "error",
+      "global_label_dangling": "warning",
+      "hier_label_mismatch": "error",
+      "label_dangling": "error",
+      "lib_symbol_issues": "warning",
+      "multiple_net_names": "warning",
+      "net_not_bus_member": "warning",
+      "no_connect_connected": "warning",
+      "no_connect_dangling": "warning",
+      "pin_not_connected": "error",
+      "pin_not_driven": "error",
+      "pin_to_pin": "warning",
+      "power_pin_not_driven": "error",
+      "similar_labels": "warning",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
+    }
+  },
   "libraries": {
     "pinned_footprint_libs": [],
     "pinned_symbol_libs": []
@@ -40,16 +215,21 @@
   "net_settings": {
     "classes": [
       {
+        "bus_width": 6.0,
         "clearance": 0.2,
         "diff_pair_gap": 0.25,
         "diff_pair_via_gap": 0.25,
         "diff_pair_width": 0.2,
+        "line_style": 0,
         "microvia_diameter": 0.3,
         "microvia_drill": 0.1,
         "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
         "track_width": 0.25,
         "via_diameter": 0.8,
-        "via_drill": 0.4
+        "via_drill": 0.4,
+        "wire_width": 6.0
       }
     ],
     "meta": {
@@ -64,26 +244,37 @@
       "netlist": "",
       "specctra_dsn": "",
       "step": "",
-      "vmrl": ""
+      "vmrl": "",
+      "vrml": ""
     },
     "page_layout_descr_file": ""
   },
   "schematic": {
     "drawing": {
-      "default_bus_thickness": 12,
+      "default_bus_thickness": 12.0,
-      "default_junction_size": 40,
+      "default_junction_size": 40.0,
-      "default_line_thickness": 6,
+      "default_line_thickness": 6.0,
-      "default_text_size": 50,
+      "default_text_size": 50.0,
-      "default_wire_thickness": 6,
+      "default_wire_thickness": 6.0,
-      "field_names": "(templatefields)",
+      "field_names": [],
+      "intersheets_ref_prefix": "",
+      "intersheets_ref_short": false,
+      "intersheets_ref_show": false,
+      "intersheets_ref_suffix": "",
+      "junction_size_choice": 3,
+      "pin_symbol_size": 25.0,
       "text_offset_ratio": 0.3
     },
     "legacy_lib_dir": "",
     "legacy_lib_list": [],
+    "meta": {
+      "version": 0
+    },
     "net_format_name": "Pcbnew",
     "page_layout_descr_file": "",
     "plot_directory": "",
     "spice_adjust_passive_values": false,
+    "spice_external_command": "spice \"%I\"",
     "subpart_first_id": 65,
     "subpart_id_separator": 0
   },

qa/eeschema/data/netlists/test_global_promotion_2/test_global_promotion_2.net

@@ -128,13 +128,13 @@
       (node (ref "J2") (pin "1") (pinfunction "Pin_1"))
       (node (ref "R1") (pin "1"))
       (node (ref "R2") (pin "1")))
-    (net (code "3") (name "/sheet5CC165F1/LIVE_1")
+    (net (code "3") (name "/Sheet5CC15EF8/NEUTRAL")
-      (node (ref "J1") (pin "2") (pinfunction "Pin_2"))
-      (node (ref "R4") (pin "2")))
-    (net (code "4") (name "/sheet5CC165F1/NEUTRAL")
       (node (ref "J2") (pin "3") (pinfunction "Pin_3"))
       (node (ref "R1") (pin "2"))
       (node (ref "R3") (pin "2")))
+    (net (code "4") (name "/sheet5CC165F1/LIVE_1")
+      (node (ref "J1") (pin "2") (pinfunction "Pin_2"))
+      (node (ref "R4") (pin "2")))
     (net (code "5") (name "LIVE")
       (node (ref "J1") (pin "1") (pinfunction "Pin_1"))
       (node (ref "R2") (pin "2")))

qa/eeschema/data/netlists/weak_vector_bus_disambiguation/weak_vector_bus_disambiguation.net

@@ -117,15 +117,15 @@
     (library (logical "Device")
       (uri "/home/jon/kicad-library/kicad-symbols//Device.kicad_sym")))
   (nets
-    (net (code "1") (name "/Merge/D1")
+    (net (code "1") (name "/Merge/A1")
-      (node (ref "R2") (pin "1"))
-      (node (ref "R4") (pin "1")))
-    (net (code "2") (name "/Merge/D2")
-      (node (ref "R2") (pin "2"))
-      (node (ref "R4") (pin "2")))
-    (net (code "3") (name "/Sub1/B1")
       (node (ref "R1") (pin "1"))
       (node (ref "R3") (pin "1")))
-    (net (code "4") (name "/Sub1/B2")
+    (net (code "2") (name "/Merge/A2")
       (node (ref "R1") (pin "2"))
-      (node (ref "R3") (pin "2")))))
+      (node (ref "R3") (pin "2")))
+    (net (code "4") (name "/Merge/D1")
+      (node (ref "R2") (pin "1"))
+      (node (ref "R4") (pin "1")))
+    (net (code "5") (name "/Merge/D2")
+      (node (ref "R2") (pin "2"))
+      (node (ref "R4") (pin "2")))))