DRC: Verify overlapping layers in physical clearance
When checking the physical clearance on a layer, it is critical to check that the via hole exists on that layer. Blind/buried and micro vias may not overlap, so should be excluded from this check when they don't exist on a particular layer Similarly, we should only be reporting a single physical clearance error for each item pair even though they may have multiple errors across multiple layers in the case of via-via clearance
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@ -71,7 +71,7 @@ public:
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}
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private:
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bool testItemAgainstItem( BOARD_ITEM* aItem, SHAPE* aItemShape, PCB_LAYER_ID aLayer,
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int testItemAgainstItem( BOARD_ITEM* aItem, SHAPE* aItemShape, PCB_LAYER_ID aLayer,
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BOARD_ITEM* other );
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void testItemAgainstZones( BOARD_ITEM* aItem, PCB_LAYER_ID aLayer );
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@ -218,8 +218,22 @@ bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::Run()
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// Visitor:
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[&]( BOARD_ITEM* other ) -> bool
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{
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return testItemAgainstItem( item, itemShape.get(), layer,
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other );
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if( testItemAgainstItem( item, itemShape.get(), layer,
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other ) > 0 )
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{
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BOARD_ITEM* a = item;
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BOARD_ITEM* b = other;
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// store canonical order
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if( static_cast<void*>( a ) > static_cast<void*>( b ) )
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std::swap( a, b );
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// Once we record one DRC for error for physical clearance
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// we don't need to record more
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checkedPairs[ { a, b } ].set();
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}
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return !m_drcEngine->IsCancelled();
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},
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m_board->m_DRCMaxPhysicalClearance );
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@ -575,7 +589,7 @@ void DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testZoneLayer( ZONE* aZone, PCB_LAYER
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}
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bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aItem,
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int DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aItem,
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SHAPE* aItemShape,
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PCB_LAYER_ID aLayer,
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BOARD_ITEM* other )
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@ -585,6 +599,7 @@ bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aIte
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DRC_CONSTRAINT constraint;
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int clearance = 0;
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int actual;
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int violations = 0;
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VECTOR2I pos;
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std::shared_ptr<SHAPE> otherShape = other->GetEffectiveShape( aLayer );
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@ -610,6 +625,7 @@ bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aIte
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drce->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drce, pos, aLayer );
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++violations;
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}
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}
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@ -623,6 +639,8 @@ bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aIte
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{
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if( aItem->GetLayerSet().Contains( aLayer ) )
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itemHoleShape = aItem->GetEffectiveHoleShape();
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else
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return violations;
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}
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else if( aItem->HasHole() )
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{
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@ -633,6 +651,8 @@ bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aIte
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{
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if( other->GetLayerSet().Contains( aLayer ) )
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otherHoleShape = other->GetEffectiveHoleShape();
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else
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return violations;
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}
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else if( other->HasHole() )
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{
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@ -661,6 +681,7 @@ bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aIte
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drce->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drce, pos, aLayer );
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++violations;
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}
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if( otherHoleShape && otherHoleShape->Collide( aItemShape, clearance, &actual, &pos ) )
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@ -676,11 +697,12 @@ bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aIte
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drce->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drce, pos, aLayer );
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++violations;
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}
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}
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}
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return !m_drcEngine->IsCancelled();
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return violations;
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}
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