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Don't test non-overlapping non-through-hole vias. 

Fixes https://gitlab.com/kicad/code/kicad/-/issues/17426
This commit is contained in:
Jeff Young 2024-03-13 15:18:42 +00:00
parent 91d949f59e
commit a091767551
1 changed files with 9 additions and 0 deletions
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9
pcbnew/drc/drc_test_provider_hole_to_hole.cpp
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@ -277,6 +277,15 @@ bool DRC_TEST_PROVIDER_HOLE_TO_HOLE::testHoleAgainstHole( BOARD_ITEM* aItem, SHA
int epsilon = m_board->GetDesignSettings().GetDRCEpsilon(); int epsilon = m_board->GetDesignSettings().GetDRCEpsilon();
SEG::ecoord epsilon_sq = SEG::Square( epsilon ); SEG::ecoord epsilon_sq = SEG::Square( epsilon );
// Blind-buried or microvias that don't overlap layers aren't an issue.
if( aItem->Type() == PCB_VIA_T && aOther->Type() == PCB_VIA_T )
{
LSET viaHoleLayers = static_cast<PCB_VIA*>( aItem )->GetLayerSet() & LSET::AllCuMask();
if( ( viaHoleLayers & static_cast<PCB_VIA*>( aOther )->GetLayerSet() ).none() )
return false;
}
// Holes at same location generate a separate violation // Holes at same location generate a separate violation
if( ( aHole->GetCenter() - otherHole->GetCenter() ).SquaredEuclideanNorm() < epsilon_sq ) if( ( aHole->GetCenter() - otherHole->GetCenter() ).SquaredEuclideanNorm() < epsilon_sq )
{ {