Vias are plated holes too....
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@ -124,9 +124,10 @@ static void isPlated( LIBEVAL::CONTEXT* aCtx, void* self )
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PCB_EXPR_VAR_REF* vref = static_cast<PCB_EXPR_VAR_REF*>( self );
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BOARD_ITEM* item = vref ? vref->GetObject( aCtx ) : nullptr;
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PAD* pad = dynamic_cast<PAD*>( item );
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if( pad && pad->GetAttribute() == PAD_ATTRIB_PTH )
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if( item->Type() == PCB_PAD_T && dynamic_cast<PAD*>( item )->GetAttribute() == PAD_ATTRIB_PTH )
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result->Set( 1.0 );
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else if( item->Type() == PCB_VIA_T )
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result->Set( 1.0 );
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}
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