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Redo pad & via painting (again). 

New strategy isolates all draw/don't draw decisions to the ViewGetLOD
routines, and all dimmed/not dimmed to PCB_RENDER_SETTINGS::GetColor.
The actual drawing in PCB_PAINTER is more-or-less conditon free.

Also adds new layers for pad and via hole walls so that they can be
controlled for high-contrast mode.

Also changes the drawing paradigm so that the pads are drawn even when
not on the high contrast layer, just in low contrast.  The hole wall
is drawn in high contrast.  This actually makes things clearer to the
user (although to be honest was done to keep from having to re-render
pads when the high contrast layer changes since we have two separate
layers now that we can adjut colours on).

Fixes https://gitlab.com/kicad/code/kicad/issues/7328
This commit is contained in:
Jeff Young 2021-01-30 14:41:31 +00:00
parent e72262a007
commit a235103e48
19 changed files with 350 additions and 382 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
common/layer_id.cpp
View File

@ -154,7 +154,10 @@ wxString LayerName( int aLayer )
case LAYER_VIA_THROUGH: return _( "Through vias" );
case LAYER_VIA_BBLIND: return _( "Bl/Buried vias" );
case LAYER_VIA_MICROVIA: return _( "Micro-vias" );
case LAYER_VIAS_HOLES: return _( "Via holes" );
case LAYER_VIA_HOLES: return _( "Via holes" );
case LAYER_VIA_HOLEWALLS: return _( "Via hole walls" );
case LAYER_PAD_PLATEDHOLES: return _( "Plated holes" );
case LAYER_PAD_HOLEWALLS: return _( "Plated hole walls" );
case LAYER_NON_PLATEDHOLES: return _( "Non-plated holes" );
case LAYER_RATSNEST: return _( "Ratsnest" );
case LAYER_NO_CONNECTS: return _( "No-connects" );

6
common/lset.cpp
View File

@ -947,8 +947,10 @@ GAL_SET GAL_SET::DefaultVisible()
LAYER_MOD_REFERENCES,
LAYER_TRACKS,
LAYER_PADS_TH,
LAYER_PADS_PLATEDHOLES,
LAYER_VIAS_HOLES,
LAYER_PAD_PLATEDHOLES,
LAYER_PAD_HOLEWALLS,
LAYER_VIA_HOLES,
LAYER_VIA_HOLEWALLS,
LAYER_DRC_ERROR,
LAYER_DRC_WARNING,
// LAYER_DRC_EXCLUSION, // DRC exclusions hidden by default

8
common/settings/builtin_color_themes.h
View File

@ -88,14 +88,14 @@ static const std::map<int, COLOR4D> s_defaultTheme =
{ LAYER_NO_CONNECTS, CSS_COLOR( 0, 0, 132, 1 ) },
{ LAYER_PAD_BK, CSS_COLOR( 77, 127, 196, 1 ) },
{ LAYER_PAD_FR, CSS_COLOR( 200, 52, 52, 1 ) },
{ LAYER_PADS_PLATEDHOLES, CSS_COLOR( 194, 194, 0, 1 ) },
{ LAYER_PAD_PLATEDHOLES, CSS_COLOR( 194, 194, 0, 1 ) },
{ LAYER_PADS_TH, CSS_COLOR( 227, 183, 46, 1 ) },
{ LAYER_NON_PLATEDHOLES, CSS_COLOR( 26, 196, 210, 1 ) },
{ LAYER_RATSNEST, CSS_COLOR( 245, 255, 213, 0.702 ) },
{ LAYER_SELECT_OVERLAY, CSS_COLOR( 4, 255, 67, 1 ) },
{ LAYER_VIA_THROUGH, CSS_COLOR( 236, 236, 236, 1 ) },
{ LAYER_VIA_BBLIND, CSS_COLOR( 187, 151, 38, 1 ) },
{ LAYER_VIAS_HOLES, CSS_COLOR( 227, 183, 46, 1 ) },
{ LAYER_VIA_HOLES, CSS_COLOR( 227, 183, 46, 1 ) },
{ LAYER_VIA_MICROVIA, CSS_COLOR( 0, 132, 132, 1 ) },
{ LAYER_WORKSHEET, CSS_COLOR( 200, 114, 171, 1 ) },
@ -234,14 +234,14 @@ static const std::map<int, COLOR4D> s_classicTheme =
{ LAYER_NO_CONNECTS, COLOR4D( BLUE ) },
{ LAYER_PAD_BK, COLOR4D( GREEN ) },
{ LAYER_PAD_FR, COLOR4D( RED ) },
{ LAYER_PADS_PLATEDHOLES, COLOR4D( YELLOW ) },
{ LAYER_PAD_PLATEDHOLES, COLOR4D( YELLOW ) },
{ LAYER_PADS_TH, COLOR4D( YELLOW ) },
{ LAYER_NON_PLATEDHOLES, COLOR4D( YELLOW ) },
{ LAYER_RATSNEST, COLOR4D( WHITE ) },
{ LAYER_SELECT_OVERLAY, COLOR4D( PUREGREEN ) },
{ LAYER_VIA_THROUGH, COLOR4D( LIGHTGRAY ) },
{ LAYER_VIA_BBLIND, COLOR4D( BROWN ) },
{ LAYER_VIAS_HOLES, COLOR4D( 0.5, 0.4, 0, 0.8 ) },
{ LAYER_VIA_HOLES, COLOR4D( 0.5, 0.4, 0, 0.8 ) },
{ LAYER_VIA_MICROVIA, COLOR4D( CYAN ) },
{ LAYER_VIA_THROUGH, COLOR4D( LIGHTGRAY ) },
{ LAYER_WORKSHEET, COLOR4D( DARKRED ) },

6
common/settings/color_settings.cpp
View File

@ -134,12 +134,12 @@ COLOR_SETTINGS::COLOR_SETTINGS( wxString aFilename ) :
CLR( "board.no_connect", LAYER_NO_CONNECTS );
CLR( "board.pad_back", LAYER_PAD_BK );
CLR( "board.pad_front", LAYER_PAD_FR );
CLR( "board.pad_plated_hole", LAYER_PADS_PLATEDHOLES );
CLR( "board.pad_plated_hole", LAYER_PAD_PLATEDHOLES );
CLR( "board.pad_through_hole", LAYER_PADS_TH );
CLR( "board.plated_hole", LAYER_NON_PLATEDHOLES );
CLR( "board.ratsnest", LAYER_RATSNEST );
CLR( "board.via_blind_buried", LAYER_VIA_BBLIND );
CLR( "board.via_hole", LAYER_VIAS_HOLES );
CLR( "board.via_hole", LAYER_VIA_HOLES );
CLR( "board.via_micro", LAYER_VIA_MICROVIA );
CLR( "board.via_through", LAYER_VIA_THROUGH );
CLR( "board.worksheet", LAYER_WORKSHEET );
@ -220,7 +220,7 @@ COLOR_SETTINGS::COLOR_SETTINGS( wxString aFilename ) :
registerMigration( 1, 2,
[&]()
{
// Fix LAYER_VIAS_HOLES color - before version 2, this setting had no effect
// Fix LAYER_VIA_HOLES color - before version 2, this setting had no effect
nlohmann::json::json_pointer ptr( "/board/via_hole");
( *this )[ptr] = COLOR4D( 0.5, 0.4, 0, 0.8 ).ToWxString( wxC2S_CSS_SYNTAX );

3
common/view/view_group.cpp
View File

@ -160,7 +160,8 @@ void VIEW_GROUP::ViewDraw( int aLayer, VIEW* aView ) const
switch( layer )
{
case LAYER_PADS_TH:
case LAYER_PADS_PLATEDHOLES:
case LAYER_PAD_PLATEDHOLES:
case LAYER_PAD_HOLEWALLS:
case LAYER_PAD_FR:
case LAYER_PAD_BK:
draw = true;

8
eeschema/sch_painter.h
View File

@ -138,13 +138,7 @@ public:
/// @copydoc PAINTER::Draw()
virtual bool Draw( const VIEW_ITEM*, int ) override;
/// @copydoc PAINTER::ApplySettings()
virtual void ApplySettings( const RENDER_SETTINGS* aSettings ) override
{
m_schSettings = *static_cast<const SCH_RENDER_SETTINGS*>( aSettings );
}
/// @copydoc PAINTER::GetAdapter()
/// @copydoc PAINTER::GetSettings()
virtual SCH_RENDER_SETTINGS* GetSettings() override
{
return &m_schSettings;

8
gerbview/gerbview_painter.h
View File

@ -169,13 +169,7 @@ class GERBVIEW_PAINTER : public PAINTER
public:
GERBVIEW_PAINTER( GAL* aGal );
/// @copydoc PAINTER::ApplySettings()
virtual void ApplySettings( const RENDER_SETTINGS* aSettings ) override
{
m_gerbviewSettings = *static_cast<const GERBVIEW_RENDER_SETTINGS*>( aSettings );
}
/// @copydoc PAINTER::GetAdapter()
/// @copydoc PAINTER::GetSettings()
virtual GERBVIEW_RENDER_SETTINGS* GetSettings() override
{
return &m_gerbviewSettings;

41
include/layers_id_colors_and_visibility.h
View File

@ -164,8 +164,8 @@ enum NETNAMES_LAYER_ID: int
LAYER_PAD_FR_NETNAMES,
LAYER_PAD_BK_NETNAMES,
LAYER_PADS_NETNAMES,
LAYER_VIAS_NETNAMES,
LAYER_PAD_NETNAMES,
LAYER_VIA_NETNAMES,
NETNAMES_LAYER_ID_END
};
@ -200,8 +200,10 @@ enum GAL_LAYER_ID: int
LAYER_MOD_REFERENCES, ///< show footprints references (when texts are visibles)
LAYER_TRACKS,
LAYER_PADS_TH, ///< multilayer pads, usually with holes
LAYER_PADS_PLATEDHOLES, ///< to draw pad holes (plated)
LAYER_VIAS_HOLES, ///< to draw via holes (pad holes do not use this layer)
LAYER_PAD_PLATEDHOLES, ///< to draw pad holes (plated)
LAYER_PAD_HOLEWALLS,
LAYER_VIA_HOLES, ///< to draw via holes (pad holes do not use this layer)
LAYER_VIA_HOLEWALLS,
LAYER_DRC_ERROR, ///< layer for drc markers with SEVERITY_ERROR
LAYER_DRC_WARNING, ///< layer for drc markers with SEVERITY_WARNING
LAYER_DRC_EXCLUSION, ///< layer for drc markers which have been individually excluded
@ -215,7 +217,6 @@ enum GAL_LAYER_ID: int
LAYER_DRAW_BITMAPS, ///< to handle and draw images bitmaps
/// This is the end of the layers used for visibility bit masks in Pcbnew
/// There can be at most 32 layers above here.
GAL_LAYER_ID_BITMASK_END,
LAYER_WORKSHEET_PAGE1, ///< for pageLayout editor previewing
@ -422,11 +423,13 @@ wxString LayerName( int aLayer );
// from a dialog, but have a visibility control flag.
// Here is a mask to set them visible, to be sure they are displayed
// after loading a board for instance
#define MIN_VISIBILITY_MASK int( ( 1 << GAL_LAYER_INDEX( LAYER_PADS_PLATEDHOLES ) ) +\
( 1 << GAL_LAYER_INDEX( LAYER_VIAS_HOLES ) ) +\
( 1 << GAL_LAYER_INDEX( LAYER_SELECT_OVERLAY ) ) +\
( 1 << GAL_LAYER_INDEX( LAYER_GP_OVERLAY ) ) +\
( 1 << GAL_LAYER_INDEX( LAYER_RATSNEST ) ) )
#define MIN_VISIBILITY_MASK int( ( 1 << GAL_LAYER_INDEX( LAYER_PAD_PLATEDHOLES ) ) +\
( 1 << GAL_LAYER_INDEX( LAYER_PAD_HOLEWALLS ) ) +\
( 1 << GAL_LAYER_INDEX( LAYER_VIA_HOLES ) ) +\
( 1 << GAL_LAYER_INDEX( LAYER_VIA_HOLEWALLS ) ) +\
( 1 << GAL_LAYER_INDEX( LAYER_SELECT_OVERLAY ) ) +\
( 1 << GAL_LAYER_INDEX( LAYER_GP_OVERLAY ) ) +\
( 1 << GAL_LAYER_INDEX( LAYER_RATSNEST ) ) )
/// A sequence of layers, a sequence provides a certain order.
@ -901,13 +904,13 @@ inline int GetNetnameLayer( int aLayer )
if( IsCopperLayer( aLayer ) )
return NETNAMES_LAYER_INDEX( aLayer );
else if( aLayer == LAYER_PADS_TH )
return LAYER_PADS_NETNAMES;
return LAYER_PAD_NETNAMES;
else if( aLayer == LAYER_PAD_FR )
return LAYER_PAD_FR_NETNAMES;
else if( aLayer == LAYER_PAD_BK )
return LAYER_PAD_BK_NETNAMES;
else if( aLayer >= LAYER_VIA_MICROVIA && aLayer <= LAYER_VIA_THROUGH )
return LAYER_VIAS_NETNAMES;
return LAYER_VIA_NETNAMES;
// Fallback
return Cmts_User;
@ -949,12 +952,14 @@ inline bool IsNetCopperLayer( LAYER_NUM aLayer )
{
static std::set<LAYER_NUM> netCopperLayers =
{
LAYER_PAD_FR,
LAYER_PAD_BK,
LAYER_PADS_TH,
LAYER_VIA_THROUGH,
LAYER_VIA_BBLIND,
LAYER_VIA_MICROVIA
LAYER_PAD_FR,
LAYER_PAD_BK,
LAYER_PADS_TH,
LAYER_PAD_HOLEWALLS,
LAYER_VIA_THROUGH,
LAYER_VIA_BBLIND,
LAYER_VIA_MICROVIA,
LAYER_VIA_HOLEWALLS
};
return IsCopperLayer( aLayer ) || netCopperLayers.count( aLayer );

8
include/page_layout/ws_painter.h
View File

@ -107,13 +107,7 @@ public:
void DrawBorder( const PAGE_INFO* aPageInfo, int aScaleFactor ) const;
/// @copydoc PAINTER::ApplySettings()
virtual void ApplySettings( const RENDER_SETTINGS* aSettings ) override
{
m_renderSettings = *static_cast<const WS_RENDER_SETTINGS*>( aSettings );
}
/// @copydoc PAINTER::GetAdapter()
/// @copydoc PAINTER::GetSettings()
virtual RENDER_SETTINGS* GetSettings() override { return &m_renderSettings; }
private:

7
include/painter.h
View File

@ -77,13 +77,6 @@ public:
m_gal = aGal;
}
/**
* Loads colors and display modes settings that are going to be used when drawing items.
*
* @param aSettings are settings to be applied.
*/
virtual void ApplySettings( const RENDER_SETTINGS* aSettings ) = 0;
/**
* Return a pointer to current settings that are going to be used when drawing items.
*

6
pcbnew/dialogs/panel_fp_editor_color_settings.cpp
View File

@ -65,8 +65,10 @@ PANEL_FP_EDITOR_COLOR_SETTINGS::PANEL_FP_EDITOR_COLOR_SETTINGS( FOOTPRINT_EDIT_F
for( int id = GAL_LAYER_ID_START; id < GAL_LAYER_ID_END; id++ )
{
if( id == LAYER_VIAS
|| id == LAYER_PADS_PLATEDHOLES
|| id == LAYER_VIAS_HOLES )
|| id == LAYER_VIA_HOLES
|| id == LAYER_VIA_HOLEWALLS
|| id == LAYER_PAD_PLATEDHOLES
|| id == LAYER_PAD_HOLEWALLS )
{
continue;
}

4
pcbnew/dialogs/panel_pcbnew_color_settings.cpp
View File

@ -354,6 +354,7 @@ std::string g_previewBoard =
std::set<int> g_excludedLayers =
{
LAYER_VIAS,
LAYER_VIA_HOLEWALLS,
LAYER_MOD_FR,
LAYER_MOD_BK,
LAYER_MOD_VALUES,
@ -361,7 +362,8 @@ std::set<int> g_excludedLayers =
LAYER_TRACKS,
LAYER_MOD_TEXT_FR,
LAYER_MOD_TEXT_BK,
LAYER_PADS_PLATEDHOLES,
LAYER_PAD_PLATEDHOLES,
LAYER_PAD_HOLEWALLS,
LAYER_GP_OVERLAY,
LAYER_DRAW_BITMAPS,
LAYER_MARKER_SHADOWS

63
pcbnew/pad.cpp
View File

@ -43,9 +43,13 @@
#include <convert_to_biu.h>
#include <convert_basic_shapes_to_polygon.h>
#include <widgets/msgpanel.h>
#include <pcb_painter.h>
#include <memory>
using KIGFX::PCB_PAINTER;
using KIGFX::PCB_RENDER_SETTINGS;
PAD::PAD( FOOTPRINT* parent ) :
BOARD_CONNECTED_ITEM( parent, PCB_PAD_T )
{
@ -1141,7 +1145,10 @@ void PAD::ViewGetLayers( int aLayers[], int& aCount ) const
// These 2 types of pads contain a hole
if( m_attribute == PAD_ATTRIB_PTH )
aLayers[aCount++] = LAYER_PADS_PLATEDHOLES;
{
aLayers[aCount++] = LAYER_PAD_PLATEDHOLES;
aLayers[aCount++] = LAYER_PAD_HOLEWALLS;
}
if( m_attribute == PAD_ATTRIB_NPTH )
aLayers[aCount++] = LAYER_NON_PLATEDHOLES;
@ -1150,7 +1157,7 @@ void PAD::ViewGetLayers( int aLayers[], int& aCount ) const
{
// Multi layer pad
aLayers[aCount++] = LAYER_PADS_TH;
aLayers[aCount++] = LAYER_PADS_NETNAMES;
aLayers[aCount++] = LAYER_PAD_NETNAMES;
}
else if( IsOnLayer( F_Cu ) )
{
@ -1159,7 +1166,7 @@ void PAD::ViewGetLayers( int aLayers[], int& aCount ) const
// Is this a PTH pad that has only front copper? If so, we need to also display the
// net name on the PTH netname layer so that it isn't blocked by the drill hole.
if( m_attribute == PAD_ATTRIB_PTH )
aLayers[aCount++] = LAYER_PADS_NETNAMES;
aLayers[aCount++] = LAYER_PAD_NETNAMES;
else
aLayers[aCount++] = LAYER_PAD_FR_NETNAMES;
}
@ -1170,7 +1177,7 @@ void PAD::ViewGetLayers( int aLayers[], int& aCount ) const
// Is this a PTH pad that has only back copper? If so, we need to also display the
// net name on the PTH netname layer so that it isn't blocked by the drill hole.
if( m_attribute == PAD_ATTRIB_PTH )
aLayers[aCount++] = LAYER_PADS_NETNAMES;
aLayers[aCount++] = LAYER_PAD_NETNAMES;
else
aLayers[aCount++] = LAYER_PAD_BK_NETNAMES;
}
@ -1211,12 +1218,23 @@ void PAD::ViewGetLayers( int aLayers[], int& aCount ) const
double PAD::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
{
constexpr double HIDE = std::numeric_limits<double>::max();
PCB_PAINTER* painter = static_cast<PCB_PAINTER*>( aView->GetPainter() );
PCB_RENDER_SETTINGS* renderSettings = painter->GetSettings();
BOARD* board = GetBoard();
if( board && aLayer == LAYER_PADS_TH )
{
LSET visible = board->GetVisibleLayers() & board->GetEnabledLayers();
if( !FlashLayer( visible ) )
return HIDE;
}
if( aView->GetPrintMode() > 0 ) // In printing mode the pad is always drawable
return 0.0;
constexpr double HIDE = std::numeric_limits<double>::max();
BOARD* board = GetBoard();
// Meta control for hiding all pads
if( !aView->IsLayerVisible( LAYER_PADS ) )
return HIDE;
@ -1224,7 +1242,9 @@ double PAD::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
// Handle Render tab switches
if( ( GetAttribute() == PAD_ATTRIB_PTH || GetAttribute() == PAD_ATTRIB_NPTH )
&& !aView->IsLayerVisible( LAYER_PADS_TH ) )
{
return HIDE;
}
if( !IsFlipped() && !aView->IsLayerVisible( LAYER_MOD_FR ) )
return HIDE;
@ -1238,18 +1258,16 @@ double PAD::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
if( IsBackLayer( (PCB_LAYER_ID) aLayer ) && !aView->IsLayerVisible( LAYER_PAD_BK ) )
return HIDE;
if( board )
{
LSET visible = board->GetVisibleLayers() & board->GetEnabledLayers();
// Don't draw the copper ring of a PTH if none of the copper layers are visible
if( aLayer == LAYER_PADS_TH && ( LSET::AllCuMask() & GetLayerSet() & visible ).none() )
return HIDE;
}
// Netnames will be shown only if zoom is appropriate
if( IsNetnameLayer( aLayer ) )
{
// Hide netnames unless pad is flashed to a high-contrast layer
if( renderSettings->GetHighContrast() )
{
if( !FlashLayer( renderSettings->GetPrimaryHighContrastLayer() ) )
return HIDE;
}
// Netnames will be shown only if zoom is appropriate
int divisor = std::min( GetBoundingBox().GetWidth(), GetBoundingBox().GetHeight() );
// Pad sizes can be zero briefly when someone is typing a number like "0.5"
@ -1260,7 +1278,16 @@ double PAD::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
return ( double ) Millimeter2iu( 5 ) / divisor;
}
// Other layers are shown without any conditions
if( aLayer == LAYER_PADS_TH
&& GetShape() != PAD_SHAPE_CUSTOM
&& GetSizeX() <= GetDrillSizeX()
&& GetSizeY() <= GetDrillSizeY() )
{
// Don't tweak the drawing code with a degenerate pad
return HIDE;
}
// Passed all tests; show.
return 0.0;
}

64
pcbnew/pcb_draw_panel_gal.cpp
View File

@ -56,22 +56,31 @@ const LAYER_NUM GAL_LAYER_ORDER[] =
LAYER_GP_OVERLAY,
LAYER_SELECT_OVERLAY,
LAYER_DRC_ERROR, LAYER_DRC_WARNING, LAYER_DRC_EXCLUSION, LAYER_MARKER_SHADOWS,
LAYER_PADS_NETNAMES, LAYER_VIAS_NETNAMES,
Dwgs_User, Cmts_User, Eco1_User, Eco2_User, Edge_Cuts,
LAYER_PAD_NETNAMES, LAYER_VIA_NETNAMES,
Dwgs_User,
Cmts_User,
Eco1_User, Eco2_User,
Edge_Cuts,
User_1, ZONE_LAYER_FOR( User_1 ), User_2, ZONE_LAYER_FOR( User_2 ),
User_3, ZONE_LAYER_FOR( User_3 ), User_4, ZONE_LAYER_FOR( User_4 ),
User_5, ZONE_LAYER_FOR( User_5 ), User_6, ZONE_LAYER_FOR( User_6 ),
User_7, ZONE_LAYER_FOR( User_7 ), User_8, ZONE_LAYER_FOR( User_8 ),
User_1, ZONE_LAYER_FOR( User_1 ),
User_2, ZONE_LAYER_FOR( User_2 ),
User_3, ZONE_LAYER_FOR( User_3 ),
User_4, ZONE_LAYER_FOR( User_4 ),
User_5, ZONE_LAYER_FOR( User_5 ),
User_6, ZONE_LAYER_FOR( User_6 ),
User_7, ZONE_LAYER_FOR( User_7 ),
User_8, ZONE_LAYER_FOR( User_8 ),
User_9, ZONE_LAYER_FOR( User_9 ),
LAYER_MOD_TEXT_FR,
LAYER_MOD_REFERENCES, LAYER_MOD_VALUES,
LAYER_RATSNEST, LAYER_ANCHOR,
LAYER_VIAS_HOLES, LAYER_PADS_PLATEDHOLES, LAYER_NON_PLATEDHOLES,
LAYER_VIA_THROUGH, LAYER_VIA_BBLIND,
LAYER_VIA_MICROVIA, LAYER_PADS_TH,
LAYER_RATSNEST,
LAYER_ANCHOR,
LAYER_VIA_HOLES, LAYER_VIA_HOLEWALLS,
LAYER_PAD_PLATEDHOLES, LAYER_PAD_HOLEWALLS, LAYER_NON_PLATEDHOLES,
LAYER_VIA_THROUGH, LAYER_VIA_BBLIND, LAYER_VIA_MICROVIA,
LAYER_PADS_TH,
LAYER_PAD_FR_NETNAMES, LAYER_PAD_FR,
NETNAMES_LAYER_INDEX( F_Cu ), F_Cu, ZONE_LAYER_FOR( F_Cu ),
@ -277,11 +286,11 @@ void PCB_DRAW_PANEL_GAL::SetHighContrastLayer( PCB_LAYER_ID aLayer )
// fixme do not like the idea of storing the list of layers here,
// should be done in some other way I guess..
LAYER_NUM layers[] = {
GetNetnameLayer( aLayer ), LAYER_VIAS_NETNAMES,
LAYER_PAD_FR_NETNAMES, LAYER_PAD_BK_NETNAMES, LAYER_PADS_NETNAMES,
GetNetnameLayer( aLayer ), LAYER_VIA_NETNAMES,
LAYER_PAD_FR_NETNAMES, LAYER_PAD_BK_NETNAMES, LAYER_PAD_NETNAMES,
ZONE_LAYER_FOR( aLayer ),
LAYER_PADS_TH, LAYER_PADS_PLATEDHOLES, LAYER_NON_PLATEDHOLES,
LAYER_VIA_THROUGH, LAYER_VIA_BBLIND, LAYER_VIA_MICROVIA, LAYER_VIAS_HOLES,
LAYER_PADS_TH, LAYER_PAD_PLATEDHOLES, LAYER_PAD_HOLEWALLS, LAYER_NON_PLATEDHOLES,
LAYER_VIA_THROUGH, LAYER_VIA_BBLIND, LAYER_VIA_MICROVIA, LAYER_VIA_HOLES, LAYER_VIA_HOLEWALLS,
LAYER_DRC_ERROR, LAYER_DRC_WARNING, LAYER_DRC_EXCLUSION, LAYER_MARKER_SHADOWS,
LAYER_SELECT_OVERLAY, LAYER_GP_OVERLAY,
LAYER_RATSNEST, LAYER_CURSOR, LAYER_ANCHOR
@ -315,9 +324,10 @@ void PCB_DRAW_PANEL_GAL::SetTopLayer( PCB_LAYER_ID aLayer )
// Layers that should always have on-top attribute enabled
const std::vector<LAYER_NUM> layers = {
LAYER_VIA_THROUGH, LAYER_VIA_BBLIND, LAYER_VIA_MICROVIA, LAYER_VIAS_HOLES,
LAYER_VIAS_NETNAMES,
LAYER_PADS_TH, LAYER_PADS_PLATEDHOLES, LAYER_PADS_NETNAMES, LAYER_NON_PLATEDHOLES,
LAYER_VIA_THROUGH, LAYER_VIA_BBLIND, LAYER_VIA_MICROVIA, LAYER_VIA_HOLES, LAYER_VIA_HOLEWALLS,
LAYER_VIA_NETNAMES,
LAYER_PADS_TH, LAYER_PAD_PLATEDHOLES, LAYER_PAD_HOLEWALLS, LAYER_NON_PLATEDHOLES,
LAYER_PAD_NETNAMES,
LAYER_SELECT_OVERLAY, LAYER_GP_OVERLAY,
LAYER_RATSNEST,
LAYER_DRC_ERROR, LAYER_DRC_WARNING, LAYER_DRC_EXCLUSION, LAYER_MARKER_SHADOWS
@ -364,9 +374,9 @@ void PCB_DRAW_PANEL_GAL::SetTopLayer( PCB_LAYER_ID aLayer )
// Fix up pad and via netnames to be below. This is hacky, we need a rethink
// of layer ordering...
m_view->SetLayerOrder( LAYER_PADS_NETNAMES,
m_view->SetLayerOrder( LAYER_PAD_NETNAMES,
m_view->GetLayerOrder( LAYER_MARKER_SHADOWS ) + 3 );
m_view->SetLayerOrder( LAYER_VIAS_NETNAMES,
m_view->SetLayerOrder( LAYER_VIA_NETNAMES,
m_view->GetLayerOrder( LAYER_MARKER_SHADOWS ) + 4 );
}
}
@ -412,8 +422,10 @@ void PCB_DRAW_PANEL_GAL::SyncLayersVisibility( const BOARD* aBoard )
m_view->SetLayerVisible( i, true );
// Enable some layers that are GAL specific
m_view->SetLayerVisible( LAYER_PADS_PLATEDHOLES, true );
m_view->SetLayerVisible( LAYER_VIAS_HOLES, true );
m_view->SetLayerVisible( LAYER_PAD_PLATEDHOLES, true );
m_view->SetLayerVisible( LAYER_PAD_HOLEWALLS, true );
m_view->SetLayerVisible( LAYER_VIA_HOLES, true );
m_view->SetLayerVisible( LAYER_VIA_HOLEWALLS, true );
m_view->SetLayerVisible( LAYER_GP_OVERLAY, true );
m_view->SetLayerVisible( LAYER_SELECT_OVERLAY, true );
m_view->SetLayerVisible( LAYER_RATSNEST, true );
@ -559,12 +571,14 @@ void PCB_DRAW_PANEL_GAL::setDefaultLayerDeps()
m_view->SetLayerDisplayOnly( LAYER_ANCHOR );
// Some more required layers settings
m_view->SetRequired( LAYER_VIAS_NETNAMES, LAYER_VIAS );
m_view->SetRequired( LAYER_PADS_NETNAMES, LAYER_PADS );
m_view->SetRequired( LAYER_VIA_NETNAMES, LAYER_VIAS );
m_view->SetRequired( LAYER_PAD_NETNAMES, LAYER_PADS );
// Holes can be independent of their host objects (cf: printing drill marks)
m_view->SetRequired( LAYER_VIAS_HOLES, LAYER_VIAS );
m_view->SetRequired( LAYER_PADS_PLATEDHOLES, LAYER_PADS );
m_view->SetRequired( LAYER_VIA_HOLES, LAYER_VIAS );
m_view->SetRequired( LAYER_VIA_HOLEWALLS, LAYER_VIAS );
m_view->SetRequired( LAYER_PAD_PLATEDHOLES, LAYER_PADS );
m_view->SetRequired( LAYER_PAD_HOLEWALLS, LAYER_PADS );
m_view->SetRequired( LAYER_NON_PLATEDHOLES, LAYER_PADS );
// Via visibility

48
pcbnew/pcb_edit_frame.cpp
View File

@ -977,33 +977,21 @@ void PCB_EDIT_FRAME::SetActiveLayer( PCB_LAYER_ID aLayer )
GetCanvas()->SetFocus(); // allow capture of hotkeys
GetCanvas()->SetHighContrastLayer( aLayer );
// Pads and vias on a restricted layer set must be redrawn when the active layer is changed
GetCanvas()->GetView()->UpdateAllItemsConditionally( KIGFX::REPAINT,
[]( KIGFX::VIEW_ITEM* aItem ) -> bool
[&]( KIGFX::VIEW_ITEM* aItem ) -> bool
{
if( VIA* via = dynamic_cast<VIA*>( aItem ) )
{
// Vias on a restricted layer set must be redrawn when the active layer
// is changed
return ( via->GetViaType() == VIATYPE::BLIND_BURIED ||
via->GetViaType() == VIATYPE::MICROVIA );
}
else if( PAD* pad = dynamic_cast<PAD*>( aItem ) )
{
// TODO: this could be optimized if the pad painter is changed
// See https://gitlab.com/kicad/code/kicad/-/issues/6912
return !!pad;
}
return false;
} );
// Clearances could be layer-dependent so redraw them when the active layer is changed
if( GetDisplayOptions().m_DisplayPadIsol )
{
GetCanvas()->GetView()->UpdateAllItemsConditionally( KIGFX::REPAINT,
[&]( KIGFX::VIEW_ITEM* aItem ) -> bool
{
if( PAD* pad = dynamic_cast<PAD*>( aItem ) )
// Clearances could be layer-dependent so redraw them when the active layer
// is changed
if( GetDisplayOptions().m_DisplayPadIsol )
{
// Round-corner rects are expensive to draw, but are mostly found on
// SMD pads which only need redrawing on an active-to-not-active
@ -1019,26 +1007,20 @@ void PCB_EDIT_FRAME::SetActiveLayer( PCB_LAYER_ID aLayer )
return true;
}
return false;
} );
}
if( GetDisplayOptions().m_ShowTrackClearanceMode )
{
GetCanvas()->GetView()->UpdateAllItemsConditionally( KIGFX::REPAINT,
[&]( KIGFX::VIEW_ITEM* aItem ) -> bool
}
else if( TRACK* track = dynamic_cast<TRACK*>( aItem ) )
{
if( TRACK* track = dynamic_cast<TRACK*>( aItem ) )
// Clearances could be layer-dependent so redraw them when the active layer
// is changed
if( GetDisplayOptions().m_ShowTrackClearanceMode )
{
// Tracks aren't particularly expensive to draw, but it's an easy
// check.
// Tracks aren't particularly expensive to draw, but it's an easy check.
return track->IsOnLayer( oldLayer ) || track->IsOnLayer( aLayer );
}
}
return false;
} );
}
return false;
} );
GetCanvas()->Refresh();
}

381
pcbnew/pcb_painter.cpp
View File

@ -105,11 +105,11 @@ void PCB_RENDER_SETTINGS::LoadColors( const COLOR_SETTINGS* aSettings )
m_layerColors[i] = aSettings->GetColor( i );
// Default colors for specific layers (not really board layers).
m_layerColors[LAYER_PADS_PLATEDHOLES] = aSettings->GetColor( LAYER_PCB_BACKGROUND );
m_layerColors[LAYER_VIAS_NETNAMES] = COLOR4D( 0.2, 0.2, 0.2, 0.9 );
m_layerColors[LAYER_PADS_NETNAMES] = COLOR4D( 1.0, 1.0, 1.0, 0.9 );
m_layerColors[LAYER_PAD_FR_NETNAMES] = COLOR4D( 1.0, 1.0, 1.0, 0.9 );
m_layerColors[LAYER_PAD_BK_NETNAMES] = COLOR4D( 1.0, 1.0, 1.0, 0.9 );
m_layerColors[LAYER_PAD_PLATEDHOLES] = aSettings->GetColor( LAYER_PCB_BACKGROUND );
m_layerColors[LAYER_VIA_NETNAMES] = COLOR4D( 0.2, 0.2, 0.2, 0.9 );
m_layerColors[LAYER_PAD_NETNAMES] = COLOR4D( 1.0, 1.0, 1.0, 0.9 );
m_layerColors[LAYER_PAD_FR_NETNAMES] = COLOR4D( 1.0, 1.0, 1.0, 0.9 );
m_layerColors[LAYER_PAD_BK_NETNAMES] = COLOR4D( 1.0, 1.0, 1.0, 0.9 );
// LAYER_PADS_TH, LAYER_NON_PLATEDHOLES, LAYER_ANCHOR ,LAYER_RATSNEST,
// LAYER_VIA_THROUGH, LAYER_VIA_BBLIND, LAYER_VIA_MICROVIA
@ -224,20 +224,18 @@ void PCB_RENDER_SETTINGS::LoadDisplayOptions( const PCB_DISPLAY_OPTIONS& aOption
COLOR4D PCB_RENDER_SETTINGS::GetColor( const VIEW_ITEM* aItem, int aLayer ) const
{
int netCode = -1;
const EDA_ITEM* item = dynamic_cast<const EDA_ITEM*>( aItem );
const EDA_ITEM* item = dynamic_cast<const EDA_ITEM*>( aItem );
const BOARD_CONNECTED_ITEM* conItem = dynamic_cast<const BOARD_CONNECTED_ITEM*> ( aItem );
int netCode = -1;
int originalLayer = aLayer;
// Marker shadows
if( aLayer == LAYER_MARKER_SHADOWS )
return m_backgroundColor.WithAlpha( 0.6 );
if( !item )
return m_layerColors[aLayer];
if( aLayer == LAYER_PADS_PLATEDHOLES
if( aLayer == LAYER_PAD_PLATEDHOLES
|| aLayer == LAYER_NON_PLATEDHOLES
|| aLayer == LAYER_VIAS_HOLES )
|| aLayer == LAYER_VIA_HOLES )
{
// Careful that we don't end up with the same colour for the annular ring and the hole
// when printing in B&W.
@ -263,9 +261,18 @@ COLOR4D PCB_RENDER_SETTINGS::GetColor( const VIEW_ITEM* aItem, int aLayer ) cons
if( item && item->Type() == PCB_ZONE_T && IsZoneLayer( aLayer ) )
aLayer = aLayer - LAYER_ZONE_START;
// Hole walls should pull from the copper layer
if( aLayer == LAYER_PAD_HOLEWALLS )
aLayer = LAYER_PADS_TH;
else if( aLayer == LAYER_VIA_HOLEWALLS )
aLayer = LAYER_VIA_THROUGH;
// Normal path: get the layer base color
COLOR4D color = m_layerColors[aLayer];
if( !item )
return m_layerColors[aLayer];
// Selection disambiguation
if( item->IsBrightened() )
return color.Brightened( m_selectFactor ).WithAlpha( 0.8 );
@ -331,18 +338,16 @@ COLOR4D PCB_RENDER_SETTINGS::GetColor( const VIEW_ITEM* aItem, int aLayer ) cons
PCB_LAYER_ID primary = GetPrimaryHighContrastLayer();
bool isActive = m_highContrastLayers.count( aLayer );
// Track annotations are drawn on synthetic layers, but we only want them drawn if the
// track itself is on the primary layer.
if( item->Type() == PCB_TRACE_T || item->Type() == PCB_ARC_T )
{
if( !static_cast<const TRACK*>( item )->IsOnLayer( primary ) )
isActive = false;
}
else if( item->Type() == PCB_PAD_T )
if( originalLayer == LAYER_PADS_TH )
{
if( !static_cast<const PAD*>( item )->FlashLayer( primary ) )
isActive = false;
}
else if( originalLayer == LAYER_VIA_THROUGH )
{
if( !static_cast<const VIA*>( item )->FlashLayer( primary ) )
isActive = false;
}
if( !isActive )
{
@ -488,51 +493,55 @@ void PCB_PAINTER::draw( const TRACK* aTrack, int aLayer )
VECTOR2D start( aTrack->GetStart() );
VECTOR2D end( aTrack->GetEnd() );
int width = aTrack->GetWidth();
COLOR4D color = m_pcbSettings.GetColor( aTrack, aLayer );
if( m_pcbSettings.m_netNamesOnTracks && IsNetnameLayer( aLayer ) )
if( IsNetnameLayer( aLayer ) )
{
// If there is a net name - display it on the track
if( aTrack->GetNetCode() > NETINFO_LIST::UNCONNECTED )
{
VECTOR2D line = ( end - start );
double length = line.EuclideanNorm();
if( !m_pcbSettings.m_netNamesOnTracks )
return;
// Check if the track is long enough to have a netname displayed
if( length < 10 * width )
return;
if( aTrack->GetNetCode() <= NETINFO_LIST::UNCONNECTED )
return;
const wxString& netName = UnescapeString( aTrack->GetShortNetname() );
VECTOR2D textPosition = start + line / 2.0; // center of the track
VECTOR2D line = ( end - start );
double length = line.EuclideanNorm();
double textOrientation;
// Check if the track is long enough to have a netname displayed
if( length < 10 * width )
return;
if( end.y == start.y ) // horizontal
textOrientation = 0;
else if( end.x == start.x ) // vertical
textOrientation = M_PI / 2;
else
textOrientation = -atan( line.y / line.x );
const wxString& netName = UnescapeString( aTrack->GetShortNetname() );
VECTOR2D textPosition = start + line / 2.0; // center of the track
double textSize = width;
double textOrientation;
m_gal->SetIsStroke( true );
m_gal->SetIsFill( false );
m_gal->SetStrokeColor( m_pcbSettings.GetColor( aTrack, aLayer ) );
m_gal->SetLineWidth( width / 10.0 );
m_gal->SetFontBold( false );
m_gal->SetFontItalic( false );
m_gal->SetFontUnderlined( false );
m_gal->SetTextMirrored( false );
m_gal->SetGlyphSize( VECTOR2D( textSize * 0.7, textSize * 0.7 ) );
m_gal->SetHorizontalJustify( GR_TEXT_HJUSTIFY_CENTER );
m_gal->SetVerticalJustify( GR_TEXT_VJUSTIFY_CENTER );
m_gal->BitmapText( netName, textPosition, textOrientation );
}
if( end.y == start.y ) // horizontal
textOrientation = 0;
else if( end.x == start.x ) // vertical
textOrientation = M_PI / 2;
else
textOrientation = -atan( line.y / line.x );
double textSize = width;
m_gal->SetIsStroke( true );
m_gal->SetIsFill( false );
m_gal->SetStrokeColor( color );
m_gal->SetLineWidth( width / 10.0 );
m_gal->SetFontBold( false );
m_gal->SetFontItalic( false );
m_gal->SetFontUnderlined( false );
m_gal->SetTextMirrored( false );
m_gal->SetGlyphSize( VECTOR2D( textSize * 0.7, textSize * 0.7 ) );
m_gal->SetHorizontalJustify( GR_TEXT_HJUSTIFY_CENTER );
m_gal->SetVerticalJustify( GR_TEXT_VJUSTIFY_CENTER );
m_gal->BitmapText( netName, textPosition, textOrientation );
return;
}
else if( IsCopperLayer( aLayer ) )
{
// Draw a regular track
COLOR4D color = m_pcbSettings.GetColor( aTrack, aLayer );
bool outline_mode = m_pcbSettings.m_sketchMode[LAYER_TRACKS];
m_gal->SetStrokeColor( color );
m_gal->SetFillColor( color );
@ -541,20 +550,21 @@ void PCB_PAINTER::draw( const TRACK* aTrack, int aLayer )
m_gal->SetLineWidth( m_pcbSettings.m_outlineWidth );
m_gal->DrawSegment( start, end, width );
}
// Clearance lines
constexpr int clearanceFlags = PCB_RENDER_SETTINGS::CL_EXISTING | PCB_RENDER_SETTINGS::CL_TRACKS;
// Clearance lines
constexpr int clearanceFlags = PCB_RENDER_SETTINGS::CL_EXISTING
| PCB_RENDER_SETTINGS::CL_TRACKS;
if( ( m_pcbSettings.m_clearanceDisplayFlags & clearanceFlags ) == clearanceFlags )
{
int clearance = aTrack->GetOwnClearance( m_pcbSettings.GetActiveLayer() );
if( ( m_pcbSettings.m_clearanceDisplayFlags & clearanceFlags ) == clearanceFlags )
{
int clearance = aTrack->GetOwnClearance( m_pcbSettings.GetActiveLayer() );
m_gal->SetLineWidth( m_pcbSettings.m_outlineWidth );
m_gal->SetIsFill( false );
m_gal->SetIsStroke( true );
m_gal->SetStrokeColor( color );
m_gal->DrawSegment( start, end, width + clearance * 2 );
}
m_gal->SetLineWidth( m_pcbSettings.m_outlineWidth );
m_gal->SetIsFill( false );
m_gal->SetIsStroke( true );
m_gal->SetStrokeColor( color );
m_gal->DrawSegment( start, end, width + clearance * 2 );
}
}
@ -563,11 +573,19 @@ void PCB_PAINTER::draw( const ARC* aArc, int aLayer )
{
VECTOR2D center( aArc->GetCenter() );
int width = aArc->GetWidth();
COLOR4D color = m_pcbSettings.GetColor( aArc, aLayer );
double radius = aArc->GetRadius();
double start_angle = DECIDEG2RAD( aArc->GetArcAngleStart() );
double angle = DECIDEG2RAD( aArc->GetAngle() );
if( IsCopperLayer( aLayer ) )
if( IsNetnameLayer( aLayer ) )
{
// Ummm, yeah. Anyone fancy implementing text on a path?
return;
}
else if( IsCopperLayer( aLayer ) )
{
// Draw a regular track
COLOR4D color = m_pcbSettings.GetColor( aArc, aLayer );
bool outline_mode = m_pcbSettings.m_sketchMode[LAYER_TRACKS];
m_gal->SetStrokeColor( color );
m_gal->SetFillColor( color );
@ -575,35 +593,37 @@ void PCB_PAINTER::draw( const ARC* aArc, int aLayer )
m_gal->SetIsFill( not outline_mode );
m_gal->SetLineWidth( m_pcbSettings.m_outlineWidth );
auto radius = aArc->GetRadius();
auto start_angle = DECIDEG2RAD( aArc->GetArcAngleStart() );
auto angle = DECIDEG2RAD( aArc->GetAngle() );
m_gal->DrawArcSegment( center, radius, start_angle, start_angle + angle, width );
}
// Clearance lines
constexpr int clearanceFlags = PCB_RENDER_SETTINGS::CL_EXISTING | PCB_RENDER_SETTINGS::CL_TRACKS;
// Clearance lines
constexpr int clearanceFlags = PCB_RENDER_SETTINGS::CL_EXISTING
| PCB_RENDER_SETTINGS::CL_TRACKS;
if( ( m_pcbSettings.m_clearanceDisplayFlags & clearanceFlags ) == clearanceFlags )
{
int clearance = aArc->GetOwnClearance( m_pcbSettings.GetActiveLayer() );
if( ( m_pcbSettings.m_clearanceDisplayFlags & clearanceFlags ) == clearanceFlags )
{
int clearance = aArc->GetOwnClearance( m_pcbSettings.GetActiveLayer() );
m_gal->SetLineWidth( m_pcbSettings.m_outlineWidth );
m_gal->SetIsFill( false );
m_gal->SetIsStroke( true );
m_gal->SetStrokeColor( color );
m_gal->SetLineWidth( m_pcbSettings.m_outlineWidth );
m_gal->SetIsFill( false );
m_gal->SetIsStroke( true );
m_gal->SetStrokeColor( color );
m_gal->DrawArcSegment( center, radius, start_angle, start_angle + angle,
width + clearance * 2 );
}
m_gal->DrawArcSegment( center, radius, start_angle, start_angle + angle,
width + clearance * 2 );
}
}
void PCB_PAINTER::draw( const VIA* aVia, int aLayer )
{
VECTOR2D center( aVia->GetStart() );
double radius = 0.0;
BOARD* board = aVia->GetBoard();
BOARD_DESIGN_SETTINGS& bds = board->GetDesignSettings();
COLOR4D color = m_pcbSettings.GetColor( aVia, aLayer );
VECTOR2D center( aVia->GetStart() );
if( color == COLOR4D::CLEAR )
return;
// Draw description layer
if( IsNetnameLayer( aLayer ) )
@ -614,26 +634,6 @@ void PCB_PAINTER::draw( const VIA* aVia, int aLayer )
if( !m_pcbSettings.m_netNamesOnVias || aVia->GetNetname().empty() )
return;
// We won't get CLEAR from GetColor below for a non-through via on an inactive layer in
// high contrast mode because LAYER_VIAS_NETNAMES will always be part of the high-contrast
// set. So we do another check here to prevent drawing netnames for these vias.
if( m_pcbSettings.GetHighContrast() )
{
bool draw = false;
for( unsigned int layer : m_pcbSettings.GetHighContrastLayers() )
{
if( aVia->FlashLayer( static_cast<PCB_LAYER_ID>( layer ) ) )
{
draw = true;
break;
}
}
if( !draw )
return;
}
double maxSize = PCB_RENDER_SETTINGS::MAX_FONT_SIZE;
double size = aVia->GetWidth();
@ -667,28 +667,21 @@ void PCB_PAINTER::draw( const VIA* aVia, int aLayer )
return;
}
else if( aLayer == LAYER_VIAS_HOLES )
{
radius = getDrillSize( aVia ) / 2.0;
}
else if( ( aLayer == LAYER_VIA_THROUGH && aVia->GetViaType() == VIATYPE::THROUGH )
|| ( aLayer == LAYER_VIA_BBLIND && aVia->GetViaType() == VIATYPE::BLIND_BURIED )
|| ( aLayer == LAYER_VIA_MICROVIA && aVia->GetViaType() == VIATYPE::MICROVIA ) )
{
radius = aVia->GetWidth() / 2.0;
}
else
else if( aLayer == LAYER_VIA_HOLEWALLS )
{
int platingThickness = bds.GetHolePlatingThickness();
m_gal->SetIsFill( false );
m_gal->SetIsStroke( true );
m_gal->SetStrokeColor( color );
m_gal->SetLineWidth( platingThickness );
m_gal->DrawCircle( center, ( getDrillSize( aVia ) + platingThickness ) / 2.0 );
return;
}
bool sketchMode = false;
BOARD* board = aVia->GetBoard();
BOARD_DESIGN_SETTINGS& bds = board->GetDesignSettings();
COLOR4D color = m_pcbSettings.GetColor( aVia, aLayer );
if( color == COLOR4D::CLEAR )
return;
bool sketchMode = false;
switch( aVia->GetViaType() )
{
@ -698,33 +691,39 @@ void PCB_PAINTER::draw( const VIA* aVia, int aLayer )
default: wxASSERT( false ); break;
}
m_gal->SetIsFill( !sketchMode );
m_gal->SetIsStroke( sketchMode );
if( sketchMode )
{
// Outline mode
m_gal->SetIsStroke( true );
m_gal->SetIsFill( false );
m_gal->SetLineWidth( m_pcbSettings.m_outlineWidth );
m_gal->SetStrokeColor( color );
}
else
{
// Filled mode
m_gal->SetIsFill( true );
m_gal->SetIsStroke( false );
m_gal->SetFillColor( color );
}
if( aLayer == LAYER_VIAS_HOLES )
if( aLayer == LAYER_VIA_HOLES )
{
m_gal->DrawCircle( center, radius );
m_gal->DrawCircle( center, getDrillSize( aVia ) / 2.0 );
}
else if( ( aVia->GetViaType() == VIATYPE::BLIND_BURIED || aVia->GetViaType() == VIATYPE::MICROVIA )
&& !m_pcbSettings.GetDrawIndividualViaLayers() )
else if( aLayer == LAYER_VIA_THROUGH || m_pcbSettings.GetDrawIndividualViaLayers() )
{
m_gal->DrawCircle( center, aVia->GetWidth() / 2.0 );
}
else if( aLayer == LAYER_VIA_BBLIND || aLayer == LAYER_VIA_MICROVIA )
{
// Outer circles of blind/buried and micro-vias are drawn in a special way to indicate the
// top and bottom layers
PCB_LAYER_ID layerTop, layerBottom;
aVia->LayerPair( &layerTop, &layerBottom );
double radius = aVia->GetWidth() / 2.0;
if( !sketchMode )
m_gal->SetLineWidth( ( aVia->GetWidth() - aVia->GetDrillValue() ) / 2.0 );
@ -745,48 +744,20 @@ void PCB_PAINTER::draw( const VIA* aVia, int aLayer )
m_gal->DrawArc( center, radius, M_PI, 3.0 * M_PI / 2.0 );
}
else
{
bool drawHoleWallOnly = false;
if( m_pcbSettings.m_hiContrastEnabled && !aVia->IsSelected() )
{
if( !aVia->FlashLayer( m_pcbSettings.GetPrimaryHighContrastLayer() ) )
drawHoleWallOnly = true;
}
else
{
LSET visible = board->GetVisibleLayers() & board->GetEnabledLayers();
if( !aVia->FlashLayer( visible ) )
drawHoleWallOnly = true;
}
if( drawHoleWallOnly )
{
m_gal->SetIsFill( false );
m_gal->SetIsStroke( true );
m_gal->SetStrokeColor( color );
m_gal->SetLineWidth( bds.GetHolePlatingThickness() * 2 );
radius = getDrillSize( aVia ) / 2.0 ;
}
m_gal->DrawCircle( center, radius );
}
// Clearance lines
constexpr int clearanceFlags = PCB_RENDER_SETTINGS::CL_EXISTING | PCB_RENDER_SETTINGS::CL_VIAS;
if( ( m_pcbSettings.m_clearanceDisplayFlags & clearanceFlags ) == clearanceFlags
&& aLayer != LAYER_VIAS_HOLES )
&& aLayer != LAYER_VIA_HOLES )
{
PCB_LAYER_ID activeLayer = m_pcbSettings.GetActiveLayer();
double radius;
if( !aVia->FlashLayer( activeLayer ) )
{
radius = getDrillSize( aVia ) / 2.0 +
aVia->GetBoard()->GetDesignSettings().GetHolePlatingThickness();
}
if( aVia->FlashLayer( activeLayer ) )
radius = aVia->GetWidth() / 2.0;
else
radius = getDrillSize( aVia ) / 2.0 + bds.GetHolePlatingThickness();
m_gal->SetLineWidth( m_pcbSettings.m_outlineWidth );
m_gal->SetIsFill( false );
@ -805,7 +776,10 @@ bool isImplicitNet( const wxString& aNetName )
void PCB_PAINTER::draw( const PAD* aPad, int aLayer )
{
// Draw description layer
BOARD* board = aPad->GetBoard();
BOARD_DESIGN_SETTINGS& bds = board->GetDesignSettings();
COLOR4D color = m_pcbSettings.GetColor( aPad, aLayer );
if( IsNetnameLayer( aLayer ) )
{
// Is anything that we can display enabled?
@ -911,11 +885,25 @@ void PCB_PAINTER::draw( const PAD* aPad, int aLayer )
}
return;
}
else if( aLayer == LAYER_PAD_HOLEWALLS )
{
int platingThickness = bds.GetHolePlatingThickness();
// Pad drawing
BOARD* board = aPad->GetBoard();
BOARD_DESIGN_SETTINGS& bds = board->GetDesignSettings();
COLOR4D color = m_pcbSettings.GetColor( aPad, aLayer );
m_gal->SetIsFill( false );
m_gal->SetIsStroke( true );
m_gal->SetLineWidth( platingThickness );
m_gal->SetStrokeColor( color );
const SHAPE_SEGMENT* seg = aPad->GetEffectiveHoleShape();
int holeSize = seg->GetWidth() + platingThickness;
if( seg->GetSeg().A == seg->GetSeg().B ) // Circular hole
m_gal->DrawCircle( seg->GetSeg().A, holeSize / 2 );
else
m_gal->DrawSegment( seg->GetSeg().A, seg->GetSeg().B, holeSize );
return;
}
if( m_pcbSettings.m_sketchMode[LAYER_PADS_TH] )
{
@ -933,34 +921,8 @@ void PCB_PAINTER::draw( const PAD* aPad, int aLayer )
m_gal->SetFillColor( color );
}
auto drawHoleWallCylinder =
[&]( const PAD* aPad )
{
if( aPad->GetAttribute() != PAD_ATTRIB_PTH )
return false;
if( m_pcbSettings.m_hiContrastEnabled && !aPad->IsSelected() )
{
if( !aPad->FlashLayer( m_pcbSettings.GetPrimaryHighContrastLayer() ) )
return true;
}
else
{
LSET visible = board->GetVisibleLayers() & board->GetEnabledLayers();
if( !aPad->FlashLayer( visible ) )
return true;
}
return aPad->GetShape() != PAD_SHAPE_CUSTOM
&& aPad->GetSizeX() <= aPad->GetDrillSizeX()
&& aPad->GetSizeY() <= aPad->GetDrillSizeY();
};
if( aLayer == LAYER_PADS_PLATEDHOLES || aLayer == LAYER_NON_PLATEDHOLES )
if( aLayer == LAYER_PAD_PLATEDHOLES || aLayer == LAYER_NON_PLATEDHOLES )
{
// Drawing the hole ------------------------------------------------------
const SHAPE_SEGMENT* seg = aPad->GetEffectiveHoleShape();
if( seg->GetSeg().A == seg->GetSeg().B ) // Circular hole
@ -968,36 +930,8 @@ void PCB_PAINTER::draw( const PAD* aPad, int aLayer )
else
m_gal->DrawSegment( seg->GetSeg().A, seg->GetSeg().B, seg->GetWidth() );
}
else if( drawHoleWallCylinder( aPad ) )
{
// Drawing only the hole wall --------------------------------------------
bool draw = true;
m_gal->SetIsFill( false );
m_gal->SetIsStroke( true );
m_gal->SetStrokeColor( color );
if( aLayer == LAYER_PADS_TH )
m_gal->SetLineWidth( bds.GetHolePlatingThickness() * 2 );
else if( aLayer == F_Mask || aLayer == B_Mask )
m_gal->SetLineWidth( ( bds.GetHolePlatingThickness() + aPad->GetSolderMaskMargin() ) * 2 );
else
draw = false;
if( draw )
{
const SHAPE_SEGMENT* seg = aPad->GetEffectiveHoleShape();
if( seg->GetSeg().A == seg->GetSeg().B ) // Circular hole
m_gal->DrawCircle( seg->GetSeg().A, getDrillSize( aPad ).x / 2 );
else
m_gal->DrawSegment( seg->GetSeg().A, seg->GetSeg().B, seg->GetWidth() );
}
}
else
{
// Drawing the pad -------------------------------------------------------
wxSize pad_size = aPad->GetSize();
wxSize margin;
@ -1165,7 +1099,6 @@ void PCB_PAINTER::draw( const PAD* aPad, int aLayer )
}
}
// Draw clearance outlines
constexpr int clearanceFlags = PCB_RENDER_SETTINGS::CL_PADS;
if( ( m_pcbSettings.m_clearanceDisplayFlags & clearanceFlags ) == clearanceFlags

8
pcbnew/pcb_painter.h
View File

@ -243,13 +243,7 @@ class PCB_PAINTER : public PAINTER
public:
PCB_PAINTER( GAL* aGal );
/// @copydoc PAINTER::ApplySettings()
virtual void ApplySettings( const RENDER_SETTINGS* aSettings ) override
{
m_pcbSettings = *static_cast<const PCB_RENDER_SETTINGS*>( aSettings );
}
/// @copydoc PAINTER::GetAdapter()
/// @copydoc PAINTER::GetSettings()
virtual PCB_RENDER_SETTINGS* GetSettings() override
{
return &m_pcbSettings;

12
pcbnew/pcbnew_printout.cpp
View File

@ -216,8 +216,8 @@ void PCBNEW_PRINTOUT::setupViewLayers( KIGFX::VIEW& aView, const LSET& aLayerSet
if( m_pcbnewSettings.m_drillMarks != PCBNEW_PRINTOUT_SETTINGS::NO_DRILL_SHAPE )
{
// Enable hole layers to draw drill marks
for( GAL_LAYER_ID holeLayer : { LAYER_PADS_PLATEDHOLES, LAYER_NON_PLATEDHOLES,
LAYER_VIAS_HOLES } )
for( GAL_LAYER_ID holeLayer : { LAYER_PAD_PLATEDHOLES, LAYER_NON_PLATEDHOLES,
LAYER_VIA_HOLES } )
{
aView.SetLayerVisible( holeLayer, true );
aView.SetTopLayer( holeLayer, true );
@ -241,17 +241,17 @@ void PCBNEW_PRINTOUT::setupPainter( KIGFX::PAINTER& aPainter )
case PCBNEW_PRINTOUT_SETTINGS::SMALL_DRILL_SHAPE:
painter.SetDrillMarks( false, Millimeter2iu( ADVANCED_CFG::GetCfg().m_SmallDrillMarkSize ) );
painter.GetSettings()->SetLayerColor( LAYER_PADS_PLATEDHOLES, COLOR4D::BLACK );
painter.GetSettings()->SetLayerColor( LAYER_PAD_PLATEDHOLES, COLOR4D::BLACK );
painter.GetSettings()->SetLayerColor( LAYER_NON_PLATEDHOLES, COLOR4D::BLACK );
painter.GetSettings()->SetLayerColor( LAYER_VIAS_HOLES, COLOR4D::BLACK );
painter.GetSettings()->SetLayerColor( LAYER_VIA_HOLES, COLOR4D::BLACK );
break;
case PCBNEW_PRINTOUT_SETTINGS::FULL_DRILL_SHAPE:
painter.SetDrillMarks( true );
painter.GetSettings()->SetLayerColor( LAYER_PADS_PLATEDHOLES, COLOR4D::BLACK );
painter.GetSettings()->SetLayerColor( LAYER_PAD_PLATEDHOLES, COLOR4D::BLACK );
painter.GetSettings()->SetLayerColor( LAYER_NON_PLATEDHOLES, COLOR4D::BLACK );
painter.GetSettings()->SetLayerColor( LAYER_VIAS_HOLES, COLOR4D::BLACK );
painter.GetSettings()->SetLayerColor( LAYER_VIA_HOLES, COLOR4D::BLACK );
break;
}

46
pcbnew/track.cpp
View File

@ -39,6 +39,10 @@
#include <geometry/shape_circle.h>
#include <geometry/shape_arc.h>
#include <drc/drc_engine.h>
#include <pcb_painter.h>
using KIGFX::PCB_PAINTER;
using KIGFX::PCB_RENDER_SETTINGS;
TRACK::TRACK( BOARD_ITEM* aParent, KICAD_T idtype ) :
BOARD_CONNECTED_ITEM( aParent, idtype )
@ -530,12 +534,22 @@ double TRACK::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
{
constexpr double HIDE = std::numeric_limits<double>::max();
PCB_PAINTER* painter = static_cast<PCB_PAINTER*>( aView->GetPainter() );
PCB_RENDER_SETTINGS* renderSettings = painter->GetSettings();
if( !aView->IsLayerVisible( LAYER_TRACKS ) )
return HIDE;
// Netnames will be shown only if zoom is appropriate
if( IsNetnameLayer( aLayer ) )
{
// Hide netnames on dimmed tracks
if( renderSettings->GetHighContrast() )
{
if( m_layer != renderSettings->GetPrimaryHighContrastLayer() )
return HIDE;
}
// Netnames will be shown only if zoom is appropriate
return ( double ) Millimeter2iu( 4 ) / ( m_Width + 1 );
}
@ -559,18 +573,20 @@ const BOX2I TRACK::ViewBBox() const
void VIA::ViewGetLayers( int aLayers[], int& aCount ) const
{
aLayers[0] = LAYER_VIAS_HOLES;
aLayers[1] = LAYER_VIAS_NETNAMES;
aCount = 3;
aLayers[0] = LAYER_VIA_HOLES;
aLayers[1] = LAYER_VIA_HOLEWALLS;
aLayers[2] = LAYER_VIA_NETNAMES;
// Just show it on common via & via holes layers
switch( GetViaType() )
{
case VIATYPE::THROUGH: aLayers[2] = LAYER_VIA_THROUGH; break;
case VIATYPE::BLIND_BURIED: aLayers[2] = LAYER_VIA_BBLIND; break;
case VIATYPE::MICROVIA: aLayers[2] = LAYER_VIA_MICROVIA; break;
default: aLayers[2] = LAYER_GP_OVERLAY; break;
case VIATYPE::THROUGH: aLayers[3] = LAYER_VIA_THROUGH; break;
case VIATYPE::BLIND_BURIED: aLayers[3] = LAYER_VIA_BBLIND; break;
case VIATYPE::MICROVIA: aLayers[3] = LAYER_VIA_MICROVIA; break;
default: aLayers[3] = LAYER_GP_OVERLAY; break;
}
aCount = 4;
}
@ -578,9 +594,21 @@ double VIA::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
{
constexpr double HIDE = (double)std::numeric_limits<double>::max();
// Netnames will be shown only if zoom is appropriate
PCB_PAINTER* painter = static_cast<PCB_PAINTER*>( aView->GetPainter() );
PCB_RENDER_SETTINGS* renderSettings = painter->GetSettings();
if( IsNetnameLayer( aLayer ) )
{
// Show netnames only if via is flashed to a high-contrast layer
if( renderSettings->GetHighContrast() )
{
if( !FlashLayer( renderSettings->GetPrimaryHighContrastLayer() ) )
return HIDE;
}
// Netnames will be shown only if zoom is appropriate
return m_Width == 0 ? HIDE : ( (double)Millimeter2iu( 10 ) / m_Width );
}
bool onVisibleLayer = false;