Don't duplicate user-defined track widths, via sizes or DP dims...
... when appending to board. Fixes https://gitlab.com/kicad/code/kicad/issues/12014
This commit is contained in:
parent
b792a3f3f5
commit
aa9fe58abe
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@ -1090,7 +1090,7 @@ void PCB_PARSER::resolveGroups( BOARD_ITEM* aParent )
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{
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BOARD_ITEM* item;
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if( m_resetKIIDs )
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if( m_appendToExisting )
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item = getItem( m_resetKIIDMap[ aUuid.AsString() ] );
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else
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item = getItem( aUuid );
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@ -1868,16 +1868,15 @@ void PCB_PARSER::parseSetup()
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wxCHECK_RET( CurTok() == T_setup,
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wxT( "Cannot parse " ) + GetTokenString( CurTok() ) + wxT( " as setup." ) );
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T token;
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NETCLASS* defaultNetClass = m_board->GetDesignSettings().GetDefault();
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BOARD_DESIGN_SETTINGS& designSettings = m_board->GetDesignSettings();
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ZONE_SETTINGS& zoneSettings = designSettings.GetDefaultZoneSettings();
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BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
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NETCLASS* defaultNetClass = bds.GetDefault();
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ZONE_SETTINGS& zoneSettings = bds.GetDefaultZoneSettings();
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// Missing soldermask min width value means that the user has set the value to 0 and
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// not the default value (0.25mm)
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designSettings.m_SolderMaskMinWidth = 0;
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bds.m_SolderMaskMinWidth = 0;
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for( token = NextTok(); token != T_RIGHT; token = NextTok() )
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for( T token = NextTok(); token != T_RIGHT; token = NextTok() )
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{
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if( token != T_LEFT )
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Expecting( T_LEFT );
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@ -1898,10 +1897,14 @@ void PCB_PARSER::parseSetup()
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case T_user_trace_width:
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{
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// Make room for the netclass value
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if( designSettings.m_TrackWidthList.empty() )
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designSettings.m_TrackWidthList.emplace_back( 0 );
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if( bds.m_TrackWidthList.empty() )
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bds.m_TrackWidthList.emplace_back( 0 );
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int trackWidth = parseBoardUnits( T_user_trace_width );
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if( !m_appendToExisting || !alg::contains( bds.m_TrackWidthList, trackWidth ) )
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bds.m_TrackWidthList.push_back( trackWidth );
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designSettings.m_TrackWidthList.push_back( parseBoardUnits( T_user_trace_width ) );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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@ -1926,13 +1929,13 @@ void PCB_PARSER::parseSetup()
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break;
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case T_clearance_min:
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designSettings.m_MinClearance = parseBoardUnits( T_clearance_min );
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bds.m_MinClearance = parseBoardUnits( T_clearance_min );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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case T_trace_min:
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designSettings.m_TrackMinWidth = parseBoardUnits( T_trace_min );
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bds.m_TrackMinWidth = parseBoardUnits( T_trace_min );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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@ -1950,46 +1953,49 @@ void PCB_PARSER::parseSetup()
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break;
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case T_via_min_annulus:
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designSettings.m_ViasMinAnnularWidth = parseBoardUnits( T_via_min_annulus );
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bds.m_ViasMinAnnularWidth = parseBoardUnits( T_via_min_annulus );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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case T_via_min_size:
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designSettings.m_ViasMinSize = parseBoardUnits( T_via_min_size );
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bds.m_ViasMinSize = parseBoardUnits( T_via_min_size );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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case T_through_hole_min:
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designSettings.m_MinThroughDrill = parseBoardUnits( T_through_hole_min );
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bds.m_MinThroughDrill = parseBoardUnits( T_through_hole_min );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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// Legacy token for T_through_hole_min
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case T_via_min_drill:
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designSettings.m_MinThroughDrill = parseBoardUnits( T_via_min_drill );
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bds.m_MinThroughDrill = parseBoardUnits( T_via_min_drill );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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case T_hole_to_hole_min:
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designSettings.m_HoleToHoleMin = parseBoardUnits( T_hole_to_hole_min );
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bds.m_HoleToHoleMin = parseBoardUnits( T_hole_to_hole_min );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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case T_user_via:
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{
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int viaSize = parseBoardUnits( "user via size" );
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int viaDrill = parseBoardUnits( "user via drill" );
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int viaSize = parseBoardUnits( "user via size" );
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int viaDrill = parseBoardUnits( "user via drill" );
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VIA_DIMENSION via( viaSize, viaDrill );
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// Make room for the netclass value
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if( designSettings.m_ViasDimensionsList.empty() )
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designSettings.m_ViasDimensionsList.emplace_back( VIA_DIMENSION( 0, 0 ) );
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if( bds.m_ViasDimensionsList.empty() )
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bds.m_ViasDimensionsList.emplace_back( VIA_DIMENSION( 0, 0 ) );
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if( !m_appendToExisting || !alg::contains( bds.m_ViasDimensionsList, via ) )
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bds.m_ViasDimensionsList.emplace_back( via );
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designSettings.m_ViasDimensionsList.emplace_back( VIA_DIMENSION( viaSize, viaDrill ) );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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@ -2020,83 +2026,78 @@ void PCB_PARSER::parseSetup()
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break;
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case T_uvia_min_size:
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designSettings.m_MicroViasMinSize = parseBoardUnits( T_uvia_min_size );
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bds.m_MicroViasMinSize = parseBoardUnits( T_uvia_min_size );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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case T_uvia_min_drill:
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designSettings.m_MicroViasMinDrill = parseBoardUnits( T_uvia_min_drill );
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bds.m_MicroViasMinDrill = parseBoardUnits( T_uvia_min_drill );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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case T_user_diff_pair:
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{
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int width = parseBoardUnits( "user diff-pair width" );
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int gap = parseBoardUnits( "user diff-pair gap" );
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int viaGap = parseBoardUnits( "user diff-pair via gap" );
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designSettings.m_DiffPairDimensionsList.emplace_back(
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DIFF_PAIR_DIMENSION( width, gap, viaGap ) );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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}
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{
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int width = parseBoardUnits( "user diff-pair width" );
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int gap = parseBoardUnits( "user diff-pair gap" );
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int viaGap = parseBoardUnits( "user diff-pair via gap" );
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DIFF_PAIR_DIMENSION diffPair( width, gap, viaGap );
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if( !m_appendToExisting || !alg::contains( bds.m_DiffPairDimensionsList, diffPair ) )
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bds.m_DiffPairDimensionsList.emplace_back( diffPair );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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}
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case T_segment_width: // note: legacy (pre-6.0) token
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designSettings.m_LineThickness[ LAYER_CLASS_COPPER ] =
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parseBoardUnits( T_segment_width );
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bds.m_LineThickness[ LAYER_CLASS_COPPER ] = parseBoardUnits( T_segment_width );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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case T_edge_width: // note: legacy (pre-6.0) token
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designSettings.m_LineThickness[ LAYER_CLASS_EDGES ] = parseBoardUnits( T_edge_width );
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bds.m_LineThickness[ LAYER_CLASS_EDGES ] = parseBoardUnits( T_edge_width );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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case T_mod_edge_width: // note: legacy (pre-6.0) token
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designSettings.m_LineThickness[ LAYER_CLASS_SILK ] =
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parseBoardUnits( T_mod_edge_width );
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bds.m_LineThickness[ LAYER_CLASS_SILK ] = parseBoardUnits( T_mod_edge_width );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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case T_pcb_text_width: // note: legacy (pre-6.0) token
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designSettings.m_TextThickness[ LAYER_CLASS_COPPER ] =
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parseBoardUnits( T_pcb_text_width );
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bds.m_TextThickness[ LAYER_CLASS_COPPER ] = parseBoardUnits( T_pcb_text_width );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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case T_mod_text_width: // note: legacy (pre-6.0) token
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designSettings.m_TextThickness[ LAYER_CLASS_SILK ] =
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parseBoardUnits( T_mod_text_width );
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bds.m_TextThickness[ LAYER_CLASS_SILK ] = parseBoardUnits( T_mod_text_width );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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case T_pcb_text_size: // note: legacy (pre-6.0) token
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designSettings.m_TextSize[ LAYER_CLASS_COPPER ].x = parseBoardUnits( "pcb text width" );
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designSettings.m_TextSize[ LAYER_CLASS_COPPER ].y =
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parseBoardUnits( "pcb text height" );
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bds.m_TextSize[ LAYER_CLASS_COPPER ].x = parseBoardUnits( "pcb text width" );
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bds.m_TextSize[ LAYER_CLASS_COPPER ].y = parseBoardUnits( "pcb text height" );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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case T_mod_text_size: // note: legacy (pre-6.0) token
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designSettings.m_TextSize[ LAYER_CLASS_SILK ].x =
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parseBoardUnits( "footprint text width" );
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designSettings.m_TextSize[ LAYER_CLASS_SILK ].y =
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parseBoardUnits( "footprint text height" );
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bds.m_TextSize[ LAYER_CLASS_SILK ].x = parseBoardUnits( "footprint text width" );
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bds.m_TextSize[ LAYER_CLASS_SILK ].y = parseBoardUnits( "footprint text height" );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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case T_defaults:
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parseDefaults( designSettings );
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parseDefaults( bds );
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m_board->m_LegacyDesignSettingsLoaded = true;
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break;
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@ -2105,7 +2106,7 @@ void PCB_PARSER::parseSetup()
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wxSize sz;
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sz.SetWidth( parseBoardUnits( "master pad width" ) );
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sz.SetHeight( parseBoardUnits( "master pad height" ) );
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designSettings.m_Pad_Master->SetSize( sz );
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bds.m_Pad_Master->SetSize( sz );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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@ -2114,29 +2115,29 @@ void PCB_PARSER::parseSetup()
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case T_pad_drill:
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{
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int drillSize = parseBoardUnits( T_pad_drill );
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designSettings.m_Pad_Master->SetDrillSize( wxSize( drillSize, drillSize ) );
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bds.m_Pad_Master->SetDrillSize( wxSize( drillSize, drillSize ) );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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}
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case T_pad_to_mask_clearance:
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designSettings.m_SolderMaskExpansion = parseBoardUnits( T_pad_to_mask_clearance );
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bds.m_SolderMaskExpansion = parseBoardUnits( T_pad_to_mask_clearance );
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NeedRIGHT();
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break;
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case T_solder_mask_min_width:
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designSettings.m_SolderMaskMinWidth = parseBoardUnits( T_solder_mask_min_width );
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bds.m_SolderMaskMinWidth = parseBoardUnits( T_solder_mask_min_width );
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NeedRIGHT();
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break;
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case T_pad_to_paste_clearance:
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designSettings.m_SolderPasteMargin = parseBoardUnits( T_pad_to_paste_clearance );
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bds.m_SolderPasteMargin = parseBoardUnits( T_pad_to_paste_clearance );
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NeedRIGHT();
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break;
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case T_pad_to_paste_clearance_ratio:
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designSettings.m_SolderPasteMarginRatio = parseDouble( T_pad_to_paste_clearance_ratio );
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bds.m_SolderPasteMarginRatio = parseDouble( T_pad_to_paste_clearance_ratio );
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NeedRIGHT();
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break;
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@ -2144,7 +2145,7 @@ void PCB_PARSER::parseSetup()
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{
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int x = parseBoardUnits( "auxiliary origin X" );
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int y = parseBoardUnits( "auxiliary origin Y" );
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designSettings.SetAuxOrigin( VECTOR2I( x, y ) );
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bds.SetAuxOrigin( VECTOR2I( x, y ) );
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// Aux origin still stored in board for the moment
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//m_board->m_LegacyDesignSettingsLoaded = true;
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@ -2156,7 +2157,7 @@ void PCB_PARSER::parseSetup()
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{
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int x = parseBoardUnits( "grid origin X" );
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int y = parseBoardUnits( "grid origin Y" );
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designSettings.SetGridOrigin( VECTOR2I( x, y ) );
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bds.SetGridOrigin( VECTOR2I( x, y ) );
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// Grid origin still stored in board for the moment
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//m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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@ -2179,7 +2180,7 @@ void PCB_PARSER::parseSetup()
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}
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case T_max_error:
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designSettings.m_MaxError = parseBoardUnits( T_max_error );
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bds.m_MaxError = parseBoardUnits( T_max_error );
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m_board->m_LegacyDesignSettingsLoaded = true;
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NeedRIGHT();
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break;
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@ -6152,7 +6153,7 @@ KIID PCB_PARSER::CurStrToKIID()
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{
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KIID aId;
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if( m_resetKIIDs )
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if( m_appendToExisting )
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{
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aId = KIID();
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m_resetKIIDMap.insert( std::make_pair( CurStr(), aId ) );
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@ -73,12 +73,12 @@ class PROGRESS_REPORTER;
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class PCB_PARSER : public PCB_LEXER
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{
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public:
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PCB_PARSER( LINE_READER* aReader, BOARD* aBoard,
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PCB_PARSER( LINE_READER* aReader, BOARD* aAppendToMe,
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std::function<bool( wxString, int, wxString, wxString )>* aQueryUserCallback,
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PROGRESS_REPORTER* aProgressReporter = nullptr, unsigned aLineCount = 0 ) :
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PCB_LEXER( aReader ),
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m_board( aBoard ),
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m_resetKIIDs( aBoard != nullptr ),
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m_board( aAppendToMe ),
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m_appendToExisting( aAppendToMe != nullptr ),
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m_progressReporter( aProgressReporter ),
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m_lastProgressTime( std::chrono::steady_clock::now() ),
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m_lineCount( aLineCount ),
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@ -324,7 +324,7 @@ private:
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bool parseBool();
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/*
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* @return if m_resetKIIDs, returns new KIID(), otherwise returns CurStr() as KIID.
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* @return if m_appendToExisting, returns new KIID(), otherwise returns CurStr() as KIID.
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*/
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KIID CurStrToKIID();
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@ -354,7 +354,7 @@ private:
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std::vector<int> m_netCodes; ///< net codes mapping for boards being loaded
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bool m_tooRecent; ///< true if version parses as later than supported
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int m_requiredVersion; ///< set to the KiCad format version this board requires
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bool m_resetKIIDs; ///< reading into an existing board; reset UUIDs
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bool m_appendToExisting; ///< reading into an existing board; reset UUIDs
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///< if resetting UUIDs, record new ones to update groups with.
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KIID_MAP m_resetKIIDMap;
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