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CADSTAR PCB: Set Copper-to-Hole clearance as 0 

Testing suggests that CADSTAR doesn't actually have any clearance to the
hole (other than electrical clearance to the barrel of the padstack/
viastack).

This removes a large amount of DRC violations on imported designs.
This commit is contained in:
Roberto Fernandez Bautista 2021-10-10 00:20:13 +01:00
parent eb7d0fdf8a
commit ac3ade874e
1 changed files with 1 additions and 1 deletions
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2
pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp
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@ -654,7 +654,7 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadDesignRules()
ds.m_ViasMinAnnularWidth = ds.m_TrackMinWidth / 2; // Not specified, assumed half track width
ds.m_MinThroughDrill = PCB_IU_PER_MM * 0.0508; // CADSTAR does not specify a minimum hole size
// so set to minimum permitted in KiCad (2 mils)
ds.m_HoleClearance = ds.m_CopperEdgeClearance; // Not specified, assumed same as edge
ds.m_HoleClearance = 0; // Testing suggests cadstar might not have a copper-to-hole clearance
auto applyNetClassRule = [&]( wxString aID, NETCLASS* aNetClassPtr,
void ( NETCLASS::*aFunc )( int ) ) {