Add silk clearance checking to Resolve Clearances...

Also fixes a bug in order of RTrees in silk collision checker.
This commit is contained in:
Jeff Young 2020-10-11 14:15:22 +01:00
parent 42eecdfd3a
commit af28ef9d56
4 changed files with 44 additions and 29 deletions

View File

@ -620,18 +620,19 @@ DRC_CONSTRAINT DRC_ENGINE::EvalRulesForItems( DRC_CONSTRAINT_TYPE_T aConstraintI
REPORT( "" )
if( aConstraintId == DRC_CONSTRAINT_TYPE_CLEARANCE )
if( aConstraintId == DRC_CONSTRAINT_TYPE_CLEARANCE
|| aConstraintId == DRC_CONSTRAINT_TYPE_SILK_CLEARANCE
|| aConstraintId == DRC_CONSTRAINT_TYPE_HOLE_CLEARANCE
|| aConstraintId == DRC_CONSTRAINT_TYPE_COURTYARD_CLEARANCE )
{
int clearance = rcons->constraint.m_Value.Min();
REPORT( wxString::Format( implicit ? _( "Checking %s; clearance: %s." )
: _( "Checking rule %s; clearance: %s."),
REPORT( wxString::Format( _( "Checking %s; clearance: %s." ),
rcons->constraint.GetName(),
MessageTextFromValue( UNITS, clearance ) ) )
}
else
{
REPORT( wxString::Format( implicit ? _( "Checking %s." )
: _( "Checking rule %s."),
REPORT( wxString::Format( _( "Checking %s." ),
rcons->constraint.GetName() ) )
}

View File

@ -199,11 +199,13 @@ bool DRC_TEST_PROVIDER_SILK_CLEARANCE::Run()
return true;
};
int numSilk = forEachGeometryItem( { PCB_SHAPE_T, PCB_FP_SHAPE_T, PCB_TEXT_T, PCB_FP_TEXT_T },
forEachGeometryItem( { PCB_SHAPE_T, PCB_FP_SHAPE_T, PCB_TEXT_T, PCB_FP_TEXT_T },
LSET( 2, F_SilkS, B_SilkS ), addToSilkTree );
forEachGeometryItem( {}, LSET::FrontMask() | LSET::BackMask(), addToTargetTree );
reportAux( _("Testing %d silkscreen features."), numSilk );
reportAux( _("Testing %d silkscreen features against %d board items."),
silkTree.size(),
targetTree.size() );
const std::vector<DRC_RTREE::LAYER_PAIR> layerPairs =
{
@ -225,7 +227,7 @@ bool DRC_TEST_PROVIDER_SILK_CLEARANCE::Run()
DRC_RTREE::LAYER_PAIR( B_SilkS, Edge_Cuts ),
};
silkTree.QueryCollidingPairs( &targetTree, layerPairs, checkClearance, m_largestClearance );
targetTree.QueryCollidingPairs( &silkTree, layerPairs, checkClearance, m_largestClearance );
reportRuleStatistics();

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@ -183,8 +183,9 @@ void PCB_INSPECTION_TOOL::reportZoneConnection( ZONE_CONTAINER* aZone, D_PAD* aP
}
void PCB_INSPECTION_TOOL::reportCopperClearance( PCB_LAYER_ID aLayer, BOARD_CONNECTED_ITEM* aA,
BOARD_ITEM* aB, REPORTER* r )
void PCB_INSPECTION_TOOL::reportClearance( DRC_CONSTRAINT_TYPE_T aClearanceType,
PCB_LAYER_ID aLayer, BOARD_ITEM* aA, BOARD_ITEM* aB,
REPORTER* r )
{
r->Report( "" );
@ -201,8 +202,7 @@ void PCB_INSPECTION_TOOL::reportCopperClearance( PCB_LAYER_ID aLayer, BOARD_CONN
return;
}
auto constraint = drcEngine.EvalRulesForItems( DRC_CONSTRAINT_TYPE_CLEARANCE, aA, aB,
aLayer, r );
auto constraint = drcEngine.EvalRulesForItems( aClearanceType, aA, aB, aLayer, r );
if( r )
{
@ -248,9 +248,32 @@ int PCB_INSPECTION_TOOL::InspectClearance( const TOOL_EVENT& aEvent )
else if( !a->IsConnected() && b->IsConnected() )
std::swap( a, b );
if( !IsCopperLayer( layer ) )
auto getItemDescription =
[&]( BOARD_ITEM* aItem )
{
r->Report( wxString::Format( _( "Active layer (%s) is not a copper layer. "
wxString s = aItem->GetSelectMenuText( r->GetUnits() );
if( auto* cItem = dynamic_cast<BOARD_CONNECTED_ITEM*>( aItem ) )
s += wxString::Format( _( " [netclass %s]" ), cItem->GetNetClassName() );
return s;
};
if( layer == F_SilkS || layer == B_SilkS )
{
r->Report( _( "<h7>Silkscreen clearance resolution for:</h7>" ) );
r->Report( wxString::Format( wxT( "<ul><li>%s %s</li><li>%s</li><li>%s</li></ul>" ),
_( "Layer" ),
m_frame->GetBoard()->GetLayerName( layer ),
getItemDescription( a ),
getItemDescription( b ) ) );
reportClearance( DRC_CONSTRAINT_TYPE_SILK_CLEARANCE, layer, a, b, r );
}
else if( !IsCopperLayer( layer ) )
{
r->Report( wxString::Format( _( "Active layer (%s) is not a silk or copper layer. "
"No clearance defined." ),
m_frame->GetBoard()->GetLayerName( layer ) ) );
}
@ -272,17 +295,6 @@ int PCB_INSPECTION_TOOL::InspectClearance( const TOOL_EVENT& aEvent )
}
else
{
auto getItemDescription =
[&]( BOARD_ITEM* aItem )
{
wxString s = aItem->GetSelectMenuText( r->GetUnits() );
if( auto* cItem = dynamic_cast<BOARD_CONNECTED_ITEM*>( aItem ) )
s += wxString::Format( _( " [netclass %s]" ), cItem->GetNetClassName() );
return s;
};
r->Report( _( "<h7>Clearance resolution for:</h7>" ) );
r->Report( wxString::Format( wxT( "<ul><li>%s %s</li><li>%s</li><li>%s</li></ul>" ),
@ -311,7 +323,7 @@ int PCB_INSPECTION_TOOL::InspectClearance( const TOOL_EVENT& aEvent )
else if( ac )
{
// Different nets (or second unconnected)....
reportCopperClearance( layer, ac, b, r );
reportClearance( DRC_CONSTRAINT_TYPE_CLEARANCE, layer, ac, b, r );
}
}

View File

@ -116,8 +116,8 @@ private:
void reportZoneConnection( ZONE_CONTAINER* aZone, D_PAD* aPad, REPORTER* r );
void reportCopperClearance( PCB_LAYER_ID aLayer, BOARD_CONNECTED_ITEM* aA, BOARD_ITEM* aB,
REPORTER* r );
void reportClearance( DRC_CONSTRAINT_TYPE_T aClearanceType, PCB_LAYER_ID aLayer,
BOARD_ITEM* aA, BOARD_ITEM* aB, REPORTER* r );
private:
PCB_EDIT_FRAME* m_frame; // Pointer to the currently used edit frame.