Deprecate V6 roadmap and move to Wiki
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# Version 6 Road Map # {#v6_road_map}
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# Version 6 Road Map
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This document is the KiCad version 6 Developer's road map document. It is
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living document that should be maintained during the version 6 development
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cycle. The goal of this document is to provide an overview for developers
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of the goals for the project for the version 6 release of KiCad. It is
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broken into sections for each major component of the KiCad source code and
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documentation. It defines tasks that developers an use to contribute to the
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project and provides updated status information. Tasks should define clear
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objectives and avoid vague generalizations so that a new developer can complete
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the task. It is not a place for developers to add their own personal wish.
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list. It should only be updated with approval of the project manager after
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discussion with the lead developers.
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Each entry in the road map is made up of four sections. The goal should
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be a brief description of the what the road map entry will accomplish. The
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task section should be a list of deliverable items that are specific enough
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hat they can be documented as completed. The dependencies sections is a list
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of requirements that must be completed before work can begin on any of the
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tasks. The status section should include a list of completed tasks or marked
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as complete as when the goal is met.
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[TOC]
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# General # {#v6_general}
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This section defines the tasks that affect all or most of KiCad or do not
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fit under as specific part of the code such as the board editor or the
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schematic editor.
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## User Interface Modernization ## {#v6_wxaui}
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**Goal:**
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Give KiCad a more modern user interface with dockable tool bars and windows.
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Create perspectives to allow users to arrange dockable windows as they prefer.
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**Task:**
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- Take advantage of the advanced UI features in wxAui such as detaching and
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hiding.
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- Clean up menu structure. Menus must allow access to all features of the
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program in a clear and logical way. Currently some functions of Pcbnew are
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accessible only through tool bars
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- Redesign dialogs, make sure they are following same style rules.
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- Check quality of translations. Either fix or remove bad quality translations.
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- Develop a global shortcut manager that allows the user assign arbitrary
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shortcuts for any tool or action.
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**Dependencies:**
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- None
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**Status:**
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- No progress.
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## Object Properties and Introspection ## {#v6_object_props}
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**Goal:**
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Provide an object introspection system using properties.
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**Task:**
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- Select existing or develop property system.
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- Add definable properties to base objects.
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- Create introspection framework for manipulating object properties.
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- Serialization of properties to and from files and/or other I/O structures.
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- Create tool to edit property namespace/object name/name/type/value table.
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**Dependencies:**
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- None
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**Status:**
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- In progress.
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# Eeschema: Schematic Editor # {#v6_eeschema}
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This section applies to the source code for the Eeschema schematic editor.
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## Coherent SCHEMATIC Object ## {#v6_sch_object}
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**Goal:**
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Clean up the code related to the schematic object(s) into a coherent object for
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managing and manipulating the schematic that can be used by third party tools
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and Python scripting.
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**Task:**
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- Move handling of root sheet object to SCHEMATIC object.
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- Move SCH_SCREENS code into SCH_OBJECT.
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- Build and maintain schematic hierarchy in SCHEMATIC object rather than
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recreating on the fly every time the hierarchical information is required.
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- Optionally build and maintain netlist during editing for extended editing
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features.
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- Add any missing functionality to the SCHEMATIC object.
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**Dependencies:**
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- None
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**Status:**
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- In progress.
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## Implement Sweet (S-Expression) Symbol Libraries ## {#v6_sch_sweet}
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**Goal:**
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Make symbol library design more robust and feature rich. Use s-expressions
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to make component library files more readable.
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**Task:**
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- Use sweet component file format for component libraries.
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**Dependencies:**
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- None
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**Status:**
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- Initial SWEET library file format document written.
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## S-Expression File Format ## {#v6_sch_sexpr}
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**Goal:**
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Make schematic file format more readable, add new features, and take advantage
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of the s-expression parser and formatter capability used in Pcbnew.
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**Task:**
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- Finalize feature set and file format.
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- Discuss the possibility of dropping the unit-less proposal temporarily to get
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the s-expression file format and SWEET library format implemented without
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completely rewriting Eeschema.
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- Add new s-expression file format to plugin.
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**Dependencies:**
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- [S-expression file format](#v6_sch_sweet).
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**Status:**
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- File format document initial draft complete.
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## Move Common Schematic Code into a Shared Object ## {#v6_sch_shared_object}
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**Goal:**
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Refactor all schematic object code so that it can be built into a shared object
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for use by the schematic editor, Python module, and linked into third party
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programs.
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**Task**
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- Split schematic object code from schematic and component editor code.
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- Generate shared object from schematic object code.
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- Update build configuration to build schematic and component editors
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against new schematic shared object.
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**Dependencies:**
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- None
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**Progress:**
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- No progress.
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## ERC Improvements ## {#v6_sch_erc_improvements}
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**Goal:**
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Improve the coverage and usability of the electrical rules checker (ERC).
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**Task:**
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- Add warning when multiple labels are defined for a single net. The user should
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be able to disable this warning.
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- Save electrical rules settings to project file between sessions.
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**Dependencies:**
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- None
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**Status:**
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- No progress.
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## Port Editing Tools to New Tool Framework ## {#v6_sch_tool_framework}
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**Goal:**
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Convert all editing tool to new tool framework.
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**Task:**
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- Rewrite existing editing tools using the new tool framework.
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- Add new capabilities supported by the new tool framework to existing
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editing tools.
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- Remove legacy tool framework.
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**Dependencies:**
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- None.
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**Status:**
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- Schematic editor complete.
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## Net Highlighting ## {#v6_sch_net_highlight}
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**Goal:**
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Highlight wires, buses, and junctions when corresponding net in Pcbnew is selected.
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**Task:**
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- Add communications link to handle net selection from Pcbnew.
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- Implement highlight algorithm for net objects.
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- Highlight objects connected to net selected in Pcbnew.
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**Dependencies:**
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- None.
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**Status:**
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- Complete.
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## Allow Use of System Fonts ## {#v6_sch_sys_fonts}
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**Goal:**
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Currently the schematic editor uses the stroke drawn fonts which aren't really
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necessary for accurate printing of schematics. Allow the use of system fonts
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for schematic text.
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**Task:**
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- Determine which library for font handling makes the most sense, wxWidgets or
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freetype.
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- Add support for selecting text object fonts.
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**Dependencies:**
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- [S-expression schematic file format](#v6_sch_sexpr).
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**Status:**
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- No progress.
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## Symbol and Netlist Attributes ## {#v6_netlist_attributes}
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**Goal:**
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Provide a method of passing information to other tools via the net list.
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**Task:**
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- Add virtual components and attributes to netlist to define properties that
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can be used by other tools besides the board editor.
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- Attributes (properties) are automatically included as part of the new file
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format.
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**Dependencies:**
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- [S-expression schematic file format](#v6_sch_sexpr).
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**Status:**
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- No progress.
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## Orthogonal Wire Drag ## {#v6_orthogonal_drag}
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**Goal:**
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Keep wires and buses orthogonal when dragging a symbol.
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**Task:**
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- Add code to new tool framework to allow for orthogonal dragging of symbols.
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**Dependencies:**
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- [New tool framework](#v6_sch_tool_framework).
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**Status:**
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- No progress.
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## Custom Wire and Bus Attributes ## {#v6_sch_bus_wire_attr}
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**Goal:**
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Allow for wires and buses to have different widths, colors, and line types.
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**Task:**
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- Add code to support custom wire and bus attributes.
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- Add user interface element to support changing wire and bus attributes.
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**Dependencies:**
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- [S-Expression File Format](#v6_sch_sexpr).
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**Status:**
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- No progress.
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## Connectivity Improvements ## {#v6_sch_connectivity}
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**Goal:**
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Support structured buses, real time netlist calculations, and other
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connectivity improvements.
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**Task:**
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- Keep netlist up to date real time.
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- Add support for structured bus definitions.
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- Possible real time ERC checking.
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**Dependencies:**
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- None.
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**Status:**
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- Real time netlist and structured bus support complete.
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## ERC Improvements ## {#v6_sch_erc}
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**Goal:**
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Improve ERC test coverage and other ERC usability features.
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**Task:**
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- Add missing ERC tests to improve coverage.
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- Save ERC settings in project file.
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- Add mechanism to allow import and export of ERC settings.
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- ERC user interface improvements.
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**Dependencies:**
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- None.
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**Status:**
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- Preliminary specification draft complete.
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## Python Support ## {#v6_sch_python}
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**Goal:**
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SWIG all schematic low level objects and coherent schematic object to
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provide Python interface for manipulating schematic objects.
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**Task:**-
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- Create SWIG wrappers for all low level schematic, symbol library, and
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coherent schematic object code.
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- Add Python interpreter launcher.
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**Dependencies:**
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- [Coherent Schematic Object](#v6_sch_object).
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**Status:**
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- No Progress.
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# CvPcb: Footprint Association Tool # {#v6_cvpcb}
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This section covers the source code of the footprint assignment tool CvPcb.
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# Pcbnew: Circuit Board Editor # {#v6_pcbnew}
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This section covers the source code of the board editing application Pcbnew.
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## Push and Shove Router Improvements ## {#v6_ps_router_improvements}
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**Goal:**
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Add finishing touches to push and shove router.
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**Task:**
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- Delete and backspace in idle mode
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- Differential pair clearance fixes.
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- Differential pair optimizer improvements (recognize differential pairs)
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- Persistent differential pair gap/width setting.
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- Walk around in drag mode.
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- Optimize trace being dragged too. (currently no optimization)
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- Auto-finish traces (if time permits)
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- Additional optimization pass for spring back algorithm using area-minimization
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strategy. (improves tightness of routing)
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- Restrict optimization area to view port (if user wants to)
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- Support 45 degree tuning meanders.
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- Respect trace/via locking!
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- Keep out zone support.
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- Microwave tools to be added as parameterized shapes generated by Python
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scripts.
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- BGA fan out support.
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- Drag footprints with traces connected.
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**Dependencies:**
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- None.
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**Status:**
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- In progress.
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## Selection Filtering ## {#v6_pcb_selection_filtering}
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**Goal:**
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Make the selection tool easier for the user to determine which object(s) are
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being selected by filtering.
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**Task:**
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- Provide filtered object selection by adding a third tab to the layer manager
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or possibly some other UI element to provide filtered selection options.
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**Dependencies:**
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- None
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**Status:**
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- In progress.
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## Design Rule Check (DRC) Improvements. ## {#v6_drc_improvements}
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**Goal:**
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Create additional DRC tests for improved error checking.
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**Task:**
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- Remove floating point code from clearance calculations to prevent rounding
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errors.
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- Add checks for component, silk screen, and mask clearances.
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- Add checks for keep out zones.
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- Remove DRC related limitations such as no arc or text on copper layers.
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- Add option for saving and loading DRC options.
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**Dependencies:**
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- [Constraint Management System](#v6_pcb_constraint).
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**Progress:**
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- In progress.
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## Linked Objects ## {#v6_pcb_linked_objects}
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**Goal:**
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Provide a way to allow external objects such as footprints to be externally
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linked in the board file so that changes in the footprint are automatically
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updated. This will allow a one to many object relationship which can pave
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the way for reusable board modules.
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**Task:**
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- Add externally and internally linked objects to the file format to allow for
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footprints and/or other board objects to be shared (one to many relationship)
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instead of only supporting embedded objects (one to one relationship) that
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can only be edited in place.
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**Dependencies:**
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- None.
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**Status:**
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- No progress.
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## Pin and Part Swapping ## {#v6_pcb_drc}
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**Goal:**
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Allow Pcbnew to perform pin and/or part swapping during layout so the user
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does not have to do it in Eeschema and re-import the net list.
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**Task:**
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- Provide forward and back annotation between the schematic and board editors.
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- Define netlist file format changes required to handle pin/part swapping.
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- Update netlist file formatter and parser to handle file format changes.
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- Develop a netlist comparison engine that will produce a netlist diff that
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can be passed between the schematic and board editors.
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- Create pin/part swap dialog to manipulate swappable pins and parts.
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- Add support to handle net label back annotation changes.
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**Dependencies:**
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- [S-Expression File Format](#v6_sch_sexpr).
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**Status:**
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- No progress.
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## Keepout Zones. ## {#v6_keepout_zones}
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**Goal:**
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Add support for keepout zones on boards and footprints.
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**Task:**
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- Add keepout support to zone classes.
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- Add keepout zone support to board editor.
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- Add keepout zone support to library editor.
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**Dependencies:**
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- [DRC Improvements.](#v6_drc_improvements)
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**Progress:**
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- In progress.
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## Clipboard Support ## {#v6_fp_edit_clipboard}
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**Goal:**
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Provide clipboard cut and paste for footprints.
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**Task:**
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- Clipboard cut and paste to and from clipboard of footprints in footprint
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editor.
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**Dependencies:**
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- None
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**Status:**
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- Complete.
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## Net Highlighting ## {#v6_pcb_net_highlight}
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**Goal:**
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Highlight rats nest links and/or traces when corresponding net in Eeschema is selected.
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**Task:**
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- Add communications link to handle net selection from Eeschema.
|
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- Implement highlight algorithm for objects connected to the selected net.
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- Highlight objects connected to net selected in Eeschema
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|
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**Dependencies:**
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- None.
|
||||
|
||||
**Status:**
|
||||
- Complete.
|
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## Hatched Zone Filling ## {#v6_pcb_hatched_zones}
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**Goal:**
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Currently Pcbnew only supports solid zone files. Add option to fill zones
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with hatching.
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**Task:**
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- Determine zone fill method, required filling code, and file format requirements.
|
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- Add hatch option and hatch configuration to zone dialog.
|
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**Dependencies:**
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- None.
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**Status:**
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||||
- Complete.
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## Board Stack Up Impedance Calculator ## {#v6_pcb_impedance_calc}
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**Goal:**
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Provide a calculator to compute trace impedances using a full board stackup.
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Maybe this should be included in the PCB calculator application.
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**Task:**
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- Design a trace impedance calculator that includes full board stackup.
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|
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**Dependencies:**
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- None.
|
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|
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**Status:**
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- In progress.
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## Net Class Improvements ## {#v6_pcb_net_class_improvements}
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**Goal:**
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|
||||
Add support for route impedance, color selection, etc in net class object.
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||||
|
||||
**Task:**
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- Determine parameters to add to net class object.
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- Implement file parser and formatter changes to support net class object
|
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changes.
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- Implement tools to work with new net class parameters.
|
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- Create UI elements to configure new net class parameters.
|
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- Update the render tab UI code to view traces by net class.
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||||
**Dependencies:**
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||||
- None.
|
||||
|
||||
**Status:**
|
||||
- No progress.
|
||||
|
||||
## Ratsnest Improvements ## {#v6_pcb_ratsnest_improvements}
|
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**Goal:**
|
||||
|
||||
Add support for curved rats and per net color and visibility settings.
|
||||
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**Task:**
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||||
- Implement rat curving to minimize overlapped rats.
|
||||
- Implement UI code to configure ratsnest color and visibility.
|
||||
- Update ratsnest code to handle per net color and visibility.
|
||||
|
||||
**Dependencies:**
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||||
- None.
|
||||
|
||||
**Status:**
|
||||
- Curved rat support complete.
|
||||
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||||
## DXF Improvements ## {#v6_pcb_dxf_import}
|
||||
**Goal:**
|
||||
|
||||
- Allow for anchor point setting and layer mapping support on DXF import and
|
||||
export multiple board layers to a single DXF file.
|
||||
|
||||
**Task:**
|
||||
- Provide method to select DXF import anchor point.
|
||||
- Add user interface to allow mapping DXF layers to board layers.
|
||||
- Modify DXF plotting to export multiple layers to a single file.
|
||||
|
||||
**Dependencies:**
|
||||
- None.
|
||||
|
||||
**Status:**
|
||||
- No progress.
|
||||
|
||||
## Improve Dimension Tool ## {#v6_pcb_dim_tool}
|
||||
**Goal:**
|
||||
|
||||
Make dimensions link to objects and change when objects are modified and add
|
||||
basic mechanical constraints.
|
||||
|
||||
**Task:**
|
||||
- Add code to link dimension to objects.
|
||||
- Add basic mechanical constraints like linear distance and angle.
|
||||
|
||||
**Dependencies:**
|
||||
- None.
|
||||
|
||||
**Status:**
|
||||
- In progress.
|
||||
|
||||
## Constraint Management System ## {#v6_pcb_constraint}
|
||||
**Goal:**
|
||||
|
||||
Implement full featured constraint management system to allow for complex
|
||||
board constraints instead of netclass only constraints.
|
||||
|
||||
**Task:**
|
||||
- Write specification to define requirement of new constraint system.
|
||||
- Implement new constraint system including file format changes.
|
||||
- Allow constraints to be defined in schematic editor and passed to board
|
||||
editor via netlist.
|
||||
- Update netlist file format to support constraints.
|
||||
- Update DRC to test new constraints.
|
||||
|
||||
**Dependencies:**
|
||||
- None.
|
||||
|
||||
**Status**
|
||||
- No Progress.
|
||||
|
||||
## Append Board in Project Mode ## {#v6_pcb_append}
|
||||
**Goal:**
|
||||
|
||||
Allow appending to the board when running Pcbnew in the project mode.
|
||||
|
||||
**Task:**
|
||||
- Enable append board feature in project mode.
|
||||
- Extend copy/paste feature to introduce paste special tool to add prefix
|
||||
and/or suffix to nets of pasted/appended objects.
|
||||
|
||||
**Dependencies:**
|
||||
- None.
|
||||
|
||||
**Status:**
|
||||
- No progress.
|
||||
|
||||
## Grid and Auxiliary Origin Improvements ## {#v6_pcb_origin}
|
||||
**Goal:**
|
||||
|
||||
Allow reset grid and auxiliary origin without hotkey only. Add support to
|
||||
make all coordinates relative to the plot origin.
|
||||
|
||||
**Task:**
|
||||
- Add reset grid and auxiliary origin commands to menu entry and/or toolbar
|
||||
button.
|
||||
- Add code to dialogs to allow coordinates to be specified relative to the
|
||||
plot origin.
|
||||
|
||||
**Dependencies:**
|
||||
- None.
|
||||
|
||||
**Status:**
|
||||
- Relative coordinate entry in progress.
|
||||
|
||||
## Addition Mechanical Layers ## {#v6_pcb_mech_layers}
|
||||
**Goal:**
|
||||
|
||||
Add more mechanical layers.
|
||||
|
||||
**Task:**
|
||||
- Add remaining mechanical layers for a total of 32.
|
||||
|
||||
**Dependencies:**
|
||||
- None.
|
||||
|
||||
**Status:**
|
||||
- No progress.
|
||||
|
||||
## Layer Renaming ## {#v6_pcb_layer_rename}
|
||||
**Goal:**
|
||||
|
||||
Allow mechanical layers to be renamed.
|
||||
|
||||
**Task:**
|
||||
- Quote layer names in file format to support any printable characters in
|
||||
layer names.
|
||||
- Add user interface to allow mechanical layers to be renamed.
|
||||
|
||||
**Dependencies:**
|
||||
- None.
|
||||
|
||||
**Status:**
|
||||
- Quoted layer names complete.
|
||||
|
||||
## Stable Python API ## {#v6_pcb_python_api}
|
||||
**Goal:**
|
||||
|
||||
Create a Python wrapper to hide the SWIG generated API.
|
||||
|
||||
**Task:**
|
||||
- Document new Python API.
|
||||
- Write Python API.
|
||||
|
||||
**Dependencies:**
|
||||
- None.
|
||||
|
||||
**Status:**
|
||||
- Initial technical specification drafted.
|
||||
|
||||
## Track Refining ## {#v6_pcb_track_refine}
|
||||
**Goal:**
|
||||
|
||||
Add support for teardrops and automatically updating length tuning
|
||||
meandering.
|
||||
|
||||
**Task:**
|
||||
- Draft specification for track refining.
|
||||
- Implement support for teardrops.
|
||||
- Implement support for changing tuned length meandering.
|
||||
|
||||
**Dependencies:**
|
||||
- None.
|
||||
|
||||
**Status:**
|
||||
- Initial technical specification drafted.
|
||||
|
||||
## Groups and Rooms ## {#v6_pcb_groups}
|
||||
**Goal:**
|
||||
|
||||
Support grouping board objects into reusable snippets.
|
||||
|
||||
**Task:**
|
||||
- Write design specification.
|
||||
- Update board file format to support grouped objects.
|
||||
- Add user interface code to support grouped board objects.
|
||||
|
||||
**Dependencies:**
|
||||
- None.
|
||||
|
||||
**Status:**
|
||||
- Initial technical specification drafted.
|
||||
|
||||
## Pad Stack Support ## {#v6_pcb_padstack}
|
||||
**Goal:**
|
||||
|
||||
Add padstack support.
|
||||
|
||||
**Task:**
|
||||
- Write pad stack design specification.
|
||||
- Update board file format to support pad stacks.
|
||||
- Add user interface code to support designing pad stack objects.
|
||||
- Update push and shove router to handle pad stacks.
|
||||
- Update zone filling to handle pad stacks.
|
||||
- Update DRC to handle pad stacks.
|
||||
|
||||
**Dependencies:**
|
||||
- None.
|
||||
|
||||
**Status:**
|
||||
- Initial technical specification drafted.
|
||||
|
||||
## Net Ties ## {#v6_pcb_net_ties}
|
||||
**Goal:**
|
||||
|
||||
Add support for net ties.
|
||||
|
||||
**Task:**
|
||||
- Write net tie design specification.
|
||||
- Implement board file support for net ties.
|
||||
- Implement schematic file support for net ties.
|
||||
- Update ERC and DRC to handle net ties.
|
||||
- Update netlist to pass net tie information from schematic to board.
|
||||
- Add user interface support for net ties to editors.
|
||||
|
||||
**Dependencies:**
|
||||
- [S-Expression File Format](#v6_sch_sexpr).
|
||||
|
||||
**Status:**
|
||||
- No Progress.
|
||||
|
||||
## Anti-pad Improvements ## {#v6_pcb_anti_pad}
|
||||
**Goal:**
|
||||
|
||||
Use anti-pads on vias and through hold pads on internal layers as required.
|
||||
|
||||
**Task:**-
|
||||
- Revise zone filling algorithm to create anti-pad on internal layers.
|
||||
|
||||
**Dependencies:**
|
||||
- None.
|
||||
|
||||
**Status:**
|
||||
- No Progress.
|
||||
|
||||
## Thermal Relief Improvements ## {#v6_pcb_thermal_relief}
|
||||
**Goal:**
|
||||
|
||||
Allow for custom thermal reliefs in zones and custom pad shapes.
|
||||
|
||||
**Task:**-
|
||||
- Write technical specification to define requirements, alternate unions,
|
||||
knockouts, union spokes, etc.
|
||||
- Revise zone filling thermal relief support to handle new requirements.
|
||||
- Update board file format for new thermal relief requirements.
|
||||
- Add user interface support for thermal relief definitions.
|
||||
|
||||
**Dependencies:**
|
||||
- None.
|
||||
|
||||
**Status:**
|
||||
- No Progress.
|
||||
|
||||
## Merge KiCad2Step ## {#v6_pcb_kicad2step}
|
||||
**Goal:**
|
||||
|
||||
Merge export to STEP file code from KiCad2Step so that conversion does
|
||||
not run in a separate process.
|
||||
|
||||
**Task:**-
|
||||
- Merge KiCad2Step code into Pcbnew code base.
|
||||
- Remove unused parser code.
|
||||
|
||||
**Dependencies:**
|
||||
- None.
|
||||
|
||||
**Status:**
|
||||
- No Progress.
|
||||
|
||||
## 3D Model Improvements ## {#v6_pcb_3d_model_opacity}
|
||||
**Goal:**
|
||||
|
||||
Add opacity to 3D model support and convert from path look up to library
|
||||
table to access 3D models.
|
||||
|
||||
**Task:**-
|
||||
- Add opacity support to footprint library file format.
|
||||
- Add library table 3D model support to footprint library file format.
|
||||
- Create remapping utility to map from path look up to library table look up.
|
||||
- Add user interface support for 3D model opacity.
|
||||
- Add user interface support accessing 3D models via library table.
|
||||
|
||||
**Dependencies:**
|
||||
- None.
|
||||
|
||||
**Status:**
|
||||
- No Progress.
|
||||
|
||||
## IPC-2581 Support ## {#v6_pcb_ipc_2581}
|
||||
**Goal:**
|
||||
|
||||
Add support for exporting to and importing from IPC-2581.
|
||||
|
||||
**Task:**-
|
||||
- Add IPC-2581 export code.
|
||||
- Add IPC-2581 import code.
|
||||
|
||||
**Dependencies:**
|
||||
- None.
|
||||
|
||||
**Status:**
|
||||
- No Progress.
|
||||
|
||||
## Curved Trace Support ## {#v6_pcb}
|
||||
**Goal:**
|
||||
|
||||
Add curved trace support to the board editor.
|
||||
|
||||
**Task:**-
|
||||
- Add curved trace support to track object code.
|
||||
- Add support to board file format for curved traces.
|
||||
- Update zone fill algorithm to support curved fills.
|
||||
- Update router to support curved traces.
|
||||
- Update DRC to handle curved traces and fills.
|
||||
|
||||
**Dependencies:**
|
||||
- None.
|
||||
|
||||
**Status:**
|
||||
- No Progress.
|
||||
|
||||
|
||||
# GerbView: Gerber File Viewer # {#v6_gerbview}
|
||||
|
||||
This section covers the source code for the GerbView gerber file viewer.
|
||||
The road map has been moved to the
|
||||
[GitLab Wiki](https://gitlab.com/kicad/code/kicad/-/wikis/KiCad-6.0-Roadmap).
|
||||
This document is no longer maintained.
|
||||
|
|
|
|||
Loading…
Reference in New Issue