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Fix parsing of track/via user sizes from legacy boards 

Fixes https://gitlab.com/kicad/code/kicad/-/issues/6134
This commit is contained in:
Jon Evans 2021-01-26 21:51:36 -05:00
parent 30f3a7d124
commit bea310569b
4 changed files with 18 additions and 5 deletions
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5
common/settings/nested_settings.cpp
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@ -152,7 +152,7 @@ bool NESTED_SETTINGS::SaveToFile( const wxString& aDirectory, bool aForce )
}
void NESTED_SETTINGS::SetParent( JSON_SETTINGS* aParent )
void NESTED_SETTINGS::SetParent( JSON_SETTINGS* aParent, bool aLoadFromFile )
{
m_parent = aParent;
@ -161,6 +161,7 @@ void NESTED_SETTINGS::SetParent( JSON_SETTINGS* aParent )
m_parent->AddNestedSettings( this );
// In case we were created after the parent's ctor
LoadFromFile();
if( aLoadFromFile )
LoadFromFile();
}
}

2
include/settings/nested_settings.h
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@ -49,7 +49,7 @@ public:
*/
bool SaveToFile( const wxString& aDirectory = "", bool aForce = false ) override;
void SetParent( JSON_SETTINGS* aParent );
void SetParent( JSON_SETTINGS* aParent, bool aLoadFromFile = true );
JSON_SETTINGS* GetParent()
{

5
pcbnew/board.cpp
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@ -151,8 +151,9 @@ void BOARD::SetProject( PROJECT* aProject )
// Link the design settings object to the project file
project.m_BoardSettings = &GetDesignSettings();
// Set parent, which also will load the values from JSON stored in the project
project.m_BoardSettings->SetParent( &project );
// Set parent, which also will load the values from JSON stored in the project if we don't
// have legacy design settings loaded already
project.m_BoardSettings->SetParent( &project, !m_LegacyDesignSettingsLoaded );
// The DesignSettings' netclasses pointer will be pointing to its internal netclasses
// list at this point. If we loaded anything into it from a legacy board file then we

11
pcbnew/plugins/kicad/pcb_parser.cpp
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@ -1574,10 +1574,16 @@ void PCB_PARSER::parseSetup()
break;
case T_user_trace_width:
{
// Make room for the netclass value
if( designSettings.m_TrackWidthList.empty() )
designSettings.m_TrackWidthList.emplace_back( 0 );
designSettings.m_TrackWidthList.push_back( parseBoardUnits( T_user_trace_width ) );
m_board->m_LegacyDesignSettingsLoaded = true;
NeedRIGHT();
break;
}
case T_trace_clearance:
defaultNetClass->SetClearance( parseBoardUnits( T_trace_clearance ) );
@ -1656,6 +1662,11 @@ void PCB_PARSER::parseSetup()
{
int viaSize = parseBoardUnits( "user via size" );
int viaDrill = parseBoardUnits( "user via drill" );
// Make room for the netclass value
if( designSettings.m_ViasDimensionsList.empty() )
designSettings.m_ViasDimensionsList.emplace_back( VIA_DIMENSION( 0, 0 ) );
designSettings.m_ViasDimensionsList.emplace_back( VIA_DIMENSION( viaSize, viaDrill ) );
m_board->m_LegacyDesignSettingsLoaded = true;
NeedRIGHT();