Add regression tests for track cleaner.
This commit is contained in:
Jeff Young
parent
95b87ba29a
commit
c00f4ed5d2
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@ -1516,20 +1516,25 @@ bool SHAPE_POLY_SET::Collide( const SHAPE* aShape, int aClearance, int* aActual,
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{
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{
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for( const TRIANGULATED_POLYGON::TRI& tri : tpoly->Triangles() )
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for( const TRIANGULATED_POLYGON::TRI& tri : tpoly->Triangles() )
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{
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{
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int triActual;
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if( aActual || aLocation )
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VECTOR2I triLocation;
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if( aShape->Collide( &tri, aClearance, &triActual, &triLocation ) )
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{
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{
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if( !aActual && !aLocation )
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int triActual;
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return true;
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VECTOR2I triLocation;
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if( triActual < actual )
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if( aShape->Collide( &tri, aClearance, &triActual, &triLocation ) )
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{
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{
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actual = triActual;
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if( triActual < actual )
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location = triLocation;
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{
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actual = triActual;
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location = triLocation;
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}
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}
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}
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}
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}
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else // A much faster version of above
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{
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if( aShape->Collide( &tri, aClearance ) )
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return true;
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}
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}
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}
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}
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}
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,216 @@
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(kicad_pcb (version 20200119) (host pcbnew "(5.99.0-1404-g52d891940-dirty)")
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(general
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(thickness 4.62)
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(drawings 1)
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(tracks 5)
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(modules 1)
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(nets 1)
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)
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(page "A4")
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(layers
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(0 "F.Cu" signal)
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(1 "In1.Cu" signal)
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(2 "In2.Cu" signal)
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(31 "B.Cu" signal)
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(32 "B.Adhes" user)
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(33 "F.Adhes" user)
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(34 "B.Paste" user)
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(35 "F.Paste" user)
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(36 "B.SilkS" user)
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(37 "F.SilkS" user)
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(38 "B.Mask" user)
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(39 "F.Mask" user)
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(40 "Dwgs.User" user)
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(41 "Cmts.User" user)
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(42 "Eco1.User" user)
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(43 "Eco2.User" user)
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(44 "Edge.Cuts" user)
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(45 "Margin" user)
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(46 "B.CrtYd" user)
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(47 "F.CrtYd" user)
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(48 "B.Fab" user)
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(49 "F.Fab" user)
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)
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(setup
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(stackup
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(layer "F.SilkS" (type "Top Silk Screen"))
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(layer "F.Paste" (type "Top Solder Paste"))
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(layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
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(layer "F.Cu" (type "copper") (thickness 0.035))
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(layer "dielectric 1" (type "core") (thickness 1.44) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
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(layer "In1.Cu" (type "copper") (thickness 0.035))
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(layer "dielectric 2" (type "prepreg") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
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(layer "In2.Cu" (type "copper") (thickness 0.035))
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(layer "dielectric 3" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
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(layer "B.Cu" (type "copper") (thickness 0.035))
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(layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
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(layer "B.Paste" (type "Bottom Solder Paste"))
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(layer "B.SilkS" (type "Bottom Silk Screen"))
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(copper_finish "HAL lead-free")
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(dielectric_constraints no)
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)
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(last_trace_width 0.25)
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(user_trace_width 1)
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(trace_clearance 0.2)
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(zone_clearance 0.508)
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(zone_45_only no)
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(trace_min 0.2)
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(via_size 0.8)
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(via_drill 0.4)
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(via_min_size 0.4)
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(via_min_drill 0.3)
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(uvia_size 0.3)
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(uvia_drill 0.1)
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(uvias_allowed no)
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(uvia_min_size 0.2)
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(uvia_min_drill 0.1)
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(max_error 0.005)
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(defaults
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(edge_clearance 0.01)
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(edge_cuts_line_width 0.05)
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(courtyard_line_width 0.05)
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(copper_line_width 0.2)
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(copper_text_dims (size 1.5 1.5) (thickness 0.3))
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(silk_line_width 0.12)
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(silk_text_dims (size 1 1) (thickness 0.15))
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(other_layers_line_width 0.1)
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(other_layers_text_dims (size 1 1) (thickness 0.15))
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(dimension_units 0)
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(dimension_precision 1)
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)
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(pad_size 1.5 1.5)
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(pad_drill 0)
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(pad_to_mask_clearance 0.2)
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(aux_axis_origin 0 0)
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(visible_elements FFFFFF7F)
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(pcbplotparams
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(layerselection 0x01000_7ffffff9)
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(usegerberextensions false)
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(usegerberattributes false)
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(usegerberadvancedattributes false)
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(creategerberjobfile false)
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(excludeedgelayer true)
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(linewidth 0.101600)
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(plotframeref false)
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(viasonmask false)
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(mode 1)
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(useauxorigin false)
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(hpglpennumber 1)
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(hpglpenspeed 20)
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(hpglpendiameter 15.000000)
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(psnegative false)
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(psa4output false)
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(plotreference true)
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(plotvalue true)
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(plotinvisibletext false)
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(padsonsilk false)
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(subtractmaskfromsilk false)
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(outputformat 1)
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(mirror false)
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(drillshape 0)
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(scaleselection 1)
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(outputdirectory "${plot}")
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)
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)
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(net 0 "")
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(net_class "Default" "This is the default net class."
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(clearance 0.2)
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(trace_width 0.25)
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(via_dia 0.8)
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(via_drill 0.4)
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(uvia_dia 0.3)
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(uvia_drill 0.1)
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)
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(module "Housings_DIP:DIP-40_W15.24mm" (layer "F.Cu") (tedit 54130A77) (tstamp 00000000-0000-0000-0000-00005e384273)
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(at 164.719 77.597)
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(descr "40-lead dip package, row spacing 15.24 mm (600 mils)")
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(tags "dil dip 2.54 600")
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(fp_text reference "U1" (at 0 -5.22) (layer "F.SilkS")
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_text value "DIP-40_W15.24mm${stuff}" (at 0 -3.72) (layer "F.Fab")
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_text user "field on copper" (at 7.85622 26.98242 unlocked) (layer "F.Cu")
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(effects (font (size 1 1) (thickness 0.2)))
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)
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(fp_line (start 0.135 -1.025) (end -0.8 -1.025) (layer "F.SilkS") (width 0.15))
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(fp_line (start 0.135 50.555) (end 15.105 50.555) (layer "F.SilkS") (width 0.15))
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(fp_line (start 0.135 -2.295) (end 15.105 -2.295) (layer "F.SilkS") (width 0.15))
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(fp_line (start 0.135 50.555) (end 0.135 49.285) (layer "F.SilkS") (width 0.15))
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(fp_line (start 15.105 50.555) (end 15.105 49.285) (layer "F.SilkS") (width 0.15))
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(fp_line (start 15.105 -2.295) (end 15.105 -1.025) (layer "F.SilkS") (width 0.15))
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(fp_line (start 0.135 -2.295) (end 0.135 -1.025) (layer "F.SilkS") (width 0.15))
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(fp_line (start -1.05 50.75) (end 16.3 50.75) (layer "F.CrtYd") (width 0.05))
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(fp_line (start -1.05 -2.45) (end 16.3 -2.45) (layer "F.CrtYd") (width 0.05))
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(fp_line (start 16.3 -2.45) (end 16.3 50.75) (layer "F.CrtYd") (width 0.05))
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(fp_line (start -1.05 -2.45) (end -1.05 50.75) (layer "F.CrtYd") (width 0.05))
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(pad "40" thru_hole oval (at 15.24 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 3c03b006-992b-4656-8d8b-1a40717bad9b))
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(pad "39" thru_hole oval (at 15.24 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 17e4ee73-c0b6-4f16-a52f-3352b4c4a589))
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(pad "38" thru_hole oval (at 15.24 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 078e3443-d124-424c-8675-549896b6e109))
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(pad "37" thru_hole oval (at 15.24 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp c80e473b-e8f3-40b2-a34a-cb8ba2396f2c))
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(pad "36" thru_hole oval (at 15.24 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp e272137d-dd3b-4558-883f-a111afa3585b))
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(pad "35" thru_hole oval (at 15.24 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 05ee1c41-eca6-4139-9ea4-47a6d84294ba))
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(pad "34" thru_hole oval (at 15.24 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp e4636fae-e5c5-4bba-a464-4ac9b773ed47))
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(pad "33" thru_hole oval (at 15.24 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 6ed828ab-d8d8-4fe9-b16b-ebfc33e038e4))
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(pad "32" thru_hole oval (at 15.24 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 19d71dad-df19-4f33-b0e6-6c030568956a))
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(pad "31" thru_hole oval (at 15.24 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 3b8bd1af-63d2-4e0c-9197-0ad6380b78d7))
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(pad "30" thru_hole oval (at 15.24 25.4) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 3336d357-9487-4cef-80b0-4d77065fab3e))
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(pad "29" thru_hole oval (at 15.24 27.94) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 05ebfe05-f6e7-4ad1-b07f-9b049cf5b14b))
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(pad "28" thru_hole oval (at 15.24 30.48) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 24d921f2-823b-411d-a601-08992f32e566))
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(pad "27" thru_hole oval (at 15.24 33.02) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 456fa4e1-431b-49d2-a1db-9738e920f534))
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(pad "26" thru_hole oval (at 15.24 35.56) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 991a8590-8312-43da-b38f-102ea1fac869))
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(pad "25" thru_hole oval (at 15.24 38.1) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 63a7153a-fee4-461e-a81d-346402828e19))
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(pad "24" thru_hole oval (at 15.24 40.64) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp df527ce2-b732-425c-950a-a2246d2e2816))
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(pad "23" thru_hole oval (at 15.24 43.18) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 2652c9ab-ff66-4247-bb34-3a859d22dd65))
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(pad "22" thru_hole oval (at 15.24 45.72) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 1f4cc26e-f3c7-4fb3-b473-460f7b146bc1))
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(pad "21" thru_hole oval (at 15.24 48.26) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 32fe534f-83ab-48c1-bece-80fc1226c6d7))
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(pad "20" thru_hole oval (at 0 48.26) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp e876604e-ed53-40dd-9e3d-8ae62c69ec6f))
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(pad "19" thru_hole oval (at 0 45.72) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp d17f5e4d-a323-40ff-996e-9d1748ea4193))
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(pad "18" thru_hole oval (at 0 43.18) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp e0797ab1-555e-4086-945b-6adb8e80549c))
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(pad "17" thru_hole oval (at 0 40.64) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 898c11b5-3a02-432c-a417-e902595c7baa))
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(pad "16" thru_hole oval (at 0 38.1) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp ea9d9849-4c1c-4767-bc66-4a07ba4f6072))
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(pad "15" thru_hole oval (at 0 35.56) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 288bbbf0-75a5-4670-91ca-5f36d3c210d6))
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(pad "14" thru_hole oval (at 0 33.02) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 9d83fd3c-30f0-410d-b81f-c06388279e95))
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(pad "13" thru_hole oval (at 0 30.48) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 8d278dd7-c747-4010-9785-831b0766e30a))
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(pad "12" thru_hole oval (at 0 27.94) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp f0bbe286-d2de-445f-ac17-8293f5dc5a01))
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(pad "11" thru_hole oval (at 0 25.4) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp ef8288b1-8803-486f-884f-7b7ad74f6c41))
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(pad "10" thru_hole oval (at 0 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 9434a295-ac46-41d0-9f94-9671cf7b99b0))
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(pad "9" thru_hole oval (at 0 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 6ba3a876-a0b2-4c5a-b07a-0387a0d52657))
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(pad "8" thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 1382b21a-9297-41c7-95bb-c4c8a5cf04dc))
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(pad "7" thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 87e8c4e5-6cef-426d-90b6-0abce8bcec3f))
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(pad "6" thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp bc4f65fe-8685-4fe9-b6e0-f903c1e2bae5))
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(pad "5" thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 687510dd-b060-4c32-8ca8-3f1db85c0207))
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(pad "4" thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp ef6bbd64-4a61-433f-90b6-1c71e2b5ea83))
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(pad "3" thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 72b089cd-8b4d-41b2-8e3f-4222bed7df10))
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(pad "2" thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 54f38516-e465-4f36-9335-8003d6c4f47c))
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(pad "1" thru_hole oval (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 02483e4d-3ab1-489c-951b-83a16cc9b30a))
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(model "/Users/jeff/kicad/Package_QFP.3dshapes/HTQFP-64-1EP_10x10mm_P0.5mm_EP8x8mm.wrl"
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(opacity 0.6500) (offset (xyz 0 -13 0))
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(scale (xyz 1 1 1))
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(rotate (xyz 0 0 0))
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)
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(model "/Users/jeff/kicad/Package_QFP.3dshapes/TQFP-48_7x7mm_P0.5mm.wrl"
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||||||
|
(opacity 0.2100) (at (xyz 0 0 0))
|
||||||
|
(scale (xyz 1 1 1))
|
||||||
|
(rotate (xyz 0 0 0))
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(gr_text "Text: ${LAYER} ${00000000-0000-0000-0000-00005e384273:REFERENCE}" (at 151.0919 104.5464) (layer "F.Cu") (tstamp 4a940769-dbd0-4522-898c-8e905a074b1e)
|
||||||
|
(effects (font (size 1.5 1.5) (thickness 0.375)))
|
||||||
|
)
|
||||||
|
|
||||||
|
(segment (start 156.93898 86.995) (end 148.04898 86.995) (width 1) (layer "F.Cu") (net 0) (tstamp cae62b0c-d3ee-4246-bdc8-283dac6f3145))
|
||||||
|
(via (at 156.84754 86.995) (size 4) (drill 2) (layers "F.Cu" "B.Cu") (net 0) (tstamp 19ccc761-ed00-4cfc-bfdb-96decfd7b640))
|
||||||
|
(segment (start 156.845 86.995) (end 147.955 86.995) (width 1) (layer "F.Cu") (net 0) (tstamp 5b13b4cc-9d32-4a9c-92f5-295a3af198b7))
|
||||||
|
(via (at 156.845 86.995) (size 4) (drill 2) (layers "F.Cu" "B.Cu") (net 0) (tstamp 9f3db980-ce93-4ae6-813a-9832a6affc36))
|
||||||
|
(via blind (at 147.955 86.995) (size 4) (drill 2) (layers "F.Cu" "In1.Cu") (net 0) (tstamp 645cc3b2-3724-4b57-962a-a7d28e4f84a5))
|
||||||
|
|
||||||
|
)
|
||||||
|
|
@ -0,0 +1,288 @@
|
||||||
|
update=Friday 24 April 2020 at 14:38:42
|
||||||
|
version=1
|
||||||
|
last_client=kicad
|
||||||
|
[general]
|
||||||
|
version=1
|
||||||
|
RootSch=
|
||||||
|
BoardNm=
|
||||||
|
[cvpcb]
|
||||||
|
version=1
|
||||||
|
NetIExt=net
|
||||||
|
[eeschema]
|
||||||
|
version=1
|
||||||
|
LibDir=
|
||||||
|
[eeschema/libraries]
|
||||||
|
[P22LIB_TREE_MODEL_ADAPTER]
|
||||||
|
version=1
|
||||||
|
PinnedItems1=device:
|
||||||
|
[PcbFrame]
|
||||||
|
version=1
|
||||||
|
[schematic_editor]
|
||||||
|
version=1
|
||||||
|
PageLayoutDescrFile=
|
||||||
|
PlotDirectoryName=${plot}
|
||||||
|
NetFmtName=Pcbnew
|
||||||
|
SpiceAjustPassiveValues=0
|
||||||
|
SubpartIdSeparator=0
|
||||||
|
SubpartFirstId=65
|
||||||
|
LabSize=50
|
||||||
|
TextOffsetRatio=0.2
|
||||||
|
LineThickness=6
|
||||||
|
BusThickness=12
|
||||||
|
WireThickness=6
|
||||||
|
JunctionSize=30
|
||||||
|
FieldNameTemplates=(templatefields (field (name "test") visible))
|
||||||
|
ERC_TestSimilarLabels=1
|
||||||
|
ERC_CheckUniqueGlobalLabels=1
|
||||||
|
ERC_CheckBusDriverConflicts=1
|
||||||
|
ERC_CheckBusEntryConflicts=1
|
||||||
|
ERC_CheckBusToBusConflicts=1
|
||||||
|
ERC_CheckBusToNetConflicts=1
|
||||||
|
[LibeditFrame]
|
||||||
|
version=1
|
||||||
|
PinnedItems1=device
|
||||||
|
[ModEditFrame]
|
||||||
|
version=1
|
||||||
|
[SchematicFrame]
|
||||||
|
version=1
|
||||||
|
[sheetnames]
|
||||||
|
1=00000000-0000-0000-0000-00005ea2d266:
|
||||||
|
2=00000000-0000-0000-0000-00005e63adad:Untitled Sheet
|
||||||
|
3=00000000-0000-0000-0000-000001234567:right
|
||||||
|
4=00000000-0000-0000-0000-000034567890:left
|
||||||
|
[pcbnew]
|
||||||
|
version=1
|
||||||
|
PageLayoutDescrFile=
|
||||||
|
LastNetListRead=../kicad/bin/
|
||||||
|
LastSTEPExportPath=
|
||||||
|
LastIDFExportPath=
|
||||||
|
LastVRMLExportPath=
|
||||||
|
LastSpecctraDSNExportPath=
|
||||||
|
LastGenCADExportPath=
|
||||||
|
CopperLayerCount=4
|
||||||
|
BoardThickness=4.62
|
||||||
|
AllowMicroVias=0
|
||||||
|
AllowBlindVias=0
|
||||||
|
MinTrackWidth=0.2
|
||||||
|
MinViaDiameter=0.4
|
||||||
|
MinViaDrill=0.3
|
||||||
|
MinMicroViaDiameter=0.2
|
||||||
|
MinMicroViaDrill=0.09999999999999999
|
||||||
|
MinHoleToHole=0.25
|
||||||
|
RequireCourtyardDefinitions=0
|
||||||
|
ProhibitOverlappingCourtyards=1
|
||||||
|
CopperEdgeClearance=0.01
|
||||||
|
TrackWidth1=0.25
|
||||||
|
TrackWidth2=1
|
||||||
|
ViaDiameter1=0.8
|
||||||
|
ViaDrill1=0.4
|
||||||
|
dPairWidth1=0.2
|
||||||
|
dPairGap1=0.25
|
||||||
|
dPairViaGap1=0.25
|
||||||
|
SilkLineWidth=0.12
|
||||||
|
SilkTextSizeV=1
|
||||||
|
SilkTextSizeH=1
|
||||||
|
SilkTextSizeThickness=0.15
|
||||||
|
SilkTextItalic=0
|
||||||
|
SilkTextUpright=0
|
||||||
|
CopperLineWidth=0.2
|
||||||
|
CopperTextSizeV=1.5
|
||||||
|
CopperTextSizeH=1.5
|
||||||
|
CopperTextThickness=0.3
|
||||||
|
CopperTextItalic=0
|
||||||
|
CopperTextUpright=0
|
||||||
|
EdgeCutLineWidth=0.05
|
||||||
|
CourtyardLineWidth=0.05
|
||||||
|
OthersLineWidth=0.09999999999999999
|
||||||
|
OthersTextSizeV=1
|
||||||
|
OthersTextSizeH=1
|
||||||
|
OthersTextSizeThickness=0.15
|
||||||
|
OthersTextItalic=0
|
||||||
|
OthersTextUpright=0
|
||||||
|
DimensionUnits=0
|
||||||
|
DimensionPrecision=1
|
||||||
|
SolderMaskClearance=0.2
|
||||||
|
SolderMaskMinWidth=0
|
||||||
|
SolderPasteClearance=0
|
||||||
|
SolderPasteRatio=0
|
||||||
|
[pcbnew/Layer.F.Cu]
|
||||||
|
Name=F.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.In1.Cu]
|
||||||
|
Name=In1.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.In2.Cu]
|
||||||
|
Name=In2.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.In3.Cu]
|
||||||
|
Name=In3.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In4.Cu]
|
||||||
|
Name=In4.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In5.Cu]
|
||||||
|
Name=In5.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In6.Cu]
|
||||||
|
Name=In6.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In7.Cu]
|
||||||
|
Name=In7.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In8.Cu]
|
||||||
|
Name=In8.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In9.Cu]
|
||||||
|
Name=In9.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In10.Cu]
|
||||||
|
Name=In10.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In11.Cu]
|
||||||
|
Name=In11.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In12.Cu]
|
||||||
|
Name=In12.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In13.Cu]
|
||||||
|
Name=In13.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In14.Cu]
|
||||||
|
Name=In14.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In15.Cu]
|
||||||
|
Name=In15.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In16.Cu]
|
||||||
|
Name=In16.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In17.Cu]
|
||||||
|
Name=In17.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In18.Cu]
|
||||||
|
Name=In18.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In19.Cu]
|
||||||
|
Name=In19.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In20.Cu]
|
||||||
|
Name=In20.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In21.Cu]
|
||||||
|
Name=In21.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In22.Cu]
|
||||||
|
Name=In22.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In23.Cu]
|
||||||
|
Name=In23.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In24.Cu]
|
||||||
|
Name=In24.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In25.Cu]
|
||||||
|
Name=In25.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In26.Cu]
|
||||||
|
Name=In26.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In27.Cu]
|
||||||
|
Name=In27.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In28.Cu]
|
||||||
|
Name=In28.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In29.Cu]
|
||||||
|
Name=In29.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.In30.Cu]
|
||||||
|
Name=In30.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Layer.B.Cu]
|
||||||
|
Name=B.Cu
|
||||||
|
Type=0
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.B.Adhes]
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.F.Adhes]
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.B.Paste]
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.F.Paste]
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.B.SilkS]
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.F.SilkS]
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.B.Mask]
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.F.Mask]
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.Dwgs.User]
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.Cmts.User]
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.Eco1.User]
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.Eco2.User]
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.Edge.Cuts]
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.Margin]
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.B.CrtYd]
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.F.CrtYd]
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.B.Fab]
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.F.Fab]
|
||||||
|
Enabled=1
|
||||||
|
[pcbnew/Layer.Rescue]
|
||||||
|
Enabled=0
|
||||||
|
[pcbnew/Netclasses]
|
||||||
|
[pcbnew/Netclasses/Default]
|
||||||
|
Name=Default
|
||||||
|
Clearance=0.2
|
||||||
|
TrackWidth=0.25
|
||||||
|
ViaDiameter=0.8
|
||||||
|
ViaDrill=0.4
|
||||||
|
uViaDiameter=0.3
|
||||||
|
uViaDrill=0.1
|
||||||
|
dPairWidth=0.2
|
||||||
|
dPairGap=0.25
|
||||||
|
dPairViaGap=0.25
|
||||||
|
[text_variables]
|
||||||
|
1=plot:plot_files/
|
||||||
|
2=stuff:whatever you want
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,172 @@
|
||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"design_settings": {
|
||||||
|
"defaults": {
|
||||||
|
"board_outline_line_width": 0.049999999999999996,
|
||||||
|
"copper_line_width": 0.19999999999999998,
|
||||||
|
"copper_text_italic": false,
|
||||||
|
"copper_text_size_h": 1.5,
|
||||||
|
"copper_text_size_v": 1.5,
|
||||||
|
"copper_text_thickness": 0.3,
|
||||||
|
"copper_text_upright": false,
|
||||||
|
"courtyard_line_width": 0.049999999999999996,
|
||||||
|
"dimension_precision": 4,
|
||||||
|
"dimension_units": 3,
|
||||||
|
"dimensions": {
|
||||||
|
"arrow_length": 1270000,
|
||||||
|
"extension_offset": 500000,
|
||||||
|
"keep_text_aligned": true,
|
||||||
|
"suppress_zeroes": false,
|
||||||
|
"text_position": 0,
|
||||||
|
"units_format": 1
|
||||||
|
},
|
||||||
|
"fab_line_width": 0.09999999999999999,
|
||||||
|
"fab_text_italic": false,
|
||||||
|
"fab_text_size_h": 1.0,
|
||||||
|
"fab_text_size_v": 1.0,
|
||||||
|
"fab_text_thickness": 0.15,
|
||||||
|
"fab_text_upright": false,
|
||||||
|
"other_line_width": 0.09999999999999999,
|
||||||
|
"other_text_italic": false,
|
||||||
|
"other_text_size_h": 1.0,
|
||||||
|
"other_text_size_v": 1.0,
|
||||||
|
"other_text_thickness": 0.15,
|
||||||
|
"other_text_upright": false,
|
||||||
|
"pads": {
|
||||||
|
"drill": 0.762,
|
||||||
|
"height": 1.524,
|
||||||
|
"width": 1.524
|
||||||
|
},
|
||||||
|
"silk_line_width": 0.12,
|
||||||
|
"silk_text_italic": false,
|
||||||
|
"silk_text_size_h": 1.0,
|
||||||
|
"silk_text_size_v": 1.0,
|
||||||
|
"silk_text_thickness": 0.15,
|
||||||
|
"silk_text_upright": false,
|
||||||
|
"zones": {
|
||||||
|
"45_degree_only": false,
|
||||||
|
"min_clearance": 0.508
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"diff_pair_dimensions": [],
|
||||||
|
"drc_exclusions": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 2
|
||||||
|
},
|
||||||
|
"rule_severities": {
|
||||||
|
"annular_width": "error",
|
||||||
|
"clearance": "error",
|
||||||
|
"copper_edge_clearance": "error",
|
||||||
|
"courtyards_overlap": "error",
|
||||||
|
"diff_pair_gap_out_of_range": "error",
|
||||||
|
"diff_pair_uncoupled_length_too_long": "error",
|
||||||
|
"drill_out_of_range": "error",
|
||||||
|
"duplicate_footprints": "warning",
|
||||||
|
"extra_footprint": "warning",
|
||||||
|
"hole_clearance": "error",
|
||||||
|
"hole_near_hole": "error",
|
||||||
|
"invalid_outline": "error",
|
||||||
|
"item_on_disabled_layer": "error",
|
||||||
|
"items_not_allowed": "error",
|
||||||
|
"length_out_of_range": "error",
|
||||||
|
"malformed_courtyard": "error",
|
||||||
|
"microvia_drill_out_of_range": "error",
|
||||||
|
"missing_courtyard": "ignore",
|
||||||
|
"missing_footprint": "warning",
|
||||||
|
"net_conflict": "warning",
|
||||||
|
"npth_inside_courtyard": "ignore",
|
||||||
|
"padstack": "error",
|
||||||
|
"pth_inside_courtyard": "ignore",
|
||||||
|
"shorting_items": "error",
|
||||||
|
"silk_over_copper": "warning",
|
||||||
|
"silk_overlap": "warning",
|
||||||
|
"skew_out_of_range": "error",
|
||||||
|
"too_many_vias": "error",
|
||||||
|
"track_dangling": "warning",
|
||||||
|
"track_width": "error",
|
||||||
|
"tracks_crossing": "error",
|
||||||
|
"unconnected_items": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"via_dangling": "warning",
|
||||||
|
"zone_has_empty_net": "error",
|
||||||
|
"zones_intersect": "error"
|
||||||
|
},
|
||||||
|
"rules": {
|
||||||
|
"allow_blind_buried_vias": false,
|
||||||
|
"allow_microvias": false,
|
||||||
|
"max_error": 0.005,
|
||||||
|
"min_clearance": 0.0,
|
||||||
|
"min_copper_edge_clearance": 0.01,
|
||||||
|
"min_hole_clearance": 0.0,
|
||||||
|
"min_hole_to_hole": 0.25,
|
||||||
|
"min_microvia_diameter": 0.19999999999999998,
|
||||||
|
"min_microvia_drill": 0.09999999999999999,
|
||||||
|
"min_silk_clearance": 0.0,
|
||||||
|
"min_through_hole_diameter": 0.3,
|
||||||
|
"min_track_width": 0.19999999999999998,
|
||||||
|
"min_via_annular_width": 0.049999999999999996,
|
||||||
|
"min_via_diameter": 0.39999999999999997,
|
||||||
|
"use_height_for_length_calcs": true
|
||||||
|
},
|
||||||
|
"track_widths": [],
|
||||||
|
"via_dimensions": [],
|
||||||
|
"zones_allow_external_fillets": false,
|
||||||
|
"zones_use_no_outline": true
|
||||||
|
},
|
||||||
|
"layer_presets": []
|
||||||
|
},
|
||||||
|
"boards": [],
|
||||||
|
"cvpcb": {
|
||||||
|
"equivalence_files": []
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "issue6945.kicad_pro",
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.2,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.25,
|
||||||
|
"via_diameter": 0.8,
|
||||||
|
"via_drill": 0.4,
|
||||||
|
"wire_width": 6.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_colors": null
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": []
|
||||||
|
},
|
||||||
|
"sheets": [],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,172 @@
|
||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"design_settings": {
|
||||||
|
"defaults": {
|
||||||
|
"board_outline_line_width": 0.049999999999999996,
|
||||||
|
"copper_line_width": 0.19999999999999998,
|
||||||
|
"copper_text_italic": false,
|
||||||
|
"copper_text_size_h": 1.5,
|
||||||
|
"copper_text_size_v": 1.5,
|
||||||
|
"copper_text_thickness": 0.3,
|
||||||
|
"copper_text_upright": false,
|
||||||
|
"courtyard_line_width": 0.049999999999999996,
|
||||||
|
"dimension_precision": 4,
|
||||||
|
"dimension_units": 3,
|
||||||
|
"dimensions": {
|
||||||
|
"arrow_length": 1270000,
|
||||||
|
"extension_offset": 500000,
|
||||||
|
"keep_text_aligned": true,
|
||||||
|
"suppress_zeroes": false,
|
||||||
|
"text_position": 0,
|
||||||
|
"units_format": 1
|
||||||
|
},
|
||||||
|
"fab_line_width": 0.09999999999999999,
|
||||||
|
"fab_text_italic": false,
|
||||||
|
"fab_text_size_h": 1.0,
|
||||||
|
"fab_text_size_v": 1.0,
|
||||||
|
"fab_text_thickness": 0.15,
|
||||||
|
"fab_text_upright": false,
|
||||||
|
"other_line_width": 0.09999999999999999,
|
||||||
|
"other_text_italic": false,
|
||||||
|
"other_text_size_h": 1.0,
|
||||||
|
"other_text_size_v": 1.0,
|
||||||
|
"other_text_thickness": 0.15,
|
||||||
|
"other_text_upright": false,
|
||||||
|
"pads": {
|
||||||
|
"drill": 0.762,
|
||||||
|
"height": 1.524,
|
||||||
|
"width": 1.524
|
||||||
|
},
|
||||||
|
"silk_line_width": 0.12,
|
||||||
|
"silk_text_italic": false,
|
||||||
|
"silk_text_size_h": 1.0,
|
||||||
|
"silk_text_size_v": 1.0,
|
||||||
|
"silk_text_thickness": 0.15,
|
||||||
|
"silk_text_upright": false,
|
||||||
|
"zones": {
|
||||||
|
"45_degree_only": false,
|
||||||
|
"min_clearance": 0.508
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"diff_pair_dimensions": [],
|
||||||
|
"drc_exclusions": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 2
|
||||||
|
},
|
||||||
|
"rule_severities": {
|
||||||
|
"annular_width": "error",
|
||||||
|
"clearance": "error",
|
||||||
|
"copper_edge_clearance": "error",
|
||||||
|
"courtyards_overlap": "error",
|
||||||
|
"diff_pair_gap_out_of_range": "error",
|
||||||
|
"diff_pair_uncoupled_length_too_long": "error",
|
||||||
|
"drill_out_of_range": "error",
|
||||||
|
"duplicate_footprints": "warning",
|
||||||
|
"extra_footprint": "warning",
|
||||||
|
"hole_clearance": "error",
|
||||||
|
"hole_near_hole": "error",
|
||||||
|
"invalid_outline": "error",
|
||||||
|
"item_on_disabled_layer": "error",
|
||||||
|
"items_not_allowed": "error",
|
||||||
|
"length_out_of_range": "error",
|
||||||
|
"malformed_courtyard": "error",
|
||||||
|
"microvia_drill_out_of_range": "error",
|
||||||
|
"missing_courtyard": "ignore",
|
||||||
|
"missing_footprint": "warning",
|
||||||
|
"net_conflict": "warning",
|
||||||
|
"npth_inside_courtyard": "ignore",
|
||||||
|
"padstack": "error",
|
||||||
|
"pth_inside_courtyard": "ignore",
|
||||||
|
"shorting_items": "error",
|
||||||
|
"silk_over_copper": "warning",
|
||||||
|
"silk_overlap": "warning",
|
||||||
|
"skew_out_of_range": "error",
|
||||||
|
"too_many_vias": "error",
|
||||||
|
"track_dangling": "warning",
|
||||||
|
"track_width": "error",
|
||||||
|
"tracks_crossing": "error",
|
||||||
|
"unconnected_items": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"via_dangling": "warning",
|
||||||
|
"zone_has_empty_net": "error",
|
||||||
|
"zones_intersect": "error"
|
||||||
|
},
|
||||||
|
"rules": {
|
||||||
|
"allow_blind_buried_vias": false,
|
||||||
|
"allow_microvias": false,
|
||||||
|
"max_error": 0.005,
|
||||||
|
"min_clearance": 0.0,
|
||||||
|
"min_copper_edge_clearance": 0.01,
|
||||||
|
"min_hole_clearance": 0.0,
|
||||||
|
"min_hole_to_hole": 0.25,
|
||||||
|
"min_microvia_diameter": 0.19999999999999998,
|
||||||
|
"min_microvia_drill": 0.09999999999999999,
|
||||||
|
"min_silk_clearance": 0.0,
|
||||||
|
"min_through_hole_diameter": 0.3,
|
||||||
|
"min_track_width": 0.19999999999999998,
|
||||||
|
"min_via_annular_width": 0.049999999999999996,
|
||||||
|
"min_via_diameter": 0.39999999999999997,
|
||||||
|
"use_height_for_length_calcs": true
|
||||||
|
},
|
||||||
|
"track_widths": [],
|
||||||
|
"via_dimensions": [],
|
||||||
|
"zones_allow_external_fillets": false,
|
||||||
|
"zones_use_no_outline": true
|
||||||
|
},
|
||||||
|
"layer_presets": []
|
||||||
|
},
|
||||||
|
"boards": [],
|
||||||
|
"cvpcb": {
|
||||||
|
"equivalence_files": []
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "issue8003.kicad_pro",
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.2,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.25,
|
||||||
|
"via_diameter": 0.8,
|
||||||
|
"via_drill": 0.4,
|
||||||
|
"wire_width": 6.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_colors": null
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": []
|
||||||
|
},
|
||||||
|
"sheets": [],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,616 @@
|
||||||
|
(kicad_pcb (version 20210623) (generator pcbnew)
|
||||||
|
|
||||||
|
(general
|
||||||
|
(thickness 1.6)
|
||||||
|
)
|
||||||
|
|
||||||
|
(paper "A3")
|
||||||
|
(layers
|
||||||
|
(0 "F.Cu" signal)
|
||||||
|
(31 "B.Cu" signal)
|
||||||
|
(34 "B.Paste" user)
|
||||||
|
(35 "F.Paste" user)
|
||||||
|
(36 "B.SilkS" user "B.Silkscreen")
|
||||||
|
(37 "F.SilkS" user "F.Silkscreen")
|
||||||
|
(38 "B.Mask" user)
|
||||||
|
(39 "F.Mask" user)
|
||||||
|
(40 "Dwgs.User" user "User.Drawings")
|
||||||
|
(41 "Cmts.User" user "User.Comments")
|
||||||
|
(42 "Eco1.User" user "User.Eco1")
|
||||||
|
(44 "Edge.Cuts" user)
|
||||||
|
(45 "Margin" user)
|
||||||
|
(46 "B.CrtYd" user "B.Courtyard")
|
||||||
|
(47 "F.CrtYd" user "F.Courtyard")
|
||||||
|
(48 "B.Fab" user)
|
||||||
|
(49 "F.Fab" user)
|
||||||
|
)
|
||||||
|
|
||||||
|
(setup
|
||||||
|
(stackup
|
||||||
|
(layer "F.SilkS" (type "Top Silk Screen"))
|
||||||
|
(layer "F.Paste" (type "Top Solder Paste"))
|
||||||
|
(layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
|
||||||
|
(layer "F.Cu" (type "copper") (thickness 0.035))
|
||||||
|
(layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
|
||||||
|
(layer "B.Cu" (type "copper") (thickness 0.035))
|
||||||
|
(layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
|
||||||
|
(layer "B.Paste" (type "Bottom Solder Paste"))
|
||||||
|
(layer "B.SilkS" (type "Bottom Silk Screen"))
|
||||||
|
(copper_finish "None")
|
||||||
|
(dielectric_constraints no)
|
||||||
|
)
|
||||||
|
(pad_to_mask_clearance 0)
|
||||||
|
(pcbplotparams
|
||||||
|
(layerselection 0x00010fc_ffffffff)
|
||||||
|
(disableapertmacros false)
|
||||||
|
(usegerberextensions false)
|
||||||
|
(usegerberattributes true)
|
||||||
|
(usegerberadvancedattributes true)
|
||||||
|
(creategerberjobfile true)
|
||||||
|
(svguseinch false)
|
||||||
|
(svgprecision 6)
|
||||||
|
(excludeedgelayer true)
|
||||||
|
(plotframeref false)
|
||||||
|
(viasonmask false)
|
||||||
|
(mode 1)
|
||||||
|
(useauxorigin false)
|
||||||
|
(hpglpennumber 1)
|
||||||
|
(hpglpenspeed 20)
|
||||||
|
(hpglpendiameter 15.000000)
|
||||||
|
(dxfpolygonmode true)
|
||||||
|
(dxfimperialunits true)
|
||||||
|
(dxfusepcbnewfont true)
|
||||||
|
(psnegative false)
|
||||||
|
(psa4output false)
|
||||||
|
(plotreference true)
|
||||||
|
(plotvalue true)
|
||||||
|
(plotinvisibletext false)
|
||||||
|
(sketchpadsonfab false)
|
||||||
|
(subtractmaskfromsilk false)
|
||||||
|
(outputformat 1)
|
||||||
|
(mirror false)
|
||||||
|
(drillshape 1)
|
||||||
|
(scaleselection 1)
|
||||||
|
(outputdirectory "")
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(net 0 "")
|
||||||
|
(net 1 "GND")
|
||||||
|
(net 2 "ADC12_IN14")
|
||||||
|
(net 3 "+3V3")
|
||||||
|
(net 4 "ADC2_IN15")
|
||||||
|
(net 5 "ADC3_IN5")
|
||||||
|
(net 6 "unconnected-(IC2-Pad19)")
|
||||||
|
(net 7 "unconnected-(IC2-Pad18)")
|
||||||
|
(net 8 "~{RESET}")
|
||||||
|
(net 9 "Net-(C27-Pad1)")
|
||||||
|
(net 10 "Net-(C28-Pad1)")
|
||||||
|
(net 11 "unconnected-(IC2-Pad22)")
|
||||||
|
(net 12 "PA15_IN_DFM")
|
||||||
|
(net 13 "PC15_IN_PICKUP")
|
||||||
|
(net 14 "PC13_OUT_BTS723_MV")
|
||||||
|
(net 15 "PC14_OUT_BTS723_ALARM")
|
||||||
|
(net 16 "ADC12_IN1")
|
||||||
|
(net 17 "unconnected-(IC2-Pad40)")
|
||||||
|
(net 18 "ADC12_IN2")
|
||||||
|
(net 19 "USART2_TX")
|
||||||
|
(net 20 "USART2_RX")
|
||||||
|
(net 21 "SPI1_~{SS}")
|
||||||
|
(net 22 "SPI1_SCK")
|
||||||
|
(net 23 "SPI1_MISO")
|
||||||
|
(net 24 "TIM1_CH1N")
|
||||||
|
(net 25 "PB0_OUT_SM_STEP")
|
||||||
|
(net 26 "TIM8_CH3N")
|
||||||
|
(net 27 "ADC1_IN11")
|
||||||
|
(net 28 "ADC1_IN5")
|
||||||
|
(net 29 "TIM1_CH1")
|
||||||
|
(net 30 "USART1_TX")
|
||||||
|
(net 31 "USART1_RX")
|
||||||
|
(net 32 "CAN1_RX")
|
||||||
|
(net 33 "CAN1_TX")
|
||||||
|
(net 34 "SWDIO")
|
||||||
|
(net 35 "SWDCLK")
|
||||||
|
(net 36 "SPI1_MOSI")
|
||||||
|
(net 37 "CAN2_RX")
|
||||||
|
(net 38 "CAN2_TX")
|
||||||
|
(net 39 "PB7_OUT_SM_~{ENABLE}")
|
||||||
|
(net 40 "PB8_OUT__LED")
|
||||||
|
(net 41 "TIM8_CH3")
|
||||||
|
(net 42 "Net-(IC2-Pad20)")
|
||||||
|
|
||||||
|
(footprint "0IBF_Crystal:Crystal_SMD_5032-2Pin_5.0x3.2mm_IBF" (layer "F.Cu")
|
||||||
|
(tedit 60FD5043) (tstamp 0de9af20-f2c1-4152-8c27-34e4ce4bec78)
|
||||||
|
(at 106.07 -86.88 90)
|
||||||
|
(descr "SMD Crystal 5x3,2mm Quantek QC5CB / Interquip SMAC-5032 angepaßte Pads IBFEEW")
|
||||||
|
(tags "SMD crystal")
|
||||||
|
(property "Alternative" "Abracom ABM3-10.000MHZ-D2Y-T")
|
||||||
|
(property "Bemerkung" "")
|
||||||
|
(property "Farnell" "2508597")
|
||||||
|
(property "MF" "Quantek")
|
||||||
|
(property "MPN" "QC5CB10.0000F18B23M / QC5CB10.0000F18B23R")
|
||||||
|
(property "RS" "813-6097")
|
||||||
|
(property "Sheetfile" "controller.kicad_sch")
|
||||||
|
(property "Sheetname" "Controller")
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||||||
|
(property "digikey" "")
|
||||||
|
(property "mouser" "")
|
||||||
|
(path "/21ecf582-2fe5-40fc-9946-89f54de57e7c/656de130-e9e8-49cd-b55f-f52948b09214")
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(tstamp 59ee8af3-c8d3-4c23-8657-70d98fa756b6)
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||||||
|
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|
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|
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(fp_line (start -2.8 -1.7) (end -2.8 -1.6) (layer "F.SilkS") (width 0.07) (tstamp 38b9d64d-8d84-4044-8396-27fb999961a9))
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||||||
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(fp_line (start 0.1 -0.6) (end 0.1 0.6) (layer "F.SilkS") (width 0.07) (tstamp 48a896ae-a0f3-49b6-bdc7-a62b294294d4))
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(fp_line (start -0.1 -0.6) (end 0.1 -0.6) (layer "F.SilkS") (width 0.07) (tstamp 7b374b50-4b0d-4c84-8586-a22780c1d664))
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(fp_line (start 2.8 -1.7) (end -2.8 -1.7) (layer "F.SilkS") (width 0.07) (tstamp a43f91a1-116a-4d40-a54b-8d5db52826c0))
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(fp_line (start 0.2 0) (end 0.6 0) (layer "F.SilkS") (width 0.07) (tstamp a4c12ca8-54d1-4a5a-b361-295a2d47471d))
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(fp_line (start 0.2 -0.7) (end 0.2 0.7) (layer "F.SilkS") (width 0.07) (tstamp a5118d1b-d818-4c65-8549-73ad4ccf7443))
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(fp_line (start -0.1 0.6) (end -0.1 -0.6) (layer "F.SilkS") (width 0.07) (tstamp ef9e4629-ffd8-459b-9c3a-c80fc1d215ac))
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||||||
|
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||||||
|
(fp_line (start -3.2 1.9) (end 3.2 1.9) (layer "F.CrtYd") (width 0.05) (tstamp 80afb5ab-4177-4551-8787-1c944430afa5))
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||||||
|
(fp_line (start -3.2 -1.9) (end -3.2 1.9) (layer "F.CrtYd") (width 0.05) (tstamp a13bea0c-8bdc-41f7-abc8-c973b0f0538f))
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||||||
|
(fp_line (start 3.2 1.9) (end 3.2 -1.9) (layer "F.CrtYd") (width 0.05) (tstamp fcb074a8-a44c-486a-994f-f5865e99191d))
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||||||
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||||||
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(fp_line (start -0.1 -0.6) (end 0.1 -0.6) (layer "F.Fab") (width 0.07) (tstamp adb710b1-4972-41b1-b8a9-755c11c76257))
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||||||
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||||||
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(fp_line (start -2.5 0.6) (end -1.5 1.6) (layer "F.Fab") (width 0.1) (tstamp b9e98e16-fd1f-41e0-9cc1-f6952e941337))
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||||||
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(fp_line (start -2.5 1.4) (end -2.5 -1.4) (layer "F.Fab") (width 0.1) (tstamp c472a57f-95fe-4470-9816-70cb04bae7b8))
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||||||
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||||||
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(fp_line (start 0.1 -0.6) (end 0.1 0.6) (layer "F.Fab") (width 0.07) (tstamp e2fa0db0-ddb8-41a9-93e0-8aa90030f56f))
|
||||||
|
(pad "1" smd rect locked (at -2 0 90) (size 2.2 2.8) (layers "F.Cu" "F.Paste" "F.Mask")
|
||||||
|
(net 10 "Net-(C28-Pad1)") (pintype "passive") (tstamp da710f9d-5646-4d10-b982-08ce7f8a5a98))
|
||||||
|
(pad "2" smd rect locked (at 2 0 90) (size 2.2 2.8) (layers "F.Cu" "F.Paste" "F.Mask")
|
||||||
|
(net 9 "Net-(C27-Pad1)") (pintype "passive") (tstamp 4fca3028-c5d0-4de0-b6fe-98edbb026a3d))
|
||||||
|
(model "${KICAD6_USER_LIBRARY_3D}/discrete/Crystal_SMD_5032_2pin_5x3mm.stp"
|
||||||
|
(offset (xyz 0 0 0))
|
||||||
|
(scale (xyz 1 1 1))
|
||||||
|
(rotate (xyz -90 0 0))
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(footprint "0IBF_RCL:C_1206_3216Metric" (layer "F.Cu")
|
||||||
|
(tedit 60FD2F22) (tstamp 5bf3f5fe-f86e-498f-acd9-70912b60481f)
|
||||||
|
(at 104.47 -82.38 180)
|
||||||
|
(descr "Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
|
||||||
|
(tags "capacitor")
|
||||||
|
(property "Alternative" "")
|
||||||
|
(property "Bemerkung" "")
|
||||||
|
(property "Farnell" "")
|
||||||
|
(property "MF" "")
|
||||||
|
(property "MPN" "")
|
||||||
|
(property "RS" "")
|
||||||
|
(property "Sheetfile" "controller.kicad_sch")
|
||||||
|
(property "Sheetname" "Controller")
|
||||||
|
(property "digikey" "")
|
||||||
|
(property "mouser" "")
|
||||||
|
(path "/21ecf582-2fe5-40fc-9946-89f54de57e7c/8bab4fd9-c19a-40d4-a8f5-10dd898a0374")
|
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|
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|
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|
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|
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|
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|
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|
||||||
|
)
|
||||||
|
|
||||||
|
(footprint "Package_QFP:LQFP-48_7x7mm_P0.5mm" (layer "F.Cu")
|
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|
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|
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|
||||||
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(descr "LQFP, 48 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ltc2358-16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py")
|
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|
(tags "LQFP QFP")
|
||||||
|
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|
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|
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|
||||||
|
(property "Farnell" "3648858")
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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||||||
|
(fp_line (start -3.16 -3.61) (end -3.61 -3.61) (layer "F.SilkS") (width 0.12) (tstamp c59256f0-600d-4199-8b6e-ed4994afb9a0))
|
||||||
|
(fp_line (start 3.15 -5.15) (end 3.15 -3.75) (layer "F.CrtYd") (width 0.05) (tstamp 012fa6ca-4897-4c7e-9e7c-f6a4fdf5837a))
|
||||||
|
(fp_line (start -3.75 3.75) (end -3.75 3.15) (layer "F.CrtYd") (width 0.05) (tstamp 1149d8b1-dad0-4749-9e3c-53f3718f8384))
|
||||||
|
(fp_line (start 5.15 -3.15) (end 5.15 0) (layer "F.CrtYd") (width 0.05) (tstamp 1317bb3d-69e7-484a-8293-cb5063f0e326))
|
||||||
|
(fp_line (start 0 -5.15) (end -3.15 -5.15) (layer "F.CrtYd") (width 0.05) (tstamp 1ac8a3b1-aecf-4e57-a09f-aba989a27bad))
|
||||||
|
(fp_line (start -3.75 3.15) (end -5.15 3.15) (layer "F.CrtYd") (width 0.05) (tstamp 299fe656-54f5-490c-95e5-039d00b48dfb))
|
||||||
|
(fp_line (start 3.15 3.75) (end 3.75 3.75) (layer "F.CrtYd") (width 0.05) (tstamp 30f98e32-c13b-428f-a0c2-fae2cf663a2d))
|
||||||
|
(fp_line (start 5.15 3.15) (end 5.15 0) (layer "F.CrtYd") (width 0.05) (tstamp 36a2caac-f810-4f89-80a3-aab70388c16d))
|
||||||
|
(fp_line (start 0 -5.15) (end 3.15 -5.15) (layer "F.CrtYd") (width 0.05) (tstamp 46deab9f-236a-40ed-9543-5272a528f1b3))
|
||||||
|
(fp_line (start 3.15 5.15) (end 3.15 3.75) (layer "F.CrtYd") (width 0.05) (tstamp 4acdd1bb-344f-4aea-be28-2a7a396c4b27))
|
||||||
|
(fp_line (start 3.75 -3.75) (end 3.75 -3.15) (layer "F.CrtYd") (width 0.05) (tstamp 6c220254-8b7d-443c-9ddc-fa4ce7b751da))
|
||||||
|
(fp_line (start -3.75 -3.15) (end -5.15 -3.15) (layer "F.CrtYd") (width 0.05) (tstamp 7d43b51b-418a-47e8-8fb0-8ea76c8c6556))
|
||||||
|
(fp_line (start 3.75 3.75) (end 3.75 3.15) (layer "F.CrtYd") (width 0.05) (tstamp 7e4c8177-d37e-4b5e-9ef6-2b8ca64f35e1))
|
||||||
|
(fp_line (start 3.75 3.15) (end 5.15 3.15) (layer "F.CrtYd") (width 0.05) (tstamp 7ebdebad-08ae-4ef7-8399-7482fee68f45))
|
||||||
|
(fp_line (start -3.15 -5.15) (end -3.15 -3.75) (layer "F.CrtYd") (width 0.05) (tstamp 87896831-5d8c-4521-8724-bd7e758bc5f0))
|
||||||
|
(fp_line (start 0 5.15) (end -3.15 5.15) (layer "F.CrtYd") (width 0.05) (tstamp 9490bef3-623e-4df3-98e4-1ba4877a9f5f))
|
||||||
|
(fp_line (start 3.15 -3.75) (end 3.75 -3.75) (layer "F.CrtYd") (width 0.05) (tstamp 9a7efbbe-cef6-4a16-94cc-24b9c923f135))
|
||||||
|
(fp_line (start 0 5.15) (end 3.15 5.15) (layer "F.CrtYd") (width 0.05) (tstamp ab1e36d7-dea4-41d9-9336-36d4512db9e9))
|
||||||
|
(fp_line (start -3.15 -3.75) (end -3.75 -3.75) (layer "F.CrtYd") (width 0.05) (tstamp c454684a-9f60-4d46-8bf5-00f2cf2c78a7))
|
||||||
|
(fp_line (start -3.75 -3.75) (end -3.75 -3.15) (layer "F.CrtYd") (width 0.05) (tstamp c79bd622-cd92-4a96-846f-4a8e1e806975))
|
||||||
|
(fp_line (start -3.15 5.15) (end -3.15 3.75) (layer "F.CrtYd") (width 0.05) (tstamp d715a65f-32ed-4968-9170-aeaaffcba3a6))
|
||||||
|
(fp_line (start 3.75 -3.15) (end 5.15 -3.15) (layer "F.CrtYd") (width 0.05) (tstamp da669de5-264f-478f-807b-b32b7cdc4490))
|
||||||
|
(fp_line (start -5.15 -3.15) (end -5.15 0) (layer "F.CrtYd") (width 0.05) (tstamp e1806ad6-cb3f-4c1d-91ad-d20268040d85))
|
||||||
|
(fp_line (start -3.15 3.75) (end -3.75 3.75) (layer "F.CrtYd") (width 0.05) (tstamp eea2c37f-9e65-46e4-8cd1-613a33eb97ef))
|
||||||
|
(fp_line (start -5.15 3.15) (end -5.15 0) (layer "F.CrtYd") (width 0.05) (tstamp fb60249e-6a41-4a29-9ca5-75b6ecade8c4))
|
||||||
|
(fp_line (start -3.5 3.5) (end -3.5 -2.5) (layer "F.Fab") (width 0.1) (tstamp 03ea9bfd-77ae-4ae0-be1a-ee0cd6120f15))
|
||||||
|
(fp_line (start 3.5 3.5) (end -3.5 3.5) (layer "F.Fab") (width 0.1) (tstamp 646ee076-8221-4d17-8880-7fd365a872f2))
|
||||||
|
(fp_line (start 3.5 -3.5) (end 3.5 3.5) (layer "F.Fab") (width 0.1) (tstamp 7a11f02a-5924-47b3-a142-67c316d3a351))
|
||||||
|
(fp_line (start -3.5 -2.5) (end -2.5 -3.5) (layer "F.Fab") (width 0.1) (tstamp 892b195e-b8bc-4357-8433-51de0fb58e1f))
|
||||||
|
(fp_line (start -2.5 -3.5) (end 3.5 -3.5) (layer "F.Fab") (width 0.1) (tstamp eabfab10-ac5b-4298-873d-ddd2f54ded57))
|
||||||
|
(pad "1" smd roundrect locked (at -4.1625 -2.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 3 "+3V3") (pinfunction "Vbat") (pintype "input") (tstamp 5bf1cfbf-338c-4d72-84cd-e522eb0a0b71))
|
||||||
|
(pad "2" smd roundrect locked (at -4.1625 -2.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 14 "PC13_OUT_BTS723_MV") (pinfunction "PC13") (pintype "passive") (tstamp cfa3a19d-3ebd-486a-b124-73675d2745fa))
|
||||||
|
(pad "3" smd roundrect locked (at -4.1625 -1.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 15 "PC14_OUT_BTS723_ALARM") (pinfunction "PC14_OSC32") (pintype "passive") (tstamp 2bbe60b5-6b41-44d3-9b6e-bd68ac851971))
|
||||||
|
(pad "4" smd roundrect locked (at -4.1625 -1.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 13 "PC15_IN_PICKUP") (pinfunction "PC15_OSC32") (pintype "passive") (tstamp 1b969bde-7183-439b-8efd-71d27dfdd927))
|
||||||
|
(pad "5" smd roundrect locked (at -4.1625 -0.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 9 "Net-(C27-Pad1)") (pinfunction "PF0_OSC") (pintype "passive") (tstamp 51b823a2-e195-423d-b339-de02810729a7))
|
||||||
|
(pad "6" smd roundrect locked (at -4.1625 -0.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 10 "Net-(C28-Pad1)") (pinfunction "PF1_OSC") (pintype "passive") (tstamp 02f2ec88-5fe8-49db-b520-7f45aac0aa7e))
|
||||||
|
(pad "7" smd roundrect locked (at -4.1625 0.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 8 "~{RESET}") (pinfunction "PG10_~{RES}") (pintype "passive") (tstamp 012c0e72-2733-4542-a5b3-fb6993eacc9f))
|
||||||
|
(pad "8" smd roundrect locked (at -4.1625 0.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 16 "ADC12_IN1") (pinfunction "PA0") (pintype "passive") (tstamp b8415513-aee7-46f1-ac6c-03101461533f))
|
||||||
|
(pad "9" smd roundrect locked (at -4.1625 1.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 18 "ADC12_IN2") (pinfunction "PA1") (pintype "passive") (tstamp ffcadddd-c0b1-48d7-8063-5dbf1cb73b8c))
|
||||||
|
(pad "10" smd roundrect locked (at -4.1625 1.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 19 "USART2_TX") (pinfunction "PA2") (pintype "passive") (tstamp 0d6223d0-a15e-4270-ab41-cf45ff605869))
|
||||||
|
(pad "11" smd roundrect locked (at -4.1625 2.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 20 "USART2_RX") (pinfunction "PA3") (pintype "passive") (tstamp 0ed37356-a5e6-48d9-8862-7334f24c052d))
|
||||||
|
(pad "12" smd roundrect locked (at -4.1625 2.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 21 "SPI1_~{SS}") (pinfunction "PA4") (pintype "passive") (tstamp 29058b5d-ca3f-4dd7-8af2-8854ac26acd1))
|
||||||
|
(pad "13" smd roundrect locked (at -2.75 4.1625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 22 "SPI1_SCK") (pinfunction "PA5") (pintype "passive") (tstamp e70a7607-ad5c-44c8-9616-036e8cf7f514))
|
||||||
|
(pad "14" smd roundrect locked (at -2.25 4.1625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 23 "SPI1_MISO") (pinfunction "PA6") (pintype "passive") (tstamp 6e6fd987-e913-4037-8bc2-226f34363455))
|
||||||
|
(pad "15" smd roundrect locked (at -1.75 4.1625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 24 "TIM1_CH1N") (pinfunction "PA7") (pintype "passive") (tstamp ce64664b-9f33-4bb9-bcb6-72bcf3e89e2f))
|
||||||
|
(pad "16" smd roundrect locked (at -1.25 4.1625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 25 "PB0_OUT_SM_STEP") (pinfunction "PB0") (pintype "passive") (tstamp b5fa5132-6380-488b-be0c-e66514207da3))
|
||||||
|
(pad "17" smd roundrect locked (at -0.75 4.1625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 26 "TIM8_CH3N") (pinfunction "PB1") (pintype "passive") (tstamp 7c5dd425-3131-4874-989a-4ee6b01dbf04))
|
||||||
|
(pad "18" smd roundrect locked (at -0.25 4.1625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 7 "unconnected-(IC2-Pad18)") (pinfunction "PB2") (pintype "passive") (tstamp 707dbb48-8caf-4c08-9f33-880bdf6f89f8))
|
||||||
|
(pad "19" smd roundrect locked (at 0.25 4.1625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 6 "unconnected-(IC2-Pad19)") (pinfunction "VSSA") (pintype "input") (tstamp f32bca8c-2f2d-43aa-97c3-41f1f2f20f05))
|
||||||
|
(pad "20" smd roundrect locked (at 0.75 4.1625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 42 "Net-(IC2-Pad20)") (pinfunction "VRef+") (pintype "input") (tstamp 2374a396-bbac-4269-8287-b23cf7cb4fcd))
|
||||||
|
(pad "21" smd roundrect locked (at 1.25 4.1625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 42 "Net-(IC2-Pad20)") (pinfunction "Vdda") (pintype "input") (tstamp 700f2081-1a4d-468f-b358-3b02275e6554))
|
||||||
|
(pad "22" smd roundrect locked (at 1.75 4.1625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 11 "unconnected-(IC2-Pad22)") (pinfunction "PB10") (pintype "passive") (tstamp 1b216e9c-bb33-4418-aaf0-7f0c9793ee1f))
|
||||||
|
(pad "23" smd roundrect locked (at 2.25 4.1625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 1 "GND") (pinfunction "VSS/GND") (pintype "input") (tstamp e32949db-2489-4c96-9722-3f6a012d5e66))
|
||||||
|
(pad "24" smd roundrect locked (at 2.75 4.1625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 3 "+3V3") (pinfunction "Vdd") (pintype "input") (tstamp b594f538-ed79-42cf-9c7f-01fe42485b77))
|
||||||
|
(pad "25" smd roundrect locked (at 4.1625 2.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 2 "ADC12_IN14") (pinfunction "PB11") (pintype "passive") (tstamp 2c87519d-5eda-4990-81c7-773fe9e55862))
|
||||||
|
(pad "26" smd roundrect locked (at 4.1625 2.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 27 "ADC1_IN11") (pinfunction "PB12") (pintype "passive") (tstamp aab999ad-ce93-489b-878b-177cbb1ea618))
|
||||||
|
(pad "27" smd roundrect locked (at 4.1625 1.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 5 "ADC3_IN5") (pinfunction "PB13") (pintype "passive") (tstamp 196f1506-c627-4c52-b8e1-2cf2dcb6c720))
|
||||||
|
(pad "28" smd roundrect locked (at 4.1625 1.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 28 "ADC1_IN5") (pinfunction "PB14") (pintype "passive") (tstamp 5b91a2ff-0ea5-4e16-9e05-afe2091e0b9a))
|
||||||
|
(pad "29" smd roundrect locked (at 4.1625 0.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 4 "ADC2_IN15") (pinfunction "PB15") (pintype "passive") (tstamp 73633cb8-0eb2-433a-8452-dbf3758089bf))
|
||||||
|
(pad "30" smd roundrect locked (at 4.1625 0.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 29 "TIM1_CH1") (pinfunction "PA8") (pintype "passive") (tstamp 1f1543f7-f39a-4a6b-96dd-09de60a49329))
|
||||||
|
(pad "31" smd roundrect locked (at 4.1625 -0.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 30 "USART1_TX") (pinfunction "PA9") (pintype "passive") (tstamp dba97165-5dfa-44ac-bb77-1f218e8d451a))
|
||||||
|
(pad "32" smd roundrect locked (at 4.1625 -0.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 31 "USART1_RX") (pinfunction "PA10") (pintype "passive") (tstamp 3755b813-6ef1-4064-8c43-cb3e1030baa4))
|
||||||
|
(pad "33" smd roundrect locked (at 4.1625 -1.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 32 "CAN1_RX") (pinfunction "PA11") (pintype "passive") (tstamp e9b783a2-15fb-48a5-98db-a06a38874ca2))
|
||||||
|
(pad "34" smd roundrect locked (at 4.1625 -1.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 33 "CAN1_TX") (pinfunction "PA12") (pintype "passive") (tstamp e5c7c980-6c3a-4373-978f-4476ed785cf9))
|
||||||
|
(pad "35" smd roundrect locked (at 4.1625 -2.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 1 "GND") (pinfunction "VSS/GND") (pintype "input") (tstamp a6b20249-42fa-4fb7-a76f-9ebccf646c57))
|
||||||
|
(pad "36" smd roundrect locked (at 4.1625 -2.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 3 "+3V3") (pinfunction "Vdd") (pintype "input") (tstamp 2427fbc4-dab5-41f3-8c14-a57477041f14))
|
||||||
|
(pad "37" smd roundrect locked (at 2.75 -4.1625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 34 "SWDIO") (pinfunction "SWDIO_PA13") (pintype "passive") (tstamp fdd17800-9245-402e-98bc-70ca258d1d5f))
|
||||||
|
(pad "38" smd roundrect locked (at 2.25 -4.1625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 35 "SWDCLK") (pinfunction "SWDCLK_PA14") (pintype "passive") (tstamp 3558f958-08a4-48fb-8949-b03a2b12b5b5))
|
||||||
|
(pad "39" smd roundrect locked (at 1.75 -4.1625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 12 "PA15_IN_DFM") (pinfunction "PA15") (pintype "passive") (tstamp 94abcd19-8f75-4408-a9a6-541351b19985))
|
||||||
|
(pad "40" smd roundrect locked (at 1.25 -4.1625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 17 "unconnected-(IC2-Pad40)") (pinfunction "SWO_PB3") (pintype "passive") (tstamp 842b5aec-9884-461a-8192-970f81bc21a5))
|
||||||
|
(pad "41" smd roundrect locked (at 0.75 -4.1625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 36 "SPI1_MOSI") (pinfunction "PB4") (pintype "passive") (tstamp 69d51732-0cd1-4424-8159-cdcff54d8d63))
|
||||||
|
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||||||
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||||||
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(descr "Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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|
||||||
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||||||
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||||||
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|
||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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|
||||||
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||||||
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||||||
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|
||||||
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|
||||||
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||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
|
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|
||||||
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|
||||||
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|
||||||
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|
||||||
|
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
|
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|
||||||
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||||||
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||||||
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|
||||||
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||||||
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|
||||||
|
|
||||||
|
)
|
||||||
|
|
@ -0,0 +1,537 @@
|
||||||
|
{
|
||||||
|
"board": {
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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||||||
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||||||
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|
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|
||||||
|
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||||||
|
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|
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|
||||||
|
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||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
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|
||||||
|
{
|
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|
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|
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|
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|
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|
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|
||||||
|
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|
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|
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|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
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|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
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|
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|
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|
||||||
|
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|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
"track_widths": [
|
||||||
|
0.0,
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
0.4,
|
||||||
|
0.5,
|
||||||
|
0.6,
|
||||||
|
0.8,
|
||||||
|
1.0
|
||||||
|
],
|
||||||
|
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|
||||||
|
{
|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
{
|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
{
|
||||||
|
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|
||||||
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
|
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|
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|
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|
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|
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[
|
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|
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File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,172 @@
|
||||||
|
{
|
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|
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|
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|
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|
||||||
|
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|
||||||
|
"diff_pair_gap_out_of_range": "error",
|
||||||
|
"diff_pair_uncoupled_length_too_long": "error",
|
||||||
|
"drill_out_of_range": "error",
|
||||||
|
"duplicate_footprints": "warning",
|
||||||
|
"extra_footprint": "warning",
|
||||||
|
"hole_clearance": "error",
|
||||||
|
"hole_near_hole": "error",
|
||||||
|
"invalid_outline": "error",
|
||||||
|
"item_on_disabled_layer": "error",
|
||||||
|
"items_not_allowed": "error",
|
||||||
|
"length_out_of_range": "error",
|
||||||
|
"malformed_courtyard": "error",
|
||||||
|
"microvia_drill_out_of_range": "error",
|
||||||
|
"missing_courtyard": "ignore",
|
||||||
|
"missing_footprint": "warning",
|
||||||
|
"net_conflict": "warning",
|
||||||
|
"npth_inside_courtyard": "ignore",
|
||||||
|
"padstack": "error",
|
||||||
|
"pth_inside_courtyard": "ignore",
|
||||||
|
"shorting_items": "error",
|
||||||
|
"silk_over_copper": "warning",
|
||||||
|
"silk_overlap": "warning",
|
||||||
|
"skew_out_of_range": "error",
|
||||||
|
"too_many_vias": "error",
|
||||||
|
"track_dangling": "warning",
|
||||||
|
"track_width": "error",
|
||||||
|
"tracks_crossing": "error",
|
||||||
|
"unconnected_items": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"via_dangling": "warning",
|
||||||
|
"zone_has_empty_net": "error",
|
||||||
|
"zones_intersect": "error"
|
||||||
|
},
|
||||||
|
"rules": {
|
||||||
|
"allow_blind_buried_vias": false,
|
||||||
|
"allow_microvias": false,
|
||||||
|
"max_error": 0.005,
|
||||||
|
"min_clearance": 0.0,
|
||||||
|
"min_copper_edge_clearance": 0.01,
|
||||||
|
"min_hole_clearance": 0.0,
|
||||||
|
"min_hole_to_hole": 0.25,
|
||||||
|
"min_microvia_diameter": 0.19999999999999998,
|
||||||
|
"min_microvia_drill": 0.09999999999999999,
|
||||||
|
"min_silk_clearance": 0.0,
|
||||||
|
"min_through_hole_diameter": 0.3,
|
||||||
|
"min_track_width": 0.19999999999999998,
|
||||||
|
"min_via_annular_width": 0.049999999999999996,
|
||||||
|
"min_via_diameter": 0.39999999999999997,
|
||||||
|
"use_height_for_length_calcs": true
|
||||||
|
},
|
||||||
|
"track_widths": [],
|
||||||
|
"via_dimensions": [],
|
||||||
|
"zones_allow_external_fillets": false,
|
||||||
|
"zones_use_no_outline": true
|
||||||
|
},
|
||||||
|
"layer_presets": []
|
||||||
|
},
|
||||||
|
"boards": [],
|
||||||
|
"cvpcb": {
|
||||||
|
"equivalence_files": []
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "issue8909.kicad_pro",
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.2,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.25,
|
||||||
|
"via_diameter": 0.8,
|
||||||
|
"via_drill": 0.4,
|
||||||
|
"wire_width": 6.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_colors": null
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": []
|
||||||
|
},
|
||||||
|
"sheets": [],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
||||||
|
|
@ -37,6 +37,7 @@ set( QA_PCBNEW_SRCS
|
||||||
test_lset.cpp
|
test_lset.cpp
|
||||||
test_pad_naming.cpp
|
test_pad_naming.cpp
|
||||||
test_libeval_compiler.cpp
|
test_libeval_compiler.cpp
|
||||||
|
test_tracks_cleaner.cpp
|
||||||
test_zone_filler.cpp
|
test_zone_filler.cpp
|
||||||
|
|
||||||
drc/test_drc_courtyard_invalid.cpp
|
drc/test_drc_courtyard_invalid.cpp
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,7 @@
|
||||||
/*
|
/*
|
||||||
* This program source code file is part of KiCad, a free EDA CAD application.
|
* This program source code file is part of KiCad, a free EDA CAD application.
|
||||||
*
|
*
|
||||||
* Copyright (C) 2019 KiCad Developers, see AUTHORS.txt for contributors.
|
* Copyright (C) 2019-2021 KiCad Developers, see AUTHORS.txt for contributors.
|
||||||
*
|
*
|
||||||
* This program is free software; you can redistribute it and/or
|
* This program is free software; you can redistribute it and/or
|
||||||
* modify it under the terms of the GNU General Public License
|
* modify it under the terms of the GNU General Public License
|
||||||
|
|
@ -23,17 +23,24 @@
|
||||||
|
|
||||||
#include "board_test_utils.h"
|
#include "board_test_utils.h"
|
||||||
|
|
||||||
|
#include <wx/filename.h>
|
||||||
|
#include <board.h>
|
||||||
|
#include <board_design_settings.h>
|
||||||
|
#include <settings/settings_manager.h>
|
||||||
#include <pcbnew_utils/board_file_utils.h>
|
#include <pcbnew_utils/board_file_utils.h>
|
||||||
|
#include <tool/tool_manager.h>
|
||||||
|
#include <zone_filler.h>
|
||||||
|
|
||||||
// For the temp directory logic: can be std::filesystem in C++17
|
// For the temp directory logic: can be std::filesystem in C++17
|
||||||
#include <boost/filesystem.hpp>
|
#include <boost/filesystem.hpp>
|
||||||
#include <boost/test/unit_test.hpp>
|
#include <boost/test/unit_test.hpp>
|
||||||
|
#include <board_commit.h>
|
||||||
|
|
||||||
namespace KI_TEST
|
namespace KI_TEST
|
||||||
{
|
{
|
||||||
|
|
||||||
BOARD_DUMPER::BOARD_DUMPER() : m_dump_boards( std::getenv( "KICAD_TEST_DUMP_BOARD_FILES" ) )
|
BOARD_DUMPER::BOARD_DUMPER() :
|
||||||
|
m_dump_boards( std::getenv( "KICAD_TEST_DUMP_BOARD_FILES" ) )
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -50,4 +57,60 @@ void BOARD_DUMPER::DumpBoardToFile( BOARD& aBoard, const std::string& aName ) co
|
||||||
::KI_TEST::DumpBoardToFile( aBoard, path.string() );
|
::KI_TEST::DumpBoardToFile( aBoard, path.string() );
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void LoadBoard( SETTINGS_MANAGER& aSettingsManager, const wxString& aRelPath,
|
||||||
|
std::unique_ptr<BOARD>& aBoard )
|
||||||
|
{
|
||||||
|
if( aBoard )
|
||||||
|
{
|
||||||
|
aBoard->SetProject( nullptr );
|
||||||
|
aBoard = nullptr;
|
||||||
|
}
|
||||||
|
|
||||||
|
std::string absPath = GetPcbnewTestDataDir() + aRelPath.ToStdString();
|
||||||
|
wxFileName projectFile( absPath + ".kicad_pro" );
|
||||||
|
wxFileName legacyProject( absPath + ".pro" );
|
||||||
|
std::string boardPath = absPath + ".kicad_pcb";
|
||||||
|
wxFileName rulesFile( absPath + ".kicad_dru" );
|
||||||
|
|
||||||
|
if( projectFile.Exists() )
|
||||||
|
aSettingsManager.LoadProject( projectFile.GetFullPath() );
|
||||||
|
else if( legacyProject.Exists() )
|
||||||
|
aSettingsManager.LoadProject( legacyProject.GetFullPath() );
|
||||||
|
|
||||||
|
aBoard = ReadBoardFromFileOrStream( boardPath );
|
||||||
|
|
||||||
|
if( projectFile.Exists() || legacyProject.Exists() )
|
||||||
|
aBoard->SetProject( &aSettingsManager.Prj() );
|
||||||
|
|
||||||
|
auto m_DRCEngine = std::make_shared<DRC_ENGINE>( aBoard.get(), &aBoard->GetDesignSettings() );
|
||||||
|
|
||||||
|
if( rulesFile.Exists() )
|
||||||
|
m_DRCEngine->InitEngine( rulesFile );
|
||||||
|
else
|
||||||
|
m_DRCEngine->InitEngine( wxFileName() );
|
||||||
|
|
||||||
|
aBoard->GetDesignSettings().m_DRCEngine = m_DRCEngine;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void FillZones( BOARD* m_board, int aFillVersion )
|
||||||
|
{
|
||||||
|
TOOL_MANAGER toolMgr;
|
||||||
|
toolMgr.SetEnvironment( m_board, nullptr, nullptr, nullptr, nullptr );
|
||||||
|
|
||||||
|
BOARD_COMMIT commit( &toolMgr );
|
||||||
|
ZONE_FILLER filler( m_board, &commit );
|
||||||
|
std::vector<ZONE*> toFill;
|
||||||
|
|
||||||
|
m_board->GetDesignSettings().m_ZoneFillVersion = aFillVersion;
|
||||||
|
|
||||||
|
for( ZONE* zone : m_board->Zones() )
|
||||||
|
toFill.push_back( zone );
|
||||||
|
|
||||||
|
if( filler.Fill( toFill, false, nullptr ) )
|
||||||
|
commit.Push( _( "Fill Zone(s)" ), false, false );
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
} // namespace KI_TEST
|
} // namespace KI_TEST
|
||||||
|
|
@ -1,7 +1,7 @@
|
||||||
/*
|
/*
|
||||||
* This program source code file is part of KiCad, a free EDA CAD application.
|
* This program source code file is part of KiCad, a free EDA CAD application.
|
||||||
*
|
*
|
||||||
* Copyright (C) 2019 KiCad Developers, see AUTHORS.txt for contributors.
|
* Copyright (C) 2019-2021 KiCad Developers, see AUTHORS.txt for contributors.
|
||||||
*
|
*
|
||||||
* This program is free software; you can redistribute it and/or
|
* This program is free software; you can redistribute it and/or
|
||||||
* modify it under the terms of the GNU General Public License
|
* modify it under the terms of the GNU General Public License
|
||||||
|
|
@ -21,18 +21,16 @@
|
||||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
|
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
|
||||||
* @file board_test_utils.h
|
|
||||||
* General utilities for PCB tests
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef QA_PCBNEW_BOARD_TEST_UTILS__H
|
#ifndef QA_PCBNEW_BOARD_TEST_UTILS__H
|
||||||
#define QA_PCBNEW_BOARD_TEST_UTILS__H
|
#define QA_PCBNEW_BOARD_TEST_UTILS__H
|
||||||
|
|
||||||
#include <string>
|
#include <string>
|
||||||
|
#include <wx/string.h>
|
||||||
|
|
||||||
class BOARD;
|
class BOARD;
|
||||||
class BOARD_ITEM;
|
class BOARD_ITEM;
|
||||||
|
class SETTINGS_MANAGER;
|
||||||
|
|
||||||
|
|
||||||
namespace KI_TEST
|
namespace KI_TEST
|
||||||
|
|
@ -58,6 +56,13 @@ public:
|
||||||
const bool m_dump_boards;
|
const bool m_dump_boards;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
|
void LoadBoard( SETTINGS_MANAGER& aSettingsManager, const wxString& aRelPath,
|
||||||
|
std::unique_ptr<BOARD>& aBoard );
|
||||||
|
|
||||||
|
void FillZones( BOARD* m_board, int aFillVersion );
|
||||||
|
|
||||||
|
|
||||||
} // namespace KI_TEST
|
} // namespace KI_TEST
|
||||||
|
|
||||||
#endif // QA_PCBNEW_BOARD_TEST_UTILS__H
|
#endif // QA_PCBNEW_BOARD_TEST_UTILS__H
|
||||||
|
|
@ -1,7 +1,7 @@
|
||||||
/*
|
/*
|
||||||
* This program source code file is part of KiCad, a free EDA CAD application.
|
* This program source code file is part of KiCad, a free EDA CAD application.
|
||||||
*
|
*
|
||||||
* Copyright (C) 201 KiCad Developers, see AUTHORS.txt for contributors.
|
* Copyright (C) 2021 KiCad Developers, see AUTHORS.txt for contributors.
|
||||||
*
|
*
|
||||||
* This program is free software; you can redistribute it and/or
|
* This program is free software; you can redistribute it and/or
|
||||||
* modify it under the terms of the GNU General Public License
|
* modify it under the terms of the GNU General Public License
|
||||||
|
|
@ -21,12 +21,8 @@
|
||||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
|
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <string>
|
|
||||||
|
|
||||||
#include <wx/toplevel.h>
|
|
||||||
|
|
||||||
#include <qa_utils/wx_utils/unit_test_utils.h>
|
#include <qa_utils/wx_utils/unit_test_utils.h>
|
||||||
#include <pcbnew_utils/board_file_utils.h>
|
#include <qa/pcbnew/board_test_utils.h>
|
||||||
#include <board.h>
|
#include <board.h>
|
||||||
#include <board_design_settings.h>
|
#include <board_design_settings.h>
|
||||||
#include <pad.h>
|
#include <pad.h>
|
||||||
|
|
@ -34,80 +30,20 @@
|
||||||
#include <footprint.h>
|
#include <footprint.h>
|
||||||
#include <drc/drc_item.h>
|
#include <drc/drc_item.h>
|
||||||
#include <drc/drc_engine.h>
|
#include <drc/drc_engine.h>
|
||||||
#include <zone_filler.h>
|
|
||||||
#include <board_commit.h>
|
|
||||||
#include <tool/tool_manager.h>
|
|
||||||
#include <zone_filler_tool.h>
|
|
||||||
#include <settings/settings_manager.h>
|
#include <settings/settings_manager.h>
|
||||||
|
|
||||||
|
|
||||||
struct DRC_REGRESSION_TEST_FIXTURE
|
struct DRC_REGRESSION_TEST_FIXTURE
|
||||||
{
|
{
|
||||||
DRC_REGRESSION_TEST_FIXTURE() :
|
DRC_REGRESSION_TEST_FIXTURE() :
|
||||||
m_settingsManager( true /* headless */ )
|
m_settingsManager( true /* headless */ )
|
||||||
{
|
{ }
|
||||||
}
|
|
||||||
|
|
||||||
void loadBoard( const wxString& relPath )
|
SETTINGS_MANAGER m_settingsManager;
|
||||||
{
|
std::unique_ptr<BOARD> m_board;
|
||||||
if( m_board )
|
|
||||||
{
|
|
||||||
m_board->SetProject( nullptr );
|
|
||||||
m_board = nullptr;
|
|
||||||
}
|
|
||||||
|
|
||||||
std::string absPath = KI_TEST::GetPcbnewTestDataDir() + relPath.ToStdString();
|
|
||||||
wxFileName projectFile( absPath + ".kicad_pro" );
|
|
||||||
std::string boardPath = absPath + ".kicad_pcb";
|
|
||||||
wxFileName rulesFile( absPath + ".kicad_dru" );
|
|
||||||
|
|
||||||
if( projectFile.Exists() )
|
|
||||||
m_settingsManager.LoadProject( projectFile.GetFullPath() );
|
|
||||||
|
|
||||||
m_board = KI_TEST::ReadBoardFromFileOrStream( boardPath );
|
|
||||||
|
|
||||||
if( projectFile.Exists() )
|
|
||||||
m_board->SetProject( &m_settingsManager.Prj() );
|
|
||||||
|
|
||||||
m_DRCEngine = std::make_shared<DRC_ENGINE>( m_board.get(), &m_board->GetDesignSettings() );
|
|
||||||
|
|
||||||
if( rulesFile.Exists() )
|
|
||||||
m_DRCEngine->InitEngine( rulesFile );
|
|
||||||
else
|
|
||||||
m_DRCEngine->InitEngine( wxFileName() );
|
|
||||||
|
|
||||||
m_board->GetDesignSettings().m_DRCEngine = m_DRCEngine;
|
|
||||||
|
|
||||||
m_toolMgr = std::make_unique<TOOL_MANAGER>();
|
|
||||||
m_toolMgr->SetEnvironment( m_board.get(), nullptr, nullptr, nullptr, nullptr );
|
|
||||||
}
|
|
||||||
|
|
||||||
void fillZones( int aFillVersion )
|
|
||||||
{
|
|
||||||
BOARD_COMMIT commit( m_toolMgr.get() );
|
|
||||||
ZONE_FILLER filler( m_board.get(), &commit );
|
|
||||||
std::vector<ZONE*> toFill;
|
|
||||||
|
|
||||||
m_board->GetDesignSettings().m_ZoneFillVersion = aFillVersion;
|
|
||||||
|
|
||||||
for( ZONE* zone : m_board->Zones() )
|
|
||||||
toFill.push_back( zone );
|
|
||||||
|
|
||||||
if( filler.Fill( toFill, false, nullptr ) )
|
|
||||||
commit.Push( _( "Fill Zone(s)" ), false, false );
|
|
||||||
}
|
|
||||||
|
|
||||||
SETTINGS_MANAGER m_settingsManager;
|
|
||||||
|
|
||||||
std::unique_ptr<BOARD> m_board;
|
|
||||||
std::unique_ptr<TOOL_MANAGER> m_toolMgr;
|
|
||||||
std::shared_ptr<DRC_ENGINE> m_DRCEngine;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
constexpr int delta = KiROUND( 0.006 * IU_PER_MM );
|
|
||||||
|
|
||||||
|
|
||||||
BOOST_FIXTURE_TEST_CASE( DRCFalsePositiveRegressions, DRC_REGRESSION_TEST_FIXTURE )
|
BOOST_FIXTURE_TEST_CASE( DRCFalsePositiveRegressions, DRC_REGRESSION_TEST_FIXTURE )
|
||||||
{
|
{
|
||||||
// These documents at one time flagged DRC errors that they shouldn't have.
|
// These documents at one time flagged DRC errors that they shouldn't have.
|
||||||
|
|
@ -123,8 +59,8 @@ BOOST_FIXTURE_TEST_CASE( DRCFalsePositiveRegressions, DRC_REGRESSION_TEST_FIXTUR
|
||||||
|
|
||||||
for( const wxString& relPath : tests )
|
for( const wxString& relPath : tests )
|
||||||
{
|
{
|
||||||
loadBoard( relPath );
|
KI_TEST::LoadBoard( m_settingsManager, relPath, m_board );
|
||||||
fillZones( 6 );
|
KI_TEST::FillZones( m_board.get(), 6 );
|
||||||
|
|
||||||
std::vector<DRC_ITEM> violations;
|
std::vector<DRC_ITEM> violations;
|
||||||
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
|
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
|
||||||
|
|
@ -132,17 +68,18 @@ BOOST_FIXTURE_TEST_CASE( DRCFalsePositiveRegressions, DRC_REGRESSION_TEST_FIXTUR
|
||||||
bds.m_DRCSeverities[ DRCE_INVALID_OUTLINE ] = SEVERITY::RPT_SEVERITY_IGNORE;
|
bds.m_DRCSeverities[ DRCE_INVALID_OUTLINE ] = SEVERITY::RPT_SEVERITY_IGNORE;
|
||||||
bds.m_DRCSeverities[ DRCE_UNCONNECTED_ITEMS ] = SEVERITY::RPT_SEVERITY_IGNORE;
|
bds.m_DRCSeverities[ DRCE_UNCONNECTED_ITEMS ] = SEVERITY::RPT_SEVERITY_IGNORE;
|
||||||
|
|
||||||
m_DRCEngine->SetViolationHandler(
|
bds.m_DRCEngine->SetViolationHandler(
|
||||||
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
||||||
{
|
{
|
||||||
if( bds.GetSeverity( aItem->GetErrorCode() ) == SEVERITY::RPT_SEVERITY_ERROR )
|
if( bds.GetSeverity( aItem->GetErrorCode() ) == SEVERITY::RPT_SEVERITY_ERROR )
|
||||||
violations.push_back( *aItem );
|
violations.push_back( *aItem );
|
||||||
} );
|
} );
|
||||||
|
|
||||||
m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
bds.m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||||
|
|
||||||
if( violations.empty() )
|
if( violations.empty() )
|
||||||
{
|
{
|
||||||
|
BOOST_CHECK_EQUAL( 1, 1 ); // quiet "did not check any assertions" warning
|
||||||
BOOST_TEST_MESSAGE( wxString::Format( "DRC regression: %s, passed", relPath ) );
|
BOOST_TEST_MESSAGE( wxString::Format( "DRC regression: %s, passed", relPath ) );
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
|
|
@ -179,22 +116,23 @@ BOOST_FIXTURE_TEST_CASE( DRCFalseNegativeRegressions, DRC_REGRESSION_TEST_FIXTUR
|
||||||
|
|
||||||
for( const std::pair<wxString, int>& entry : tests )
|
for( const std::pair<wxString, int>& entry : tests )
|
||||||
{
|
{
|
||||||
loadBoard( entry.first );
|
KI_TEST::LoadBoard( m_settingsManager, entry.first, m_board );
|
||||||
fillZones( 6 );
|
KI_TEST::FillZones( m_board.get(), 6 );
|
||||||
|
|
||||||
std::vector<DRC_ITEM> violations;
|
std::vector<DRC_ITEM> violations;
|
||||||
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
|
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
|
||||||
|
|
||||||
m_DRCEngine->SetViolationHandler(
|
bds.m_DRCEngine->SetViolationHandler(
|
||||||
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
||||||
{
|
{
|
||||||
violations.push_back( *aItem );
|
violations.push_back( *aItem );
|
||||||
} );
|
} );
|
||||||
|
|
||||||
m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
bds.m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||||
|
|
||||||
if( violations.size() == entry.second )
|
if( violations.size() == entry.second )
|
||||||
{
|
{
|
||||||
|
BOOST_CHECK_EQUAL( 1, 1 ); // quiet "did not check any assertions" warning
|
||||||
BOOST_TEST_MESSAGE( wxString::Format( "DRC regression: %s, passed", entry.first ) );
|
BOOST_TEST_MESSAGE( wxString::Format( "DRC regression: %s, passed", entry.first ) );
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,204 @@
|
||||||
|
/*
|
||||||
|
* This program source code file is part of KiCad, a free EDA CAD application.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2021 KiCad Developers, see AUTHORS.txt for contributors.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License
|
||||||
|
* as published by the Free Software Foundation; either version 2
|
||||||
|
* of the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, you may find one here:
|
||||||
|
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
|
||||||
|
* or you may search the http://www.gnu.org website for the version 2 license,
|
||||||
|
* or you may write to the Free Software Foundation, Inc.,
|
||||||
|
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <qa_utils/wx_utils/unit_test_utils.h>
|
||||||
|
#include <qa/pcbnew/board_test_utils.h>
|
||||||
|
#include <board.h>
|
||||||
|
#include <board_commit.h>
|
||||||
|
#include <board_design_settings.h>
|
||||||
|
#include <connectivity/connectivity_data.h>
|
||||||
|
#include <tracks_cleaner.h>
|
||||||
|
#include <cleanup_item.h>
|
||||||
|
#include <drc/drc_item.h>
|
||||||
|
#include <drc/drc_engine.h>
|
||||||
|
#include <settings/settings_manager.h>
|
||||||
|
#include <tool/tool_manager.h>
|
||||||
|
|
||||||
|
struct TRACK_CLEANER_TEST_FIXTURE
|
||||||
|
{
|
||||||
|
TRACK_CLEANER_TEST_FIXTURE() :
|
||||||
|
m_settingsManager( true /* headless */ )
|
||||||
|
{ }
|
||||||
|
|
||||||
|
SETTINGS_MANAGER m_settingsManager;
|
||||||
|
std::unique_ptr<BOARD> m_board;
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
struct TEST_DESCRIPTION
|
||||||
|
{
|
||||||
|
wxString m_File;
|
||||||
|
bool m_Shorts;
|
||||||
|
bool m_RedundantVias;
|
||||||
|
bool m_RedundantTracks;
|
||||||
|
bool m_DanglingTracks;
|
||||||
|
bool m_TracksInPads;
|
||||||
|
bool m_DanglingVias;
|
||||||
|
int m_Expected;
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
BOOST_FIXTURE_TEST_CASE( FailedToCleanRegressionTests, TRACK_CLEANER_TEST_FIXTURE )
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* This one ensures that certain cleanup items are indeed found and marked for cleanup.
|
||||||
|
*/
|
||||||
|
std::vector<TEST_DESCRIPTION> tests =
|
||||||
|
{
|
||||||
|
// short redundant redundant dangling tracks dangling
|
||||||
|
// circuits vias tracks tracks in pads vias expected
|
||||||
|
{ "issue2904", false, false, false, true, false, false, 6 },
|
||||||
|
{ "issue5093", false, false, false, false, true, false, 118 },
|
||||||
|
{ "issue7004", false, true, false, false, false, true, 25 },
|
||||||
|
{ "issue8883", true, true, true, true, false, true, 80 }
|
||||||
|
};
|
||||||
|
|
||||||
|
for( const TEST_DESCRIPTION& entry : tests )
|
||||||
|
{
|
||||||
|
KI_TEST::LoadBoard( m_settingsManager, entry.m_File, m_board );
|
||||||
|
KI_TEST::FillZones( m_board.get(), 6 );
|
||||||
|
m_board->GetConnectivity()->RecalculateRatsnest();
|
||||||
|
|
||||||
|
TOOL_MANAGER toolMgr;
|
||||||
|
toolMgr.SetEnvironment( m_board.get(), nullptr, nullptr, nullptr, nullptr );
|
||||||
|
|
||||||
|
BOARD_COMMIT commit( &toolMgr );
|
||||||
|
TRACKS_CLEANER cleaner( m_board.get(), commit );
|
||||||
|
std::vector< std::shared_ptr<CLEANUP_ITEM> > dryRunItems;
|
||||||
|
std::vector< std::shared_ptr<CLEANUP_ITEM> > realRunItems;
|
||||||
|
|
||||||
|
cleaner.CleanupBoard( true, &dryRunItems, entry.m_Shorts,
|
||||||
|
entry.m_RedundantVias,
|
||||||
|
entry.m_RedundantTracks,
|
||||||
|
entry.m_DanglingTracks,
|
||||||
|
entry.m_TracksInPads,
|
||||||
|
entry.m_DanglingVias );
|
||||||
|
|
||||||
|
cleaner.CleanupBoard( true, &realRunItems, entry.m_Shorts,
|
||||||
|
entry.m_RedundantVias,
|
||||||
|
entry.m_RedundantTracks,
|
||||||
|
entry.m_DanglingTracks,
|
||||||
|
entry.m_TracksInPads,
|
||||||
|
entry.m_DanglingVias );
|
||||||
|
|
||||||
|
if( dryRunItems.size() == entry.m_Expected && realRunItems.size() == entry.m_Expected )
|
||||||
|
{
|
||||||
|
BOOST_CHECK_EQUAL( 1, 1 ); // quiet "did not check any assertions" warning
|
||||||
|
BOOST_TEST_MESSAGE( wxString::Format( "Track cleaner regression: %s, passed",
|
||||||
|
entry.m_File ) );
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
BOOST_CHECK_EQUAL( dryRunItems.size(), entry.m_Expected );
|
||||||
|
BOOST_CHECK_EQUAL( realRunItems.size(), entry.m_Expected );
|
||||||
|
|
||||||
|
std::map<KIID, EDA_ITEM*> itemMap;
|
||||||
|
m_board->FillItemMap( itemMap );
|
||||||
|
|
||||||
|
for( const std::shared_ptr<CLEANUP_ITEM>& item : realRunItems )
|
||||||
|
{
|
||||||
|
BOOST_TEST_MESSAGE( item->ShowReport( EDA_UNITS::INCHES, RPT_SEVERITY_ERROR,
|
||||||
|
itemMap ) );
|
||||||
|
}
|
||||||
|
|
||||||
|
BOOST_ERROR( wxString::Format( "Track cleaner regression: %s, failed",
|
||||||
|
entry.m_File ) );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
BOOST_FIXTURE_TEST_CASE( TrackCleanerRegressionTests, TRACK_CLEANER_TEST_FIXTURE )
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* This one just makes sure that the dry-run counts agree with the "real" counts, and that
|
||||||
|
* the cleaning doesn't produce any connectivity changes.
|
||||||
|
*/
|
||||||
|
std::vector<wxString> tests = { "issue832",
|
||||||
|
"issue4257",
|
||||||
|
"issue8909" };
|
||||||
|
|
||||||
|
for( const wxString& relPath : tests )
|
||||||
|
{
|
||||||
|
KI_TEST::LoadBoard( m_settingsManager, relPath, m_board );
|
||||||
|
KI_TEST::FillZones( m_board.get(), 6 );
|
||||||
|
m_board->GetConnectivity()->RecalculateRatsnest();
|
||||||
|
|
||||||
|
TOOL_MANAGER toolMgr;
|
||||||
|
toolMgr.SetEnvironment( m_board.get(), nullptr, nullptr, nullptr, nullptr );
|
||||||
|
|
||||||
|
BOARD_COMMIT commit( &toolMgr );
|
||||||
|
TRACKS_CLEANER cleaner( m_board.get(), commit );
|
||||||
|
std::vector< std::shared_ptr<CLEANUP_ITEM> > dryRunItems;
|
||||||
|
std::vector< std::shared_ptr<CLEANUP_ITEM> > realRunItems;
|
||||||
|
|
||||||
|
cleaner.CleanupBoard( true, &dryRunItems, true, // short circuits
|
||||||
|
true, // redundant vias
|
||||||
|
true, // redundant tracks
|
||||||
|
true, // dangling tracks
|
||||||
|
true, // tracks in pads
|
||||||
|
true ); // dangling vias
|
||||||
|
|
||||||
|
cleaner.CleanupBoard( true, &realRunItems, true, // short circuits
|
||||||
|
true, // redundant vias
|
||||||
|
true, // redundant tracks
|
||||||
|
true, // dangling tracks
|
||||||
|
true, // tracks in pads
|
||||||
|
true ); // dangling vias
|
||||||
|
|
||||||
|
BOOST_CHECK_EQUAL( dryRunItems.size(), realRunItems.size() );
|
||||||
|
|
||||||
|
std::vector<DRC_ITEM> violations;
|
||||||
|
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
|
||||||
|
|
||||||
|
bds.m_DRCEngine->SetViolationHandler(
|
||||||
|
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
||||||
|
{
|
||||||
|
if( aItem->GetErrorCode() == DRCE_UNCONNECTED_ITEMS )
|
||||||
|
violations.push_back( *aItem );
|
||||||
|
} );
|
||||||
|
|
||||||
|
bds.m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||||
|
|
||||||
|
if( violations.empty() )
|
||||||
|
{
|
||||||
|
BOOST_TEST_MESSAGE( wxString::Format( "Track cleaner regression: %s, passed",
|
||||||
|
relPath ) );
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
std::map<KIID, EDA_ITEM*> itemMap;
|
||||||
|
m_board->FillItemMap( itemMap );
|
||||||
|
|
||||||
|
for( const DRC_ITEM& item : violations )
|
||||||
|
{
|
||||||
|
BOOST_TEST_MESSAGE( item.ShowReport( EDA_UNITS::INCHES, RPT_SEVERITY_ERROR,
|
||||||
|
itemMap ) );
|
||||||
|
}
|
||||||
|
|
||||||
|
BOOST_ERROR( wxString::Format( "Track cleaner regression: %s, failed",
|
||||||
|
relPath ) );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -1,7 +1,7 @@
|
||||||
/*
|
/*
|
||||||
* This program source code file is part of KiCad, a free EDA CAD application.
|
* This program source code file is part of KiCad, a free EDA CAD application.
|
||||||
*
|
*
|
||||||
* Copyright (C) 201 KiCad Developers, see AUTHORS.txt for contributors.
|
* Copyright (C) 2021 KiCad Developers, see AUTHORS.txt for contributors.
|
||||||
*
|
*
|
||||||
* This program is free software; you can redistribute it and/or
|
* This program is free software; you can redistribute it and/or
|
||||||
* modify it under the terms of the GNU General Public License
|
* modify it under the terms of the GNU General Public License
|
||||||
|
|
@ -21,86 +21,27 @@
|
||||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
|
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <string>
|
|
||||||
|
|
||||||
#include <wx/toplevel.h>
|
|
||||||
|
|
||||||
#include <qa_utils/wx_utils/unit_test_utils.h>
|
#include <qa_utils/wx_utils/unit_test_utils.h>
|
||||||
#include <pcbnew_utils/board_file_utils.h>
|
#include <qa/pcbnew/board_test_utils.h>
|
||||||
#include <board.h>
|
#include <board.h>
|
||||||
#include <board_design_settings.h>
|
#include <board_design_settings.h>
|
||||||
#include <pad.h>
|
#include <pad.h>
|
||||||
#include <pcb_track.h>
|
#include <pcb_track.h>
|
||||||
#include <footprint.h>
|
#include <footprint.h>
|
||||||
|
#include <zone.h>
|
||||||
#include <drc/drc_item.h>
|
#include <drc/drc_item.h>
|
||||||
#include <drc/drc_engine.h>
|
#include <drc/drc_engine.h>
|
||||||
#include <zone_filler.h>
|
|
||||||
#include <board_commit.h>
|
|
||||||
#include <tool/tool_manager.h>
|
|
||||||
#include <zone_filler_tool.h>
|
|
||||||
#include <settings/settings_manager.h>
|
#include <settings/settings_manager.h>
|
||||||
|
|
||||||
|
|
||||||
struct ZONE_FILL_TEST_FIXTURE
|
struct ZONE_FILL_TEST_FIXTURE
|
||||||
{
|
{
|
||||||
ZONE_FILL_TEST_FIXTURE() :
|
ZONE_FILL_TEST_FIXTURE() :
|
||||||
m_settingsManager( true /* headless */ )
|
m_settingsManager( true /* headless */ )
|
||||||
{
|
{ }
|
||||||
}
|
|
||||||
|
|
||||||
void loadBoard( const wxString& relPath )
|
SETTINGS_MANAGER m_settingsManager;
|
||||||
{
|
std::unique_ptr<BOARD> m_board;
|
||||||
if( m_board )
|
|
||||||
{
|
|
||||||
m_board->SetProject( nullptr );
|
|
||||||
m_board = nullptr;
|
|
||||||
}
|
|
||||||
|
|
||||||
std::string absPath = KI_TEST::GetPcbnewTestDataDir() + relPath.ToStdString();
|
|
||||||
wxFileName projectFile( absPath + ".kicad_pro" );
|
|
||||||
std::string boardPath = absPath + ".kicad_pcb";
|
|
||||||
wxFileName rulesFile( absPath + ".kicad_dru" );
|
|
||||||
|
|
||||||
if( projectFile.Exists() )
|
|
||||||
m_settingsManager.LoadProject( projectFile.GetFullPath() );
|
|
||||||
|
|
||||||
m_board = KI_TEST::ReadBoardFromFileOrStream( boardPath );
|
|
||||||
|
|
||||||
if( projectFile.Exists() )
|
|
||||||
m_board->SetProject( &m_settingsManager.Prj() );
|
|
||||||
|
|
||||||
m_DRCEngine = std::make_shared<DRC_ENGINE>( m_board.get(), &m_board->GetDesignSettings() );
|
|
||||||
|
|
||||||
if( rulesFile.Exists() )
|
|
||||||
m_DRCEngine->InitEngine( rulesFile );
|
|
||||||
else
|
|
||||||
m_DRCEngine->InitEngine( wxFileName() );
|
|
||||||
|
|
||||||
m_board->GetDesignSettings().m_DRCEngine = m_DRCEngine;
|
|
||||||
|
|
||||||
m_toolMgr = std::make_unique<TOOL_MANAGER>();
|
|
||||||
m_toolMgr->SetEnvironment( m_board.get(), nullptr, nullptr, nullptr, nullptr );
|
|
||||||
}
|
|
||||||
|
|
||||||
void fillZones( int aFillVersion )
|
|
||||||
{
|
|
||||||
BOARD_COMMIT commit( m_toolMgr.get() );
|
|
||||||
ZONE_FILLER filler( m_board.get(), &commit );
|
|
||||||
std::vector<ZONE*> toFill;
|
|
||||||
|
|
||||||
m_board->GetDesignSettings().m_ZoneFillVersion = aFillVersion;
|
|
||||||
|
|
||||||
for( ZONE* zone : m_board->Zones() )
|
|
||||||
toFill.push_back( zone );
|
|
||||||
|
|
||||||
if( filler.Fill( toFill, false, nullptr ) )
|
|
||||||
commit.Push( _( "Fill Zone(s)" ), false, false );
|
|
||||||
}
|
|
||||||
|
|
||||||
SETTINGS_MANAGER m_settingsManager;
|
|
||||||
|
|
||||||
std::unique_ptr<BOARD> m_board;
|
|
||||||
std::unique_ptr<TOOL_MANAGER> m_toolMgr;
|
|
||||||
std::shared_ptr<DRC_ENGINE> m_DRCEngine;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -109,9 +50,11 @@ constexpr int delta = KiROUND( 0.006 * IU_PER_MM );
|
||||||
|
|
||||||
BOOST_FIXTURE_TEST_CASE( BasicZoneFills, ZONE_FILL_TEST_FIXTURE )
|
BOOST_FIXTURE_TEST_CASE( BasicZoneFills, ZONE_FILL_TEST_FIXTURE )
|
||||||
{
|
{
|
||||||
loadBoard( "zone_filler" );
|
KI_TEST::LoadBoard( m_settingsManager, "zone_filler", m_board );
|
||||||
|
|
||||||
fillZones( 6 );
|
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
|
||||||
|
|
||||||
|
KI_TEST::FillZones( m_board.get(), 6 );
|
||||||
|
|
||||||
// Now that the zones are filled we're going to increase the size of -some- pads and
|
// Now that the zones are filled we're going to increase the size of -some- pads and
|
||||||
// tracks so that they generate DRC errors. The test then makes sure that those errors
|
// tracks so that they generate DRC errors. The test then makes sure that those errors
|
||||||
|
|
@ -153,9 +96,9 @@ BOOST_FIXTURE_TEST_CASE( BasicZoneFills, ZONE_FILL_TEST_FIXTURE )
|
||||||
bool foundArc12Error = false;
|
bool foundArc12Error = false;
|
||||||
bool foundOtherError = false;
|
bool foundOtherError = false;
|
||||||
|
|
||||||
m_DRCEngine->InitEngine( wxFileName() ); // Just to be sure to be sure
|
bds.m_DRCEngine->InitEngine( wxFileName() ); // Just to be sure to be sure
|
||||||
|
|
||||||
m_DRCEngine->SetViolationHandler(
|
bds.m_DRCEngine->SetViolationHandler(
|
||||||
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
||||||
{
|
{
|
||||||
if( aItem->GetErrorCode() == DRCE_CLEARANCE )
|
if( aItem->GetErrorCode() == DRCE_CLEARANCE )
|
||||||
|
|
@ -182,7 +125,7 @@ BOOST_FIXTURE_TEST_CASE( BasicZoneFills, ZONE_FILL_TEST_FIXTURE )
|
||||||
}
|
}
|
||||||
} );
|
} );
|
||||||
|
|
||||||
m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
bds.m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||||
|
|
||||||
BOOST_CHECK_EQUAL( foundPad2Error, true );
|
BOOST_CHECK_EQUAL( foundPad2Error, true );
|
||||||
BOOST_CHECK_EQUAL( foundPad4Error, true );
|
BOOST_CHECK_EQUAL( foundPad4Error, true );
|
||||||
|
|
@ -195,7 +138,7 @@ BOOST_FIXTURE_TEST_CASE( BasicZoneFills, ZONE_FILL_TEST_FIXTURE )
|
||||||
|
|
||||||
BOOST_FIXTURE_TEST_CASE( NotchedZones, ZONE_FILL_TEST_FIXTURE )
|
BOOST_FIXTURE_TEST_CASE( NotchedZones, ZONE_FILL_TEST_FIXTURE )
|
||||||
{
|
{
|
||||||
loadBoard( "notched_zones" );
|
KI_TEST::LoadBoard( m_settingsManager, "notched_zones", m_board );
|
||||||
|
|
||||||
// Older algorithms had trouble where the filleted zones intersected and left notches.
|
// Older algorithms had trouble where the filleted zones intersected and left notches.
|
||||||
// See:
|
// See:
|
||||||
|
|
@ -217,7 +160,8 @@ BOOST_FIXTURE_TEST_CASE( NotchedZones, ZONE_FILL_TEST_FIXTURE )
|
||||||
BOOST_CHECK_GT( frontCopper.OutlineCount(), 2 );
|
BOOST_CHECK_GT( frontCopper.OutlineCount(), 2 );
|
||||||
|
|
||||||
// Now re-fill and make sure the holes are gone.
|
// Now re-fill and make sure the holes are gone.
|
||||||
fillZones( 6 );
|
KI_TEST::FillZones( m_board.get(), 6 );
|
||||||
|
|
||||||
frontCopper = SHAPE_POLY_SET();
|
frontCopper = SHAPE_POLY_SET();
|
||||||
|
|
||||||
for( ZONE* zone : m_board->Zones() )
|
for( ZONE* zone : m_board->Zones() )
|
||||||
|
|
@ -250,25 +194,28 @@ BOOST_FIXTURE_TEST_CASE( RegressionZoneFillTests, ZONE_FILL_TEST_FIXTURE )
|
||||||
|
|
||||||
for( const wxString& relPath : tests )
|
for( const wxString& relPath : tests )
|
||||||
{
|
{
|
||||||
loadBoard( relPath );
|
KI_TEST::LoadBoard( m_settingsManager, relPath, m_board );
|
||||||
|
|
||||||
|
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
|
||||||
|
|
||||||
for( int fillVersion : { 5, 6 } )
|
for( int fillVersion : { 5, 6 } )
|
||||||
{
|
{
|
||||||
fillZones( fillVersion );
|
KI_TEST::FillZones( m_board.get(), fillVersion );
|
||||||
|
|
||||||
std::vector<DRC_ITEM> violations;
|
std::vector<DRC_ITEM> violations;
|
||||||
|
|
||||||
m_DRCEngine->SetViolationHandler(
|
bds.m_DRCEngine->SetViolationHandler(
|
||||||
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
||||||
{
|
{
|
||||||
if( aItem->GetErrorCode() == DRCE_CLEARANCE )
|
if( aItem->GetErrorCode() == DRCE_CLEARANCE )
|
||||||
violations.push_back( *aItem );
|
violations.push_back( *aItem );
|
||||||
} );
|
} );
|
||||||
|
|
||||||
m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
bds.m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||||
|
|
||||||
if( violations.empty() )
|
if( violations.empty() )
|
||||||
{
|
{
|
||||||
|
BOOST_CHECK_EQUAL( 1, 1 ); // quiet "did not check any assertions" warning
|
||||||
BOOST_TEST_MESSAGE( wxString::Format( "Zone fill regression: %s, V%d algo passed",
|
BOOST_TEST_MESSAGE( wxString::Format( "Zone fill regression: %s, V%d algo passed",
|
||||||
relPath,
|
relPath,
|
||||||
fillVersion ) );
|
fillVersion ) );
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue