Add regression tests for track cleaner.
This commit is contained in:
Jeff Young
parent
95b87ba29a
commit
c00f4ed5d2
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@ -1515,15 +1515,14 @@ bool SHAPE_POLY_SET::Collide( const SHAPE* aShape, int aClearance, int* aActual,
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for( const std::unique_ptr<TRIANGULATED_POLYGON>& tpoly : m_triangulatedPolys )
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{
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for( const TRIANGULATED_POLYGON::TRI& tri : tpoly->Triangles() )
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{
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if( aActual || aLocation )
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{
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int triActual;
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VECTOR2I triLocation;
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if( aShape->Collide( &tri, aClearance, &triActual, &triLocation ) )
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{
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if( !aActual && !aLocation )
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return true;
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if( triActual < actual )
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{
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actual = triActual;
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@ -1531,6 +1530,12 @@ bool SHAPE_POLY_SET::Collide( const SHAPE* aShape, int aClearance, int* aActual,
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}
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}
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}
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else // A much faster version of above
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{
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if( aShape->Collide( &tri, aClearance ) )
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return true;
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}
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}
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}
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if( actual < INT_MAX )
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,216 @@
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(kicad_pcb (version 20200119) (host pcbnew "(5.99.0-1404-g52d891940-dirty)")
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(general
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)
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(page "A4")
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(layers
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(0 "F.Cu" signal)
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(2 "In2.Cu" signal)
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(49 "F.Fab" user)
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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)
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@ -0,0 +1,288 @@
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update=Friday 24 April 2020 at 14:38:42
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version=1
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last_client=kicad
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[general]
|
||||
version=1
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||||
RootSch=
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BoardNm=
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[cvpcb]
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||||
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||||
NetIExt=net
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[eeschema]
|
||||
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|
||||
LibDir=
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||||
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||||
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PageLayoutDescrFile=
|
||||
PlotDirectoryName=${plot}
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
LabSize=50
|
||||
TextOffsetRatio=0.2
|
||||
LineThickness=6
|
||||
BusThickness=12
|
||||
WireThickness=6
|
||||
JunctionSize=30
|
||||
FieldNameTemplates=(templatefields (field (name "test") visible))
|
||||
ERC_TestSimilarLabels=1
|
||||
ERC_CheckUniqueGlobalLabels=1
|
||||
ERC_CheckBusDriverConflicts=1
|
||||
ERC_CheckBusEntryConflicts=1
|
||||
ERC_CheckBusToBusConflicts=1
|
||||
ERC_CheckBusToNetConflicts=1
|
||||
[LibeditFrame]
|
||||
version=1
|
||||
PinnedItems1=device
|
||||
[ModEditFrame]
|
||||
version=1
|
||||
[SchematicFrame]
|
||||
version=1
|
||||
[sheetnames]
|
||||
1=00000000-0000-0000-0000-00005ea2d266:
|
||||
2=00000000-0000-0000-0000-00005e63adad:Untitled Sheet
|
||||
3=00000000-0000-0000-0000-000001234567:right
|
||||
4=00000000-0000-0000-0000-000034567890:left
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=../kicad/bin/
|
||||
LastSTEPExportPath=
|
||||
LastIDFExportPath=
|
||||
LastVRMLExportPath=
|
||||
LastSpecctraDSNExportPath=
|
||||
LastGenCADExportPath=
|
||||
CopperLayerCount=4
|
||||
BoardThickness=4.62
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
MinTrackWidth=0.2
|
||||
MinViaDiameter=0.4
|
||||
MinViaDrill=0.3
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
CopperEdgeClearance=0.01
|
||||
TrackWidth1=0.25
|
||||
TrackWidth2=1
|
||||
ViaDiameter1=0.8
|
||||
ViaDrill1=0.4
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.12
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=0
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=0
|
||||
EdgeCutLineWidth=0.05
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.09999999999999999
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=0
|
||||
DimensionUnits=0
|
||||
DimensionPrecision=1
|
||||
SolderMaskClearance=0.2
|
||||
SolderMaskMinWidth=0
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.2
|
||||
TrackWidth=0.25
|
||||
ViaDiameter=0.8
|
||||
ViaDrill=0.4
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
[text_variables]
|
||||
1=plot:plot_files/
|
||||
2=stuff:whatever you want
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,172 @@
|
|||
{
|
||||
"board": {
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"board_outline_line_width": 0.049999999999999996,
|
||||
"copper_line_width": 0.19999999999999998,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.049999999999999996,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.09999999999999999,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.09999999999999999,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 0.762,
|
||||
"height": 1.524,
|
||||
"width": 1.524
|
||||
},
|
||||
"silk_line_width": 0.12,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.15,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"45_degree_only": false,
|
||||
"min_clearance": 0.508
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"copper_edge_clearance": "error",
|
||||
"courtyards_overlap": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"hole_clearance": "error",
|
||||
"hole_near_hole": "error",
|
||||
"invalid_outline": "error",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "error",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zone_has_empty_net": "error",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rules": {
|
||||
"allow_blind_buried_vias": false,
|
||||
"allow_microvias": false,
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_copper_edge_clearance": 0.01,
|
||||
"min_hole_clearance": 0.0,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.19999999999999998,
|
||||
"min_microvia_drill": 0.09999999999999999,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.19999999999999998,
|
||||
"min_via_annular_width": 0.049999999999999996,
|
||||
"min_via_diameter": 0.39999999999999997,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"track_widths": [],
|
||||
"via_dimensions": [],
|
||||
"zones_allow_external_fillets": false,
|
||||
"zones_use_no_outline": true
|
||||
},
|
||||
"layer_presets": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "issue6945.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.25,
|
||||
"via_diameter": 0.8,
|
||||
"via_drill": 0.4,
|
||||
"wire_width": 6.0
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_colors": null
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": []
|
||||
},
|
||||
"sheets": [],
|
||||
"text_variables": {}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,172 @@
|
|||
{
|
||||
"board": {
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"board_outline_line_width": 0.049999999999999996,
|
||||
"copper_line_width": 0.19999999999999998,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.049999999999999996,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.09999999999999999,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.09999999999999999,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 0.762,
|
||||
"height": 1.524,
|
||||
"width": 1.524
|
||||
},
|
||||
"silk_line_width": 0.12,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.15,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"45_degree_only": false,
|
||||
"min_clearance": 0.508
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"copper_edge_clearance": "error",
|
||||
"courtyards_overlap": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"hole_clearance": "error",
|
||||
"hole_near_hole": "error",
|
||||
"invalid_outline": "error",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "error",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zone_has_empty_net": "error",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rules": {
|
||||
"allow_blind_buried_vias": false,
|
||||
"allow_microvias": false,
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_copper_edge_clearance": 0.01,
|
||||
"min_hole_clearance": 0.0,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.19999999999999998,
|
||||
"min_microvia_drill": 0.09999999999999999,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.19999999999999998,
|
||||
"min_via_annular_width": 0.049999999999999996,
|
||||
"min_via_diameter": 0.39999999999999997,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"track_widths": [],
|
||||
"via_dimensions": [],
|
||||
"zones_allow_external_fillets": false,
|
||||
"zones_use_no_outline": true
|
||||
},
|
||||
"layer_presets": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "issue8003.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.25,
|
||||
"via_diameter": 0.8,
|
||||
"via_drill": 0.4,
|
||||
"wire_width": 6.0
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_colors": null
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": []
|
||||
},
|
||||
"sheets": [],
|
||||
"text_variables": {}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,616 @@
|
|||
(kicad_pcb (version 20210623) (generator pcbnew)
|
||||
|
||||
(general
|
||||
(thickness 1.6)
|
||||
)
|
||||
|
||||
(paper "A3")
|
||||
(layers
|
||||
(0 "F.Cu" signal)
|
||||
(31 "B.Cu" signal)
|
||||
(34 "B.Paste" user)
|
||||
(35 "F.Paste" user)
|
||||
(36 "B.SilkS" user "B.Silkscreen")
|
||||
(37 "F.SilkS" user "F.Silkscreen")
|
||||
(38 "B.Mask" user)
|
||||
(39 "F.Mask" user)
|
||||
(40 "Dwgs.User" user "User.Drawings")
|
||||
(41 "Cmts.User" user "User.Comments")
|
||||
(42 "Eco1.User" user "User.Eco1")
|
||||
(44 "Edge.Cuts" user)
|
||||
(45 "Margin" user)
|
||||
(46 "B.CrtYd" user "B.Courtyard")
|
||||
(47 "F.CrtYd" user "F.Courtyard")
|
||||
(48 "B.Fab" user)
|
||||
(49 "F.Fab" user)
|
||||
)
|
||||
|
||||
(setup
|
||||
(stackup
|
||||
(layer "F.SilkS" (type "Top Silk Screen"))
|
||||
(layer "F.Paste" (type "Top Solder Paste"))
|
||||
(layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
|
||||
(layer "F.Cu" (type "copper") (thickness 0.035))
|
||||
(layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
|
||||
(layer "B.Cu" (type "copper") (thickness 0.035))
|
||||
(layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
|
||||
(layer "B.Paste" (type "Bottom Solder Paste"))
|
||||
(layer "B.SilkS" (type "Bottom Silk Screen"))
|
||||
(copper_finish "None")
|
||||
(dielectric_constraints no)
|
||||
)
|
||||
(pad_to_mask_clearance 0)
|
||||
(pcbplotparams
|
||||
(layerselection 0x00010fc_ffffffff)
|
||||
(disableapertmacros false)
|
||||
(usegerberextensions false)
|
||||
(usegerberattributes true)
|
||||
(usegerberadvancedattributes true)
|
||||
(creategerberjobfile true)
|
||||
(svguseinch false)
|
||||
(svgprecision 6)
|
||||
(excludeedgelayer true)
|
||||
(plotframeref false)
|
||||
(viasonmask false)
|
||||
(mode 1)
|
||||
(useauxorigin false)
|
||||
(hpglpennumber 1)
|
||||
(hpglpenspeed 20)
|
||||
(hpglpendiameter 15.000000)
|
||||
(dxfpolygonmode true)
|
||||
(dxfimperialunits true)
|
||||
(dxfusepcbnewfont true)
|
||||
(psnegative false)
|
||||
(psa4output false)
|
||||
(plotreference true)
|
||||
(plotvalue true)
|
||||
(plotinvisibletext false)
|
||||
(sketchpadsonfab false)
|
||||
(subtractmaskfromsilk false)
|
||||
(outputformat 1)
|
||||
(mirror false)
|
||||
(drillshape 1)
|
||||
(scaleselection 1)
|
||||
(outputdirectory "")
|
||||
)
|
||||
)
|
||||
|
||||
(net 0 "")
|
||||
(net 1 "GND")
|
||||
(net 2 "ADC12_IN14")
|
||||
(net 3 "+3V3")
|
||||
(net 4 "ADC2_IN15")
|
||||
(net 5 "ADC3_IN5")
|
||||
(net 6 "unconnected-(IC2-Pad19)")
|
||||
(net 7 "unconnected-(IC2-Pad18)")
|
||||
(net 8 "~{RESET}")
|
||||
(net 9 "Net-(C27-Pad1)")
|
||||
(net 10 "Net-(C28-Pad1)")
|
||||
(net 11 "unconnected-(IC2-Pad22)")
|
||||
(net 12 "PA15_IN_DFM")
|
||||
(net 13 "PC15_IN_PICKUP")
|
||||
(net 14 "PC13_OUT_BTS723_MV")
|
||||
(net 15 "PC14_OUT_BTS723_ALARM")
|
||||
(net 16 "ADC12_IN1")
|
||||
(net 17 "unconnected-(IC2-Pad40)")
|
||||
(net 18 "ADC12_IN2")
|
||||
(net 19 "USART2_TX")
|
||||
(net 20 "USART2_RX")
|
||||
(net 21 "SPI1_~{SS}")
|
||||
(net 22 "SPI1_SCK")
|
||||
(net 23 "SPI1_MISO")
|
||||
(net 24 "TIM1_CH1N")
|
||||
(net 25 "PB0_OUT_SM_STEP")
|
||||
(net 26 "TIM8_CH3N")
|
||||
(net 27 "ADC1_IN11")
|
||||
(net 28 "ADC1_IN5")
|
||||
(net 29 "TIM1_CH1")
|
||||
(net 30 "USART1_TX")
|
||||
(net 31 "USART1_RX")
|
||||
(net 32 "CAN1_RX")
|
||||
(net 33 "CAN1_TX")
|
||||
(net 34 "SWDIO")
|
||||
(net 35 "SWDCLK")
|
||||
(net 36 "SPI1_MOSI")
|
||||
(net 37 "CAN2_RX")
|
||||
(net 38 "CAN2_TX")
|
||||
(net 39 "PB7_OUT_SM_~{ENABLE}")
|
||||
(net 40 "PB8_OUT__LED")
|
||||
(net 41 "TIM8_CH3")
|
||||
(net 42 "Net-(IC2-Pad20)")
|
||||
|
||||
(footprint "0IBF_Crystal:Crystal_SMD_5032-2Pin_5.0x3.2mm_IBF" (layer "F.Cu")
|
||||
(tedit 60FD5043) (tstamp 0de9af20-f2c1-4152-8c27-34e4ce4bec78)
|
||||
(at 106.07 -86.88 90)
|
||||
(descr "SMD Crystal 5x3,2mm Quantek QC5CB / Interquip SMAC-5032 angepaßte Pads IBFEEW")
|
||||
(tags "SMD crystal")
|
||||
(property "Alternative" "Abracom ABM3-10.000MHZ-D2Y-T")
|
||||
(property "Bemerkung" "")
|
||||
(property "Farnell" "2508597")
|
||||
(property "MF" "Quantek")
|
||||
(property "MPN" "QC5CB10.0000F18B23M / QC5CB10.0000F18B23R")
|
||||
(property "RS" "813-6097")
|
||||
(property "Sheetfile" "controller.kicad_sch")
|
||||
(property "Sheetname" "Controller")
|
||||
(property "digikey" "")
|
||||
(property "mouser" "")
|
||||
(path "/21ecf582-2fe5-40fc-9946-89f54de57e7c/656de130-e9e8-49cd-b55f-f52948b09214")
|
||||
(attr smd)
|
||||
(fp_text reference "Q1" (at 0 -2.8 90) (layer "F.SilkS")
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
(tstamp 59ee8af3-c8d3-4c23-8657-70d98fa756b6)
|
||||
)
|
||||
(fp_text value "QC5CB10.000" (at 0 2.8 90) (layer "F.Fab")
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
(tstamp 74fa71de-1c22-4758-b2dd-2c303737d498)
|
||||
)
|
||||
(fp_text user "${REFERENCE}" (at 3.82 0 90) (layer "F.Fab")
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
(tstamp 67ae7ca2-ebc7-49a5-baf1-24115daa3026)
|
||||
)
|
||||
(fp_line (start -0.2 0) (end -0.5 0) (layer "F.SilkS") (width 0.07) (tstamp 02db9d19-a3cb-4be0-828b-49297dcf0845))
|
||||
(fp_line (start -2.8 1.7) (end 2.8 1.7) (layer "F.SilkS") (width 0.07) (tstamp 1492f2eb-82fb-460c-a712-3ecc1389d05d))
|
||||
(fp_line (start 2.8 -1.7) (end 2.8 -1.6) (layer "F.SilkS") (width 0.07) (tstamp 15c03324-3b1a-4c11-9142-f9c2b8a369aa))
|
||||
(fp_line (start -0.2 -0.7) (end -0.2 0.7) (layer "F.SilkS") (width 0.07) (tstamp 2ca4cd67-11e7-4bc4-b349-bec6803e66ed))
|
||||
(fp_line (start -2.8 1.6) (end -2.8 1.7) (layer "F.SilkS") (width 0.07) (tstamp 2dcf3f66-5257-4408-8283-570eeab368a6))
|
||||
(fp_line (start -2.8 -1.7) (end -2.8 -1.6) (layer "F.SilkS") (width 0.07) (tstamp 38b9d64d-8d84-4044-8396-27fb999961a9))
|
||||
(fp_line (start 0.1 -0.6) (end 0.1 0.6) (layer "F.SilkS") (width 0.07) (tstamp 48a896ae-a0f3-49b6-bdc7-a62b294294d4))
|
||||
(fp_line (start 0.1 0.6) (end -0.1 0.6) (layer "F.SilkS") (width 0.07) (tstamp 4d49a789-b0f1-4705-b19c-3809bec4414b))
|
||||
(fp_line (start -0.1 -0.6) (end 0.1 -0.6) (layer "F.SilkS") (width 0.07) (tstamp 7b374b50-4b0d-4c84-8586-a22780c1d664))
|
||||
(fp_line (start 2.8 -1.7) (end -2.8 -1.7) (layer "F.SilkS") (width 0.07) (tstamp a43f91a1-116a-4d40-a54b-8d5db52826c0))
|
||||
(fp_line (start 0.2 0) (end 0.6 0) (layer "F.SilkS") (width 0.07) (tstamp a4c12ca8-54d1-4a5a-b361-295a2d47471d))
|
||||
(fp_line (start 0.2 -0.7) (end 0.2 0.7) (layer "F.SilkS") (width 0.07) (tstamp a5118d1b-d818-4c65-8549-73ad4ccf7443))
|
||||
(fp_line (start 2.8 1.6) (end 2.8 1.7) (layer "F.SilkS") (width 0.07) (tstamp b65f86ac-bb27-4ddd-8769-0a03778d1811))
|
||||
(fp_line (start -0.1 0.6) (end -0.1 -0.6) (layer "F.SilkS") (width 0.07) (tstamp ef9e4629-ffd8-459b-9c3a-c80fc1d215ac))
|
||||
(fp_line (start 3.2 -1.9) (end -3.2 -1.9) (layer "F.CrtYd") (width 0.05) (tstamp 2ceab9df-6986-47e7-9061-5955ccf38699))
|
||||
(fp_line (start -3.2 1.9) (end 3.2 1.9) (layer "F.CrtYd") (width 0.05) (tstamp 80afb5ab-4177-4551-8787-1c944430afa5))
|
||||
(fp_line (start -3.2 -1.9) (end -3.2 1.9) (layer "F.CrtYd") (width 0.05) (tstamp a13bea0c-8bdc-41f7-abc8-c973b0f0538f))
|
||||
(fp_line (start 3.2 1.9) (end 3.2 -1.9) (layer "F.CrtYd") (width 0.05) (tstamp fcb074a8-a44c-486a-994f-f5865e99191d))
|
||||
(fp_line (start -2.3 -1.6) (end 2.3 -1.6) (layer "F.Fab") (width 0.1) (tstamp 02e3b2da-ecd6-4ec8-b312-3f9af36cb135))
|
||||
(fp_line (start 0.2 0) (end 0.6 0) (layer "F.Fab") (width 0.07) (tstamp 0c45a563-5e27-4fce-8af5-06ee0a6f1a1c))
|
||||
(fp_line (start 0.2 -0.7) (end 0.2 0.7) (layer "F.Fab") (width 0.07) (tstamp 1d7c950b-4361-4599-b3de-d1aee7824db3))
|
||||
(fp_line (start -2.3 1.6) (end -2.5 1.4) (layer "F.Fab") (width 0.1) (tstamp 1de822db-a0f9-41b7-a613-3545751f2426))
|
||||
(fp_line (start -0.2 -0.7) (end -0.2 0.7) (layer "F.Fab") (width 0.07) (tstamp 2bc58434-cbc6-4696-8426-3f8878fbf4ab))
|
||||
(fp_line (start 2.5 -1.4) (end 2.5 1.4) (layer "F.Fab") (width 0.1) (tstamp 3e247a21-39b4-4045-88d0-cacdceeafc93))
|
||||
(fp_line (start 2.5 1.4) (end 2.3 1.6) (layer "F.Fab") (width 0.1) (tstamp 46e283c6-ce96-417e-9b2b-58b60b2baab7))
|
||||
(fp_line (start -0.1 0.6) (end -0.1 -0.6) (layer "F.Fab") (width 0.07) (tstamp 63b19816-716c-41bf-9351-2df40ea7b6bf))
|
||||
(fp_line (start 0.1 0.6) (end -0.1 0.6) (layer "F.Fab") (width 0.07) (tstamp 704fbe02-9a47-437d-a3c1-99ca8ad88c2a))
|
||||
(fp_line (start -2.5 -1.4) (end -2.3 -1.6) (layer "F.Fab") (width 0.1) (tstamp 86c41ca5-1020-4e15-885c-0f8595be64ec))
|
||||
(fp_line (start 2.3 -1.6) (end 2.5 -1.4) (layer "F.Fab") (width 0.1) (tstamp a5b78643-ac93-4ff0-be94-2f958608b528))
|
||||
(fp_line (start -0.1 -0.6) (end 0.1 -0.6) (layer "F.Fab") (width 0.07) (tstamp adb710b1-4972-41b1-b8a9-755c11c76257))
|
||||
(fp_line (start -0.2 0) (end -0.5 0) (layer "F.Fab") (width 0.07) (tstamp b3510168-8969-45c5-a9fa-60ad00689094))
|
||||
(fp_line (start -2.5 0.6) (end -1.5 1.6) (layer "F.Fab") (width 0.1) (tstamp b9e98e16-fd1f-41e0-9cc1-f6952e941337))
|
||||
(fp_line (start -2.5 1.4) (end -2.5 -1.4) (layer "F.Fab") (width 0.1) (tstamp c472a57f-95fe-4470-9816-70cb04bae7b8))
|
||||
(fp_line (start 2.3 1.6) (end -2.3 1.6) (layer "F.Fab") (width 0.1) (tstamp d8d793c6-7000-4cb5-9808-f318ebb543da))
|
||||
(fp_line (start 0.1 -0.6) (end 0.1 0.6) (layer "F.Fab") (width 0.07) (tstamp e2fa0db0-ddb8-41a9-93e0-8aa90030f56f))
|
||||
(pad "1" smd rect locked (at -2 0 90) (size 2.2 2.8) (layers "F.Cu" "F.Paste" "F.Mask")
|
||||
(net 10 "Net-(C28-Pad1)") (pintype "passive") (tstamp da710f9d-5646-4d10-b982-08ce7f8a5a98))
|
||||
(pad "2" smd rect locked (at 2 0 90) (size 2.2 2.8) (layers "F.Cu" "F.Paste" "F.Mask")
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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File diff suppressed because it is too large
Load Diff
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|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "error",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zone_has_empty_net": "error",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rules": {
|
||||
"allow_blind_buried_vias": false,
|
||||
"allow_microvias": false,
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_copper_edge_clearance": 0.01,
|
||||
"min_hole_clearance": 0.0,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.19999999999999998,
|
||||
"min_microvia_drill": 0.09999999999999999,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.19999999999999998,
|
||||
"min_via_annular_width": 0.049999999999999996,
|
||||
"min_via_diameter": 0.39999999999999997,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"track_widths": [],
|
||||
"via_dimensions": [],
|
||||
"zones_allow_external_fillets": false,
|
||||
"zones_use_no_outline": true
|
||||
},
|
||||
"layer_presets": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "issue8909.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.25,
|
||||
"via_diameter": 0.8,
|
||||
"via_drill": 0.4,
|
||||
"wire_width": 6.0
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_colors": null
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": []
|
||||
},
|
||||
"sheets": [],
|
||||
"text_variables": {}
|
||||
}
|
||||
|
|
@ -37,6 +37,7 @@ set( QA_PCBNEW_SRCS
|
|||
test_lset.cpp
|
||||
test_pad_naming.cpp
|
||||
test_libeval_compiler.cpp
|
||||
test_tracks_cleaner.cpp
|
||||
test_zone_filler.cpp
|
||||
|
||||
drc/test_drc_courtyard_invalid.cpp
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* This program source code file is part of KiCad, a free EDA CAD application.
|
||||
*
|
||||
* Copyright (C) 2019 KiCad Developers, see AUTHORS.txt for contributors.
|
||||
* Copyright (C) 2019-2021 KiCad Developers, see AUTHORS.txt for contributors.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
|
|
@ -23,17 +23,24 @@
|
|||
|
||||
#include "board_test_utils.h"
|
||||
|
||||
#include <wx/filename.h>
|
||||
#include <board.h>
|
||||
#include <board_design_settings.h>
|
||||
#include <settings/settings_manager.h>
|
||||
#include <pcbnew_utils/board_file_utils.h>
|
||||
#include <tool/tool_manager.h>
|
||||
#include <zone_filler.h>
|
||||
|
||||
// For the temp directory logic: can be std::filesystem in C++17
|
||||
#include <boost/filesystem.hpp>
|
||||
#include <boost/test/unit_test.hpp>
|
||||
|
||||
#include <board_commit.h>
|
||||
|
||||
namespace KI_TEST
|
||||
{
|
||||
|
||||
BOARD_DUMPER::BOARD_DUMPER() : m_dump_boards( std::getenv( "KICAD_TEST_DUMP_BOARD_FILES" ) )
|
||||
BOARD_DUMPER::BOARD_DUMPER() :
|
||||
m_dump_boards( std::getenv( "KICAD_TEST_DUMP_BOARD_FILES" ) )
|
||||
{
|
||||
}
|
||||
|
||||
|
|
@ -50,4 +57,60 @@ void BOARD_DUMPER::DumpBoardToFile( BOARD& aBoard, const std::string& aName ) co
|
|||
::KI_TEST::DumpBoardToFile( aBoard, path.string() );
|
||||
}
|
||||
|
||||
|
||||
void LoadBoard( SETTINGS_MANAGER& aSettingsManager, const wxString& aRelPath,
|
||||
std::unique_ptr<BOARD>& aBoard )
|
||||
{
|
||||
if( aBoard )
|
||||
{
|
||||
aBoard->SetProject( nullptr );
|
||||
aBoard = nullptr;
|
||||
}
|
||||
|
||||
std::string absPath = GetPcbnewTestDataDir() + aRelPath.ToStdString();
|
||||
wxFileName projectFile( absPath + ".kicad_pro" );
|
||||
wxFileName legacyProject( absPath + ".pro" );
|
||||
std::string boardPath = absPath + ".kicad_pcb";
|
||||
wxFileName rulesFile( absPath + ".kicad_dru" );
|
||||
|
||||
if( projectFile.Exists() )
|
||||
aSettingsManager.LoadProject( projectFile.GetFullPath() );
|
||||
else if( legacyProject.Exists() )
|
||||
aSettingsManager.LoadProject( legacyProject.GetFullPath() );
|
||||
|
||||
aBoard = ReadBoardFromFileOrStream( boardPath );
|
||||
|
||||
if( projectFile.Exists() || legacyProject.Exists() )
|
||||
aBoard->SetProject( &aSettingsManager.Prj() );
|
||||
|
||||
auto m_DRCEngine = std::make_shared<DRC_ENGINE>( aBoard.get(), &aBoard->GetDesignSettings() );
|
||||
|
||||
if( rulesFile.Exists() )
|
||||
m_DRCEngine->InitEngine( rulesFile );
|
||||
else
|
||||
m_DRCEngine->InitEngine( wxFileName() );
|
||||
|
||||
aBoard->GetDesignSettings().m_DRCEngine = m_DRCEngine;
|
||||
}
|
||||
|
||||
|
||||
void FillZones( BOARD* m_board, int aFillVersion )
|
||||
{
|
||||
TOOL_MANAGER toolMgr;
|
||||
toolMgr.SetEnvironment( m_board, nullptr, nullptr, nullptr, nullptr );
|
||||
|
||||
BOARD_COMMIT commit( &toolMgr );
|
||||
ZONE_FILLER filler( m_board, &commit );
|
||||
std::vector<ZONE*> toFill;
|
||||
|
||||
m_board->GetDesignSettings().m_ZoneFillVersion = aFillVersion;
|
||||
|
||||
for( ZONE* zone : m_board->Zones() )
|
||||
toFill.push_back( zone );
|
||||
|
||||
if( filler.Fill( toFill, false, nullptr ) )
|
||||
commit.Push( _( "Fill Zone(s)" ), false, false );
|
||||
}
|
||||
|
||||
|
||||
} // namespace KI_TEST
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* This program source code file is part of KiCad, a free EDA CAD application.
|
||||
*
|
||||
* Copyright (C) 2019 KiCad Developers, see AUTHORS.txt for contributors.
|
||||
* Copyright (C) 2019-2021 KiCad Developers, see AUTHORS.txt for contributors.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
|
|
@ -21,18 +21,16 @@
|
|||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board_test_utils.h
|
||||
* General utilities for PCB tests
|
||||
*/
|
||||
|
||||
#ifndef QA_PCBNEW_BOARD_TEST_UTILS__H
|
||||
#define QA_PCBNEW_BOARD_TEST_UTILS__H
|
||||
|
||||
#include <string>
|
||||
#include <wx/string.h>
|
||||
|
||||
class BOARD;
|
||||
class BOARD_ITEM;
|
||||
class SETTINGS_MANAGER;
|
||||
|
||||
|
||||
namespace KI_TEST
|
||||
|
|
@ -58,6 +56,13 @@ public:
|
|||
const bool m_dump_boards;
|
||||
};
|
||||
|
||||
|
||||
void LoadBoard( SETTINGS_MANAGER& aSettingsManager, const wxString& aRelPath,
|
||||
std::unique_ptr<BOARD>& aBoard );
|
||||
|
||||
void FillZones( BOARD* m_board, int aFillVersion );
|
||||
|
||||
|
||||
} // namespace KI_TEST
|
||||
|
||||
#endif // QA_PCBNEW_BOARD_TEST_UTILS__H
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* This program source code file is part of KiCad, a free EDA CAD application.
|
||||
*
|
||||
* Copyright (C) 201 KiCad Developers, see AUTHORS.txt for contributors.
|
||||
* Copyright (C) 2021 KiCad Developers, see AUTHORS.txt for contributors.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
|
|
@ -21,12 +21,8 @@
|
|||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
|
||||
*/
|
||||
|
||||
#include <string>
|
||||
|
||||
#include <wx/toplevel.h>
|
||||
|
||||
#include <qa_utils/wx_utils/unit_test_utils.h>
|
||||
#include <pcbnew_utils/board_file_utils.h>
|
||||
#include <qa/pcbnew/board_test_utils.h>
|
||||
#include <board.h>
|
||||
#include <board_design_settings.h>
|
||||
#include <pad.h>
|
||||
|
|
@ -34,80 +30,20 @@
|
|||
#include <footprint.h>
|
||||
#include <drc/drc_item.h>
|
||||
#include <drc/drc_engine.h>
|
||||
#include <zone_filler.h>
|
||||
#include <board_commit.h>
|
||||
#include <tool/tool_manager.h>
|
||||
#include <zone_filler_tool.h>
|
||||
#include <settings/settings_manager.h>
|
||||
|
||||
|
||||
struct DRC_REGRESSION_TEST_FIXTURE
|
||||
{
|
||||
DRC_REGRESSION_TEST_FIXTURE() :
|
||||
m_settingsManager( true /* headless */ )
|
||||
{
|
||||
}
|
||||
|
||||
void loadBoard( const wxString& relPath )
|
||||
{
|
||||
if( m_board )
|
||||
{
|
||||
m_board->SetProject( nullptr );
|
||||
m_board = nullptr;
|
||||
}
|
||||
|
||||
std::string absPath = KI_TEST::GetPcbnewTestDataDir() + relPath.ToStdString();
|
||||
wxFileName projectFile( absPath + ".kicad_pro" );
|
||||
std::string boardPath = absPath + ".kicad_pcb";
|
||||
wxFileName rulesFile( absPath + ".kicad_dru" );
|
||||
|
||||
if( projectFile.Exists() )
|
||||
m_settingsManager.LoadProject( projectFile.GetFullPath() );
|
||||
|
||||
m_board = KI_TEST::ReadBoardFromFileOrStream( boardPath );
|
||||
|
||||
if( projectFile.Exists() )
|
||||
m_board->SetProject( &m_settingsManager.Prj() );
|
||||
|
||||
m_DRCEngine = std::make_shared<DRC_ENGINE>( m_board.get(), &m_board->GetDesignSettings() );
|
||||
|
||||
if( rulesFile.Exists() )
|
||||
m_DRCEngine->InitEngine( rulesFile );
|
||||
else
|
||||
m_DRCEngine->InitEngine( wxFileName() );
|
||||
|
||||
m_board->GetDesignSettings().m_DRCEngine = m_DRCEngine;
|
||||
|
||||
m_toolMgr = std::make_unique<TOOL_MANAGER>();
|
||||
m_toolMgr->SetEnvironment( m_board.get(), nullptr, nullptr, nullptr, nullptr );
|
||||
}
|
||||
|
||||
void fillZones( int aFillVersion )
|
||||
{
|
||||
BOARD_COMMIT commit( m_toolMgr.get() );
|
||||
ZONE_FILLER filler( m_board.get(), &commit );
|
||||
std::vector<ZONE*> toFill;
|
||||
|
||||
m_board->GetDesignSettings().m_ZoneFillVersion = aFillVersion;
|
||||
|
||||
for( ZONE* zone : m_board->Zones() )
|
||||
toFill.push_back( zone );
|
||||
|
||||
if( filler.Fill( toFill, false, nullptr ) )
|
||||
commit.Push( _( "Fill Zone(s)" ), false, false );
|
||||
}
|
||||
{ }
|
||||
|
||||
SETTINGS_MANAGER m_settingsManager;
|
||||
|
||||
std::unique_ptr<BOARD> m_board;
|
||||
std::unique_ptr<TOOL_MANAGER> m_toolMgr;
|
||||
std::shared_ptr<DRC_ENGINE> m_DRCEngine;
|
||||
};
|
||||
|
||||
|
||||
|
||||
constexpr int delta = KiROUND( 0.006 * IU_PER_MM );
|
||||
|
||||
|
||||
BOOST_FIXTURE_TEST_CASE( DRCFalsePositiveRegressions, DRC_REGRESSION_TEST_FIXTURE )
|
||||
{
|
||||
// These documents at one time flagged DRC errors that they shouldn't have.
|
||||
|
|
@ -123,8 +59,8 @@ BOOST_FIXTURE_TEST_CASE( DRCFalsePositiveRegressions, DRC_REGRESSION_TEST_FIXTUR
|
|||
|
||||
for( const wxString& relPath : tests )
|
||||
{
|
||||
loadBoard( relPath );
|
||||
fillZones( 6 );
|
||||
KI_TEST::LoadBoard( m_settingsManager, relPath, m_board );
|
||||
KI_TEST::FillZones( m_board.get(), 6 );
|
||||
|
||||
std::vector<DRC_ITEM> violations;
|
||||
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
|
||||
|
|
@ -132,17 +68,18 @@ BOOST_FIXTURE_TEST_CASE( DRCFalsePositiveRegressions, DRC_REGRESSION_TEST_FIXTUR
|
|||
bds.m_DRCSeverities[ DRCE_INVALID_OUTLINE ] = SEVERITY::RPT_SEVERITY_IGNORE;
|
||||
bds.m_DRCSeverities[ DRCE_UNCONNECTED_ITEMS ] = SEVERITY::RPT_SEVERITY_IGNORE;
|
||||
|
||||
m_DRCEngine->SetViolationHandler(
|
||||
bds.m_DRCEngine->SetViolationHandler(
|
||||
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
||||
{
|
||||
if( bds.GetSeverity( aItem->GetErrorCode() ) == SEVERITY::RPT_SEVERITY_ERROR )
|
||||
violations.push_back( *aItem );
|
||||
} );
|
||||
|
||||
m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||
bds.m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||
|
||||
if( violations.empty() )
|
||||
{
|
||||
BOOST_CHECK_EQUAL( 1, 1 ); // quiet "did not check any assertions" warning
|
||||
BOOST_TEST_MESSAGE( wxString::Format( "DRC regression: %s, passed", relPath ) );
|
||||
}
|
||||
else
|
||||
|
|
@ -179,22 +116,23 @@ BOOST_FIXTURE_TEST_CASE( DRCFalseNegativeRegressions, DRC_REGRESSION_TEST_FIXTUR
|
|||
|
||||
for( const std::pair<wxString, int>& entry : tests )
|
||||
{
|
||||
loadBoard( entry.first );
|
||||
fillZones( 6 );
|
||||
KI_TEST::LoadBoard( m_settingsManager, entry.first, m_board );
|
||||
KI_TEST::FillZones( m_board.get(), 6 );
|
||||
|
||||
std::vector<DRC_ITEM> violations;
|
||||
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
|
||||
|
||||
m_DRCEngine->SetViolationHandler(
|
||||
bds.m_DRCEngine->SetViolationHandler(
|
||||
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
||||
{
|
||||
violations.push_back( *aItem );
|
||||
} );
|
||||
|
||||
m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||
bds.m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||
|
||||
if( violations.size() == entry.second )
|
||||
{
|
||||
BOOST_CHECK_EQUAL( 1, 1 ); // quiet "did not check any assertions" warning
|
||||
BOOST_TEST_MESSAGE( wxString::Format( "DRC regression: %s, passed", entry.first ) );
|
||||
}
|
||||
else
|
||||
|
|
|
|||
|
|
@ -0,0 +1,204 @@
|
|||
/*
|
||||
* This program source code file is part of KiCad, a free EDA CAD application.
|
||||
*
|
||||
* Copyright (C) 2021 KiCad Developers, see AUTHORS.txt for contributors.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, you may find one here:
|
||||
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
|
||||
* or you may search the http://www.gnu.org website for the version 2 license,
|
||||
* or you may write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
|
||||
*/
|
||||
|
||||
#include <qa_utils/wx_utils/unit_test_utils.h>
|
||||
#include <qa/pcbnew/board_test_utils.h>
|
||||
#include <board.h>
|
||||
#include <board_commit.h>
|
||||
#include <board_design_settings.h>
|
||||
#include <connectivity/connectivity_data.h>
|
||||
#include <tracks_cleaner.h>
|
||||
#include <cleanup_item.h>
|
||||
#include <drc/drc_item.h>
|
||||
#include <drc/drc_engine.h>
|
||||
#include <settings/settings_manager.h>
|
||||
#include <tool/tool_manager.h>
|
||||
|
||||
struct TRACK_CLEANER_TEST_FIXTURE
|
||||
{
|
||||
TRACK_CLEANER_TEST_FIXTURE() :
|
||||
m_settingsManager( true /* headless */ )
|
||||
{ }
|
||||
|
||||
SETTINGS_MANAGER m_settingsManager;
|
||||
std::unique_ptr<BOARD> m_board;
|
||||
};
|
||||
|
||||
|
||||
struct TEST_DESCRIPTION
|
||||
{
|
||||
wxString m_File;
|
||||
bool m_Shorts;
|
||||
bool m_RedundantVias;
|
||||
bool m_RedundantTracks;
|
||||
bool m_DanglingTracks;
|
||||
bool m_TracksInPads;
|
||||
bool m_DanglingVias;
|
||||
int m_Expected;
|
||||
};
|
||||
|
||||
|
||||
BOOST_FIXTURE_TEST_CASE( FailedToCleanRegressionTests, TRACK_CLEANER_TEST_FIXTURE )
|
||||
{
|
||||
/*
|
||||
* This one ensures that certain cleanup items are indeed found and marked for cleanup.
|
||||
*/
|
||||
std::vector<TEST_DESCRIPTION> tests =
|
||||
{
|
||||
// short redundant redundant dangling tracks dangling
|
||||
// circuits vias tracks tracks in pads vias expected
|
||||
{ "issue2904", false, false, false, true, false, false, 6 },
|
||||
{ "issue5093", false, false, false, false, true, false, 118 },
|
||||
{ "issue7004", false, true, false, false, false, true, 25 },
|
||||
{ "issue8883", true, true, true, true, false, true, 80 }
|
||||
};
|
||||
|
||||
for( const TEST_DESCRIPTION& entry : tests )
|
||||
{
|
||||
KI_TEST::LoadBoard( m_settingsManager, entry.m_File, m_board );
|
||||
KI_TEST::FillZones( m_board.get(), 6 );
|
||||
m_board->GetConnectivity()->RecalculateRatsnest();
|
||||
|
||||
TOOL_MANAGER toolMgr;
|
||||
toolMgr.SetEnvironment( m_board.get(), nullptr, nullptr, nullptr, nullptr );
|
||||
|
||||
BOARD_COMMIT commit( &toolMgr );
|
||||
TRACKS_CLEANER cleaner( m_board.get(), commit );
|
||||
std::vector< std::shared_ptr<CLEANUP_ITEM> > dryRunItems;
|
||||
std::vector< std::shared_ptr<CLEANUP_ITEM> > realRunItems;
|
||||
|
||||
cleaner.CleanupBoard( true, &dryRunItems, entry.m_Shorts,
|
||||
entry.m_RedundantVias,
|
||||
entry.m_RedundantTracks,
|
||||
entry.m_DanglingTracks,
|
||||
entry.m_TracksInPads,
|
||||
entry.m_DanglingVias );
|
||||
|
||||
cleaner.CleanupBoard( true, &realRunItems, entry.m_Shorts,
|
||||
entry.m_RedundantVias,
|
||||
entry.m_RedundantTracks,
|
||||
entry.m_DanglingTracks,
|
||||
entry.m_TracksInPads,
|
||||
entry.m_DanglingVias );
|
||||
|
||||
if( dryRunItems.size() == entry.m_Expected && realRunItems.size() == entry.m_Expected )
|
||||
{
|
||||
BOOST_CHECK_EQUAL( 1, 1 ); // quiet "did not check any assertions" warning
|
||||
BOOST_TEST_MESSAGE( wxString::Format( "Track cleaner regression: %s, passed",
|
||||
entry.m_File ) );
|
||||
}
|
||||
else
|
||||
{
|
||||
BOOST_CHECK_EQUAL( dryRunItems.size(), entry.m_Expected );
|
||||
BOOST_CHECK_EQUAL( realRunItems.size(), entry.m_Expected );
|
||||
|
||||
std::map<KIID, EDA_ITEM*> itemMap;
|
||||
m_board->FillItemMap( itemMap );
|
||||
|
||||
for( const std::shared_ptr<CLEANUP_ITEM>& item : realRunItems )
|
||||
{
|
||||
BOOST_TEST_MESSAGE( item->ShowReport( EDA_UNITS::INCHES, RPT_SEVERITY_ERROR,
|
||||
itemMap ) );
|
||||
}
|
||||
|
||||
BOOST_ERROR( wxString::Format( "Track cleaner regression: %s, failed",
|
||||
entry.m_File ) );
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
BOOST_FIXTURE_TEST_CASE( TrackCleanerRegressionTests, TRACK_CLEANER_TEST_FIXTURE )
|
||||
{
|
||||
/*
|
||||
* This one just makes sure that the dry-run counts agree with the "real" counts, and that
|
||||
* the cleaning doesn't produce any connectivity changes.
|
||||
*/
|
||||
std::vector<wxString> tests = { "issue832",
|
||||
"issue4257",
|
||||
"issue8909" };
|
||||
|
||||
for( const wxString& relPath : tests )
|
||||
{
|
||||
KI_TEST::LoadBoard( m_settingsManager, relPath, m_board );
|
||||
KI_TEST::FillZones( m_board.get(), 6 );
|
||||
m_board->GetConnectivity()->RecalculateRatsnest();
|
||||
|
||||
TOOL_MANAGER toolMgr;
|
||||
toolMgr.SetEnvironment( m_board.get(), nullptr, nullptr, nullptr, nullptr );
|
||||
|
||||
BOARD_COMMIT commit( &toolMgr );
|
||||
TRACKS_CLEANER cleaner( m_board.get(), commit );
|
||||
std::vector< std::shared_ptr<CLEANUP_ITEM> > dryRunItems;
|
||||
std::vector< std::shared_ptr<CLEANUP_ITEM> > realRunItems;
|
||||
|
||||
cleaner.CleanupBoard( true, &dryRunItems, true, // short circuits
|
||||
true, // redundant vias
|
||||
true, // redundant tracks
|
||||
true, // dangling tracks
|
||||
true, // tracks in pads
|
||||
true ); // dangling vias
|
||||
|
||||
cleaner.CleanupBoard( true, &realRunItems, true, // short circuits
|
||||
true, // redundant vias
|
||||
true, // redundant tracks
|
||||
true, // dangling tracks
|
||||
true, // tracks in pads
|
||||
true ); // dangling vias
|
||||
|
||||
BOOST_CHECK_EQUAL( dryRunItems.size(), realRunItems.size() );
|
||||
|
||||
std::vector<DRC_ITEM> violations;
|
||||
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
|
||||
|
||||
bds.m_DRCEngine->SetViolationHandler(
|
||||
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
||||
{
|
||||
if( aItem->GetErrorCode() == DRCE_UNCONNECTED_ITEMS )
|
||||
violations.push_back( *aItem );
|
||||
} );
|
||||
|
||||
bds.m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||
|
||||
if( violations.empty() )
|
||||
{
|
||||
BOOST_TEST_MESSAGE( wxString::Format( "Track cleaner regression: %s, passed",
|
||||
relPath ) );
|
||||
}
|
||||
else
|
||||
{
|
||||
std::map<KIID, EDA_ITEM*> itemMap;
|
||||
m_board->FillItemMap( itemMap );
|
||||
|
||||
for( const DRC_ITEM& item : violations )
|
||||
{
|
||||
BOOST_TEST_MESSAGE( item.ShowReport( EDA_UNITS::INCHES, RPT_SEVERITY_ERROR,
|
||||
itemMap ) );
|
||||
}
|
||||
|
||||
BOOST_ERROR( wxString::Format( "Track cleaner regression: %s, failed",
|
||||
relPath ) );
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* This program source code file is part of KiCad, a free EDA CAD application.
|
||||
*
|
||||
* Copyright (C) 201 KiCad Developers, see AUTHORS.txt for contributors.
|
||||
* Copyright (C) 2021 KiCad Developers, see AUTHORS.txt for contributors.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
|
|
@ -21,86 +21,27 @@
|
|||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
|
||||
*/
|
||||
|
||||
#include <string>
|
||||
|
||||
#include <wx/toplevel.h>
|
||||
|
||||
#include <qa_utils/wx_utils/unit_test_utils.h>
|
||||
#include <pcbnew_utils/board_file_utils.h>
|
||||
#include <qa/pcbnew/board_test_utils.h>
|
||||
#include <board.h>
|
||||
#include <board_design_settings.h>
|
||||
#include <pad.h>
|
||||
#include <pcb_track.h>
|
||||
#include <footprint.h>
|
||||
#include <zone.h>
|
||||
#include <drc/drc_item.h>
|
||||
#include <drc/drc_engine.h>
|
||||
#include <zone_filler.h>
|
||||
#include <board_commit.h>
|
||||
#include <tool/tool_manager.h>
|
||||
#include <zone_filler_tool.h>
|
||||
#include <settings/settings_manager.h>
|
||||
|
||||
|
||||
struct ZONE_FILL_TEST_FIXTURE
|
||||
{
|
||||
ZONE_FILL_TEST_FIXTURE() :
|
||||
m_settingsManager( true /* headless */ )
|
||||
{
|
||||
}
|
||||
|
||||
void loadBoard( const wxString& relPath )
|
||||
{
|
||||
if( m_board )
|
||||
{
|
||||
m_board->SetProject( nullptr );
|
||||
m_board = nullptr;
|
||||
}
|
||||
|
||||
std::string absPath = KI_TEST::GetPcbnewTestDataDir() + relPath.ToStdString();
|
||||
wxFileName projectFile( absPath + ".kicad_pro" );
|
||||
std::string boardPath = absPath + ".kicad_pcb";
|
||||
wxFileName rulesFile( absPath + ".kicad_dru" );
|
||||
|
||||
if( projectFile.Exists() )
|
||||
m_settingsManager.LoadProject( projectFile.GetFullPath() );
|
||||
|
||||
m_board = KI_TEST::ReadBoardFromFileOrStream( boardPath );
|
||||
|
||||
if( projectFile.Exists() )
|
||||
m_board->SetProject( &m_settingsManager.Prj() );
|
||||
|
||||
m_DRCEngine = std::make_shared<DRC_ENGINE>( m_board.get(), &m_board->GetDesignSettings() );
|
||||
|
||||
if( rulesFile.Exists() )
|
||||
m_DRCEngine->InitEngine( rulesFile );
|
||||
else
|
||||
m_DRCEngine->InitEngine( wxFileName() );
|
||||
|
||||
m_board->GetDesignSettings().m_DRCEngine = m_DRCEngine;
|
||||
|
||||
m_toolMgr = std::make_unique<TOOL_MANAGER>();
|
||||
m_toolMgr->SetEnvironment( m_board.get(), nullptr, nullptr, nullptr, nullptr );
|
||||
}
|
||||
|
||||
void fillZones( int aFillVersion )
|
||||
{
|
||||
BOARD_COMMIT commit( m_toolMgr.get() );
|
||||
ZONE_FILLER filler( m_board.get(), &commit );
|
||||
std::vector<ZONE*> toFill;
|
||||
|
||||
m_board->GetDesignSettings().m_ZoneFillVersion = aFillVersion;
|
||||
|
||||
for( ZONE* zone : m_board->Zones() )
|
||||
toFill.push_back( zone );
|
||||
|
||||
if( filler.Fill( toFill, false, nullptr ) )
|
||||
commit.Push( _( "Fill Zone(s)" ), false, false );
|
||||
}
|
||||
{ }
|
||||
|
||||
SETTINGS_MANAGER m_settingsManager;
|
||||
|
||||
std::unique_ptr<BOARD> m_board;
|
||||
std::unique_ptr<TOOL_MANAGER> m_toolMgr;
|
||||
std::shared_ptr<DRC_ENGINE> m_DRCEngine;
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -109,9 +50,11 @@ constexpr int delta = KiROUND( 0.006 * IU_PER_MM );
|
|||
|
||||
BOOST_FIXTURE_TEST_CASE( BasicZoneFills, ZONE_FILL_TEST_FIXTURE )
|
||||
{
|
||||
loadBoard( "zone_filler" );
|
||||
KI_TEST::LoadBoard( m_settingsManager, "zone_filler", m_board );
|
||||
|
||||
fillZones( 6 );
|
||||
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
|
||||
|
||||
KI_TEST::FillZones( m_board.get(), 6 );
|
||||
|
||||
// Now that the zones are filled we're going to increase the size of -some- pads and
|
||||
// tracks so that they generate DRC errors. The test then makes sure that those errors
|
||||
|
|
@ -153,9 +96,9 @@ BOOST_FIXTURE_TEST_CASE( BasicZoneFills, ZONE_FILL_TEST_FIXTURE )
|
|||
bool foundArc12Error = false;
|
||||
bool foundOtherError = false;
|
||||
|
||||
m_DRCEngine->InitEngine( wxFileName() ); // Just to be sure to be sure
|
||||
bds.m_DRCEngine->InitEngine( wxFileName() ); // Just to be sure to be sure
|
||||
|
||||
m_DRCEngine->SetViolationHandler(
|
||||
bds.m_DRCEngine->SetViolationHandler(
|
||||
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
||||
{
|
||||
if( aItem->GetErrorCode() == DRCE_CLEARANCE )
|
||||
|
|
@ -182,7 +125,7 @@ BOOST_FIXTURE_TEST_CASE( BasicZoneFills, ZONE_FILL_TEST_FIXTURE )
|
|||
}
|
||||
} );
|
||||
|
||||
m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||
bds.m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||
|
||||
BOOST_CHECK_EQUAL( foundPad2Error, true );
|
||||
BOOST_CHECK_EQUAL( foundPad4Error, true );
|
||||
|
|
@ -195,7 +138,7 @@ BOOST_FIXTURE_TEST_CASE( BasicZoneFills, ZONE_FILL_TEST_FIXTURE )
|
|||
|
||||
BOOST_FIXTURE_TEST_CASE( NotchedZones, ZONE_FILL_TEST_FIXTURE )
|
||||
{
|
||||
loadBoard( "notched_zones" );
|
||||
KI_TEST::LoadBoard( m_settingsManager, "notched_zones", m_board );
|
||||
|
||||
// Older algorithms had trouble where the filleted zones intersected and left notches.
|
||||
// See:
|
||||
|
|
@ -217,7 +160,8 @@ BOOST_FIXTURE_TEST_CASE( NotchedZones, ZONE_FILL_TEST_FIXTURE )
|
|||
BOOST_CHECK_GT( frontCopper.OutlineCount(), 2 );
|
||||
|
||||
// Now re-fill and make sure the holes are gone.
|
||||
fillZones( 6 );
|
||||
KI_TEST::FillZones( m_board.get(), 6 );
|
||||
|
||||
frontCopper = SHAPE_POLY_SET();
|
||||
|
||||
for( ZONE* zone : m_board->Zones() )
|
||||
|
|
@ -250,25 +194,28 @@ BOOST_FIXTURE_TEST_CASE( RegressionZoneFillTests, ZONE_FILL_TEST_FIXTURE )
|
|||
|
||||
for( const wxString& relPath : tests )
|
||||
{
|
||||
loadBoard( relPath );
|
||||
KI_TEST::LoadBoard( m_settingsManager, relPath, m_board );
|
||||
|
||||
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
|
||||
|
||||
for( int fillVersion : { 5, 6 } )
|
||||
{
|
||||
fillZones( fillVersion );
|
||||
KI_TEST::FillZones( m_board.get(), fillVersion );
|
||||
|
||||
std::vector<DRC_ITEM> violations;
|
||||
|
||||
m_DRCEngine->SetViolationHandler(
|
||||
bds.m_DRCEngine->SetViolationHandler(
|
||||
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
||||
{
|
||||
if( aItem->GetErrorCode() == DRCE_CLEARANCE )
|
||||
violations.push_back( *aItem );
|
||||
} );
|
||||
|
||||
m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||
bds.m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||
|
||||
if( violations.empty() )
|
||||
{
|
||||
BOOST_CHECK_EQUAL( 1, 1 ); // quiet "did not check any assertions" warning
|
||||
BOOST_TEST_MESSAGE( wxString::Format( "Zone fill regression: %s, V%d algo passed",
|
||||
relPath,
|
||||
fillVersion ) );
|
||||
|
|
|
|||
Loading…
Reference in New Issue