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Pull back some 7.0 fixes to Custom Rules code completion.

This commit is contained in:
Jeff Young 2021-09-23 12:30:43 +01:00
parent 67d24e8b00
commit c38de1dcaf
6 changed files with 157 additions and 80 deletions
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33
common/eda_item.cpp
View File

@ -251,37 +251,38 @@ static struct EDA_ITEM_DESC
.Map( PCB_FOOTPRINT_T, _HKI( "Footprint" ) ) .Map( PCB_FOOTPRINT_T, _HKI( "Footprint" ) )
.Map( PCB_PAD_T, _HKI( "Pad" ) ) .Map( PCB_PAD_T, _HKI( "Pad" ) )
.Map( PCB_SHAPE_T, _HKI( "Graphic Shape" ) ) .Map( PCB_SHAPE_T, _HKI( "Graphic" ) )
.Map( PCB_TEXT_T, _HKI( "Board Text" ) ) .Map( PCB_TEXT_T, _HKI( "Text" ) )
.Map( PCB_FP_TEXT_T, _HKI( "Footprint Text" ) ) .Map( PCB_FP_TEXT_T, _HKI( "Text" ) )
.Map( PCB_FP_SHAPE_T, _HKI( "Graphic Shape" ) ) .Map( PCB_FP_SHAPE_T, _HKI( "Graphic" ) )
.Map( PCB_FP_ZONE_T, _HKI( "Zone" ) ) .Map( PCB_FP_ZONE_T, _HKI( "Zone" ) )
.Map( PCB_TRACE_T, _HKI( "Track" ) ) .Map( PCB_TRACE_T, _HKI( "Track" ) )
.Map( PCB_VIA_T, _HKI( "Via" ) ) .Map( PCB_VIA_T, _HKI( "Via" ) )
.Map( PCB_MARKER_T, _HKI( "Board Marker" ) ) .Map( PCB_MARKER_T, _HKI( "Marker" ) )
.Map( PCB_DIM_ALIGNED_T, _HKI( "Aligned Dimension" ) ) .Map( PCB_DIM_ALIGNED_T, _HKI( "Dimension" ) )
.Map( PCB_DIM_ORTHOGONAL_T, _HKI( "Orthogonal Dimension" ) ) .Map( PCB_DIM_ORTHOGONAL_T, _HKI( "Dimension" ) )
.Map( PCB_DIM_CENTER_T, _HKI( "Center Dimension" ) ) .Map( PCB_DIM_CENTER_T, _HKI( "Dimension" ) )
.Map( PCB_DIM_LEADER_T, _HKI( "Leader" ) ) .Map( PCB_DIM_LEADER_T, _HKI( "Leader" ) )
.Map( PCB_TARGET_T, _HKI( "Target" ) ) .Map( PCB_TARGET_T, _HKI( "Target" ) )
.Map( PCB_ZONE_T, _HKI( "Zone" ) ) .Map( PCB_ZONE_T, _HKI( "Zone" ) )
.Map( PCB_ITEM_LIST_T, _HKI( "Item List" ) ) .Map( PCB_ITEM_LIST_T, _HKI( "ItemList" ) )
.Map( PCB_NETINFO_T, _HKI( "Net Info" ) ) .Map( PCB_NETINFO_T, _HKI( "NetInfo" ) )
.Map( PCB_GROUP_T, _HKI( "Group" ) ) .Map( PCB_GROUP_T, _HKI( "Group" ) )
.Map( SCH_MARKER_T, _HKI( "Schematic Marker" ) ) .Map( SCH_MARKER_T, _HKI( "Marker" ) )
.Map( SCH_JUNCTION_T, _HKI( "Junction" ) ) .Map( SCH_JUNCTION_T, _HKI( "Junction" ) )
.Map( SCH_NO_CONNECT_T, _HKI( "No-Connect Flag" ) ) .Map( SCH_NO_CONNECT_T, _HKI( "No-Connect Flag" ) )
.Map( SCH_BUS_WIRE_ENTRY_T, _HKI( "Wire Entry" ) ) .Map( SCH_BUS_WIRE_ENTRY_T, _HKI( "Wire Entry" ) )
.Map( SCH_BUS_BUS_ENTRY_T, _HKI( "Bus Entry" ) ) .Map( SCH_BUS_BUS_ENTRY_T, _HKI( "Bus Entry" ) )
.Map( SCH_LINE_T, _HKI( "Graphic Line" ) ) .Map( SCH_LINE_T, _HKI( "Line" ) )
.Map( SCH_BITMAP_T, _HKI( "Bitmap" ) ) .Map( SCH_BITMAP_T, _HKI( "Bitmap" ) )
.Map( SCH_TEXT_T, _HKI( "Schematic Text" ) ) .Map( SCH_TEXT_T, _HKI( "Text" ) )
.Map( SCH_LABEL_T, _HKI( "Net Label" ) ) .Map( SCH_LABEL_T, _HKI( "Net Label" ) )
.Map( SCH_GLOBAL_LABEL_T, _HKI( "Global Label" ) ) .Map( SCH_GLOBAL_LABEL_T, _HKI( "Global Label" ) )
.Map( SCH_HIER_LABEL_T, _HKI( "Hierarchical Label" ) ) .Map( SCH_HIER_LABEL_T, _HKI( "Hierarchical Label" ) )
.Map( SCH_FIELD_T, _HKI( "Schematic Field" ) ) .Map( SCH_FIELD_T, _HKI( "Field" ) )
.Map( SCH_SYMBOL_T, _HKI( "Schematic Symbol" ) ) .Map( SCH_SYMBOL_T, _HKI( "Symbol" ) )
.Map( SCH_PIN_T, _HKI( "Pin" ) )
.Map( SCH_SHEET_PIN_T, _HKI( "Sheet Pin" ) ) .Map( SCH_SHEET_PIN_T, _HKI( "Sheet Pin" ) )
.Map( SCH_SHEET_T, _HKI( "Sheet" ) ) .Map( SCH_SHEET_T, _HKI( "Sheet" ) )
@ -296,7 +297,7 @@ static struct EDA_ITEM_DESC
.Map( LIB_ALIAS_T, _HKI( "Alias" ) ) .Map( LIB_ALIAS_T, _HKI( "Alias" ) )
.Map( LIB_ARC_T, _HKI( "Arc" ) ) .Map( LIB_ARC_T, _HKI( "Arc" ) )
.Map( LIB_CIRCLE_T, _HKI( "Circle" ) ) .Map( LIB_CIRCLE_T, _HKI( "Circle" ) )
.Map( LIB_TEXT_T, _HKI( "Symbol Text" ) ) .Map( LIB_TEXT_T, _HKI( "Text" ) )
.Map( LIB_RECTANGLE_T, _HKI( "Rectangle" ) ) .Map( LIB_RECTANGLE_T, _HKI( "Rectangle" ) )
.Map( LIB_POLYLINE_T, _HKI( "Polyline" ) ) .Map( LIB_POLYLINE_T, _HKI( "Polyline" ) )
.Map( LIB_BEZIER_T, _HKI( "Bezier" ) ) .Map( LIB_BEZIER_T, _HKI( "Bezier" ) )

2
common/scintilla_tricks.cpp
View File

@ -396,7 +396,7 @@ void SCINTILLA_TRICKS::DoAutocomplete( const wxString& aPartial, const wxArraySt
return first.CmpNoCase( second ); return first.CmpNoCase( second );
}); });
m_te->AutoCompShow( aPartial.size(), wxJoin( matchedTokens, ' ' ) ); m_te->AutoCompShow( aPartial.size(), wxJoin( matchedTokens, m_te->AutoCompGetSeparator() ) );
} }
} }

13
pcbnew/dialogs/dialog_exchange_footprints.cpp
View File

@ -336,25 +336,26 @@ bool DIALOG_EXCHANGE_FOOTPRINTS::processMatchingFootprints()
return false; return false;
} }
/* The change is done from the last footprint because processFootprint() modifies the last /*
* item in the list. * NB: the change is done from the last footprint because processFootprint() modifies the
* last item in the list.
*/ */
for( auto it = m_parent->GetBoard()->Footprints().rbegin(); for( auto it = m_parent->GetBoard()->Footprints().rbegin();
it != m_parent->GetBoard()->Footprints().rend(); it++ ) it != m_parent->GetBoard()->Footprints().rend(); it++ )
{ {
auto mod = *it; FOOTPRINT* footprint = *it;
if( !isMatch( mod ) ) if( !isMatch( footprint ) )
continue; continue;
if( m_updateMode ) if( m_updateMode )
{ {
if( processFootprint( mod, mod->GetFPID() ) ) if( processFootprint( footprint, footprint->GetFPID() ) )
change = true; change = true;
} }
else else
{ {
if( processFootprint( mod, newFPID ) ) if( processFootprint( footprint, newFPID ) )
change = true; change = true;
} }
} }

176
pcbnew/dialogs/panel_setup_rules.cpp
View File

@ -52,8 +52,13 @@ PANEL_SETUP_RULES::PANEL_SETUP_RULES( PAGED_DIALOG* aParent, PCB_EDIT_FRAME* aFr
wxPostEvent( m_Parent, wxCommandEvent( wxEVT_COMMAND_BUTTON_CLICKED, wxID_OK ) ); wxPostEvent( m_Parent, wxCommandEvent( wxEVT_COMMAND_BUTTON_CLICKED, wxID_OK ) );
} ); } );
m_textEditor->AutoCompSetSeparator( '|' );
m_netClassRegex.Compile( "NetClass\\s*[!=]=\\s*$", wxRE_ADVANCED ); m_netClassRegex.Compile( "NetClass\\s*[!=]=\\s*$", wxRE_ADVANCED );
m_netNameRegex.Compile( "NetName\\s*[!=]=\\s*$", wxRE_ADVANCED ); m_netNameRegex.Compile( "NetName\\s*[!=]=\\s*$", wxRE_ADVANCED );
m_typeRegex.Compile( "Type\\s*[!=]=\\s*$", wxRE_ADVANCED );
m_padTypeRegex.Compile( "Pad_Type\\s*[!=]=\\s*$", wxRE_ADVANCED );
m_fabPropRegex.Compile( "Fabrication_Property\\s*[!=]=\\s*$", wxRE_ADVANCED );
m_compileButton->SetBitmap( KiBitmap( BITMAPS::drc ) ); m_compileButton->SetBitmap( KiBitmap( BITMAPS::drc ) );
@ -114,9 +119,24 @@ void PANEL_SETUP_RULES::onScintillaCharAdded( wxStyledTextEvent &aEvent )
STRING, STRING,
SEXPR_OPEN, SEXPR_OPEN,
SEXPR_TOKEN, SEXPR_TOKEN,
SEXPR_STRING,
STRUCT_REF STRUCT_REF
}; };
auto isDisallowToken =
[]( const wxString& token ) -> bool
{
return token == "buried_via"
|| token == "graphic"
|| token == "hole"
|| token == "micro_via"
|| token == "pad"
|| token == "text"
|| token == "track"
|| token == "via"
|| token == "zone";
};
std::stack<wxString> sexprs; std::stack<wxString> sexprs;
wxString partial; wxString partial;
wxString last; wxString last;
@ -182,6 +202,15 @@ void PANEL_SETUP_RULES::onScintillaCharAdded( wxStyledTextEvent &aEvent )
} }
else if( c == ')' ) else if( c == ')' )
{ {
while( !sexprs.empty() && ( sexprs.top() == "assertion"
|| sexprs.top() == "disallow"
|| isDisallowToken( sexprs.top() )
|| sexprs.top() == "min_resolved_spokes"
|| sexprs.top() == "zone_connection" ) )
{
sexprs.pop();
}
if( !sexprs.empty() ) if( !sexprs.empty() )
sexprs.pop(); sexprs.pop();
@ -189,19 +218,40 @@ void PANEL_SETUP_RULES::onScintillaCharAdded( wxStyledTextEvent &aEvent )
} }
else if( c == ' ' ) else if( c == ' ' )
{ {
if( context == SEXPR_OPEN && !partial.IsEmpty() ) if( context == SEXPR_OPEN && ( partial == "constraint"
|| partial == "disallow"
|| partial == "layer"
|| partial == "severity" ) )
{ {
m_textEditor->AutoCompCancel(); m_textEditor->AutoCompCancel();
sexprs.push( partial ); sexprs.push( partial );
if( sexprs.size() && ( sexprs.top() == "constraint"
|| sexprs.top() == "disallow"
|| sexprs.top() == "layer" ) )
{
partial = wxEmptyString; partial = wxEmptyString;
context = SEXPR_TOKEN; context = SEXPR_TOKEN;
continue; continue;
} }
else if( partial == "disallow"
|| isDisallowToken( partial )
|| partial == "min_resolved_spokes"
|| partial == "zone_connection" )
{
m_textEditor->AutoCompCancel();
sexprs.push( partial );
partial = wxEmptyString;
context = SEXPR_TOKEN;
continue;
}
else if( partial == "rule"
|| partial == "assertion"
|| partial == "condition" )
{
m_textEditor->AutoCompCancel();
sexprs.push( partial );
partial = wxEmptyString;
context = SEXPR_STRING;
continue;
} }
context = NONE; context = NONE;
@ -218,20 +268,18 @@ void PANEL_SETUP_RULES::onScintillaCharAdded( wxStyledTextEvent &aEvent )
{ {
if( sexprs.empty() ) if( sexprs.empty() )
{ {
tokens = "rule " tokens = "rule|"
"version"; "version";
} }
else if( sexprs.top() == "rule" ) else if( sexprs.top() == "rule" )
{ {
tokens = "condition " tokens = "condition|"
"constraint " "constraint|"
"layer"; "layer";
} }
else if( sexprs.top() == "constraint" ) else if( sexprs.top() == "constraint" )
{ {
tokens = "max " tokens = "max|min|opt";
"min "
"opt";
} }
} }
else if( context == SEXPR_TOKEN ) else if( context == SEXPR_TOKEN )
@ -242,49 +290,42 @@ void PANEL_SETUP_RULES::onScintillaCharAdded( wxStyledTextEvent &aEvent )
} }
else if( sexprs.top() == "constraint" ) else if( sexprs.top() == "constraint" )
{ {
tokens = "annular_width " tokens = "annular_width|"
"clearance " "clearance|"
"courtyard_clearance " "courtyard_clearance|"
"diff_pair_gap " "diff_pair_gap|"
"diff_pair_uncoupled " "diff_pair_uncoupled|"
"disallow " "disallow|"
"edge_clearance " "edge_clearance|"
"length " "length|"
"hole_clearance " "hole_clearance|"
"hole_size " "hole_size|"
"hole_to_hole " "hole_to_hole|"
"silk_clearance " "silk_clearance|"
"skew " "skew|"
"track_width " "track_width|"
"via_count " "via_count|"
"via_diameter"; "via_diameter";
} }
else if( sexprs.top() == "disallow" else if( sexprs.top() == "disallow" || isDisallowToken( sexprs.top() ) )
|| sexprs.top() == "buried_via"
|| sexprs.top() == "graphic"
|| sexprs.top() == "hole"
|| sexprs.top() == "micro_via"
|| sexprs.top() == "pad"
|| sexprs.top() == "text"
|| sexprs.top() == "track"
|| sexprs.top() == "via"
|| sexprs.top() == "zone" )
{ {
tokens = "buried_via " tokens = "buried_via|"
"graphic " "graphic|"
"hole " "hole|"
"micro_via " "micro_via|"
"pad " "pad|"
"text " "text|"
"track " "track|"
"via " "via|"
"zone"; "zone";
} }
else if( sexprs.top() == "layer" ) else if( sexprs.top() == "layer" )
{ {
tokens = "inner " tokens = "inner|outer|\"x\"";
"outer " }
"\"x\""; else if( sexprs.top() == "severity" )
{
tokens = "warning|error|ignore|exclusion";
} }
} }
else if( context == STRING && !sexprs.empty() && sexprs.top() == "condition" ) else if( context == STRING && !sexprs.empty() && sexprs.top() == "condition" )
@ -307,12 +348,12 @@ void PANEL_SETUP_RULES::onScintillaCharAdded( wxStyledTextEvent &aEvent )
} }
for( const wxString& propName : propNames ) for( const wxString& propName : propNames )
tokens += " " + propName; tokens += "|" + propName;
PCB_EXPR_BUILTIN_FUNCTIONS& functions = PCB_EXPR_BUILTIN_FUNCTIONS::Instance(); PCB_EXPR_BUILTIN_FUNCTIONS& functions = PCB_EXPR_BUILTIN_FUNCTIONS::Instance();
for( const wxString& funcSig : functions.GetSignatures() ) for( const wxString& funcSig : functions.GetSignatures() )
tokens += " " + funcSig; tokens += "|" + funcSig;
} }
else if( expr_context == STRING ) else if( expr_context == STRING )
{ {
@ -322,20 +363,51 @@ void PANEL_SETUP_RULES::onScintillaCharAdded( wxStyledTextEvent &aEvent )
BOARD_DESIGN_SETTINGS& bds = board->GetDesignSettings(); BOARD_DESIGN_SETTINGS& bds = board->GetDesignSettings();
for( const std::pair<const wxString, NETCLASSPTR>& entry : bds.GetNetClasses() ) for( const std::pair<const wxString, NETCLASSPTR>& entry : bds.GetNetClasses() )
tokens += " " + entry.first; tokens += "|" + entry.first;
} }
else if( m_netNameRegex.Matches( last ) ) else if( m_netNameRegex.Matches( last ) )
{ {
BOARD* board = m_frame->GetBoard(); BOARD* board = m_frame->GetBoard();
for( const wxString& netnameCandidate : board->GetNetClassAssignmentCandidates() ) for( const wxString& netnameCandidate : board->GetNetClassAssignmentCandidates() )
tokens += " " + netnameCandidate; tokens += "|" + netnameCandidate;
}
else if( m_typeRegex.Matches( last ) )
{
tokens = "Dimension|"
"Footprint|"
"Graphic|"
"Group|"
"Leader|"
"Pad|"
"Target|"
"Text|"
"Track|"
"Via|"
"Zone";
}
else if( m_padTypeRegex.Matches( last ) )
{
tokens = "Through-hole|"
"SMD|"
"Edge connector|"
"NPTH, mechanical";
}
else if( m_fabPropRegex.Matches( last ) )
{
tokens = "None|"
"BGA pad|"
"Fiducial, global to board|"
"Fiducial, local to footprint|"
"Test point pad|"
"Heatsink pad|"
"Castellated pad";
} }
} }
} }
if( !tokens.IsEmpty() ) if( !tokens.IsEmpty() )
m_scintillaTricks-> DoAutocomplete( partial, wxSplit( tokens, ' ' ) ); m_scintillaTricks->DoAutocomplete( partial, wxSplit( tokens, '|' ) );
} }

3
pcbnew/dialogs/panel_setup_rules.h
View File

@ -59,6 +59,9 @@ private:
wxRegEx m_netClassRegex; wxRegEx m_netClassRegex;
wxRegEx m_netNameRegex; wxRegEx m_netNameRegex;
wxRegEx m_typeRegex;
wxRegEx m_padTypeRegex;
wxRegEx m_fabPropRegex;
HTML_MESSAGE_BOX* m_helpWindow; HTML_MESSAGE_BOX* m_helpWindow;
}; };

2
pcbnew/drc/drc_rule_condition.cpp
View File

@ -61,7 +61,7 @@ bool DRC_RULE_CONDITION::EvaluateFor( const BOARD_ITEM* aItemA, const BOARD_ITEM
ctx.SetErrorCallback( ctx.SetErrorCallback(
[&]( const wxString& aMessage, int aOffset ) [&]( const wxString& aMessage, int aOffset )
{ {
aReporter->Report( _( "ERROR:" ) + wxS( " " )+ aMessage ); aReporter->Report( _( "ERROR:" ) + wxS( " " ) + aMessage );
} ); } );
} }