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Add Fliege filter Spice netlist exporter test 

Which we use to test multi-part symbols, as Fliege filter has two op
amps.
This commit is contained in:
Mikolaj Wielgus 2022-08-25 08:39:46 +02:00
parent a0400791c0
commit c6defadb78
6 changed files with 1514 additions and 0 deletions
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2
qa/data/eeschema/spice_netlists/fliege_filter/fliege_filter.kicad_pcb Normal file
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@ -0,0 +1,2 @@
(kicad_pcb (version 20220818) (generator pcbnew)
)

334
qa/data/eeschema/spice_netlists/fliege_filter/fliege_filter.kicad_pro Normal file
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@ -0,0 +1,334 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.1,
"copper_line_width": 0.2,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"other_line_width": 0.15,
"silk_line_width": 0.15,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"rules": {
"min_copper_edge_clearance": 0.0,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0
},
"track_widths": [],
"via_dimensions": []
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
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[
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[
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[
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],
[
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[
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[
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]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "fliege_filter.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"1bb7f68e-09b1-4448-8403-97b70f8d3680",
""
]
],
"text_variables": {}
}

1005
qa/data/eeschema/spice_netlists/fliege_filter/fliege_filter.kicad_sch Normal file
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5
qa/data/eeschema/spice_netlists/fliege_filter/fliege_filter.kicad_sch-bak Normal file
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@ -0,0 +1,5 @@
(kicad_sch (version 20220820) (generator eeschema)
(paper "A4")
(lib_symbols)
(symbol_instances)
)

156
qa/data/eeschema/spice_netlists/fliege_filter/uopamp.lib.spice Normal file
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@ -0,0 +1,156 @@
* Universal Opamp SPICE Macromodels
* Version: v1.1
* Date: 2019-11-23
*
* Written in 2019 by Ste Kulov, HD Retrovision LLC.
* Later modified by KiCad developers
* To the extent possible under law, the author(s) have dedicated all copyright
* and related and neighboring rights to this software to the public domain worldwide.
* This software is distributed without any warranty.
* You should have received a copy of the CC0 Public Domain Dedication along with this software.
* If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
*
*****************************************
*************
* CHANGELOG *
*************
* ---------------------------------------
* v1.0
* 2019-11-08
* ---------------------------------------
* 1.) Initial Release
* ---------------------------------------
*
*
* ---------------------------------------
* v1.1
* 2019-11-23
* ---------------------------------------
* 1.) lvl2: Removed SW model and replaced all instances with semiconductor diodes.
* 2.) lvl2: Added offsets to the voltage sources to compensate for the new semiconductor junctions.
* ---------------------------------------
* v1.2
* 2022-08-23
* ---------------------------------------
* 1.) Added dual and quad channel models for both lvl1 and lvl2
*****************************************
*****************************************
.subckt uopamp_lvl1 +IN -IN OUT
* Universal Opamp Level 1
* Single pole opamp without voltage rails and referenced to GND
*
* PINOUT ORDER 1 2 3
* PINOUT ORDER +IN -IN OUT
*
* Parameters:
* Avol => open-loop voltage gain (V/V), default=100k
* GBW => gain-bandwidth product (Hz), default=100meg
* Rin => differential input resistance (ohm), default=100g
* Rout => open-loop output resistance (ohm), default=1
*
R1 +IN -IN {Rin}
G1 0 OUT +IN -IN {Avol/Rout}
R2 OUT 0 100g
C3 OUT 0 {Avol/(2*pi*GBW*Rout)}
.param Avol=100k
.param GBW=100meg
.param Rin=100g
.param Rout=1
.param pi=3.1415926535898
.ends
*****************************************
.subckt uopamp_lvl1_2x +IN1 -IN1 OUT1 +IN2 -IN2 OUT2
X1 +IN1 -IN1 OUT1 uopamp_lvl1
X2 +IN2 -IN2 OUT2 uopamp_lvl2
.ends
*****************************************
*****************************************
.subckt uopamp_lvl1_4x +IN1 -IN1 OUT1 +IN2 -IN2 OUT2 +IN3 -IN3 OUT3 +IN4 -IN4 OUT4
X1 +IN1 -IN1 OUT1 uopamp_lvl1
X2 +IN2 -IN2 OUT2 uopamp_lvl1
X3 +IN3 -IN3 OUT3 uopamp_lvl1
X4 +IN4 -IN4 OUT4 uopamp_lvl1
.ends
*****************************************
*****************************************
.subckt uopamp_lvl2 +IN -IN VCC VEE OUT
* Universal Opamp Level 2
* Single pole opamp with rail saturation, current consumption, current limiting, and input offset voltage
*
* PINOUT ORDER 1 2 3 4 5
* PINOUT ORDER +IN -IN VCC VEE OUT
*
* Parameters:
* Avol => open-loop voltage gain (V/V), default=100k
* GBW => gain-bandwidth product (Hz), default=100meg
* Rin => differential input resistance (ohm), default=100g
* Rout => open-loop output resistance (ohm), default=1
* Iq => quiescent supply current (A), default=1m
* Ilimit => maximum output current (A), default=1
* Vrail => voltage between output saturation and each rail (V), default=0
* Vos => input offset voltage (V), default=0
* Vmax => total maximum supply voltage between rails (V), default=50
*
G1 VCC N001 N002 -IN 1u
G2 VEE N001 N002 -IN 1u
R1 VCC N001 {Avol/1u}
R2 N001 VEE {Avol/1u}
G3 OUT VCC VCC N001 {1/(2*Rout)}
G4 VEE OUT N001 VEE {1/(2*Rout)}
R4 VCC OUT {2*Rout}
R5 OUT VEE {2*Rout}
C1 VCC N001 {1u/(2*pi*GBW)}
C2 N001 VEE {1u/(2*pi*GBW)}
G6 N005 VEE N001 OUT {1/(2*Rout)}
G5 N006 VEE OUT N001 {1/(2*Rout)}
R8 -IN +IN {Rin}
V6 VCC N003 {Vrail+545m}
V7 N008 VEE {Vrail+545m}
V8 N002 +IN {Vos}
V9 OUT N007 {Ilimit-545m}
V10 N004 OUT {Ilimit-545m}
D1 N001 N003 diode
D2 N008 N001 diode
D3 VCC N005 diode
D4 VCC N006 diode
D5 VEE N005 zener
D6 VEE N006 zener
D7 N001 N004 diode
D8 N007 N001 diode
I1 VCC VEE {Iq}
.param Avol = 100k
.param GBW = 100meg
.param Rin = 100g
.param Rout = 1
.param Iq = 1m
.param Ilimit = 1
.param Vrail = 0
.param Vos = 0
.param Vmax = 50
.model diode D(Is=1e-14)
.model zener D(Is=1e-14 BV={Vmax})
.param pi=3.1415926535898
.ends
*****************************************
*****************************************
.subckt uopamp_lvl2_2x VCC VEE +IN1 -IN1 OUT1 +IN2 -IN2 OUT2
X1 +IN1 -IN1 VCC VEE OUT1 uopamp_lvl2
X2 +IN2 -IN2 VCC VEE OUT2 uopamp_lvl2
.ends
*****************************************
*****************************************
.subckt uopamp_lvl2_4x VCC VEE +IN1 -IN1 OUT1 +IN2 -IN2 OUT2 +IN3 -IN3 OUT3 +IN4 -IN4 OUT4
X1 +IN1 -IN1 VCC VEE OUT1 uopamp_lvl2
X2 +IN2 -IN2 VCC VEE OUT2 uopamp_lvl2
X3 +IN3 -IN3 VCC VEE OUT3 uopamp_lvl2
X4 +IN4 -IN4 VCC VEE OUT4 uopamp_lvl2
.ends
*****************************************

12
qa/unittests/eeschema/test_netlist_exporter_spice.cpp
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@ -366,6 +366,18 @@ BOOST_AUTO_TEST_CASE( CmosNot )
}*/
BOOST_AUTO_TEST_CASE( FliegeFilter )
{
// We test a multi-unit part here, as Fliege topology uses two op amps (power supply pins are a
// third part).
TestNetlist( "fliege_filter" );
TestACPoint( 0.8e3, { { "V(/in)", 1 }, { "V(/out)", 1 } } );
TestACPoint( 1.061e3, { { "V(/in)", 1 }, { "V(/out)", 0 } } );
TestACPoint( 1.2e3, { { "V(/in)", 1 }, { "V(/out)", 1 } } );
}
BOOST_AUTO_TEST_CASE( LegacyLaserDriver )
{
TestNetlist( "legacy_laser_driver" );