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Regression test case for 11814.

This commit is contained in:
Jeff Young 2022-06-15 10:55:25 +01:00
parent 5e80e2a421
commit ce4cedb5b4
4 changed files with 45618 additions and 25 deletions
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34
qa/data/pcbnew/issue11814.kicad_dru Normal file
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@ -0,0 +1,34 @@
(version 1)
(rule "ViaToVia_SameNet"
(condition "A.Type == 'via' && A.Net == B.Net")
(constraint hole_to_hole (min 0.254mm))
(constraint hole_clearance (min 0.254mm)))
(rule "ViaToTrack"
(condition "A.Type == 'via' && B.Type == 'track'")
(constraint hole_clearance (min 0.254mm)))
(rule "NpthToTrack"
(condition "A.Type == 'hole' && !A.isPlated() && B.Type == 'track'")
(constraint hole_clearance (min 0.254mm)))
(rule "PadToTrack"
(condition "A.Type == 'pad' && B.Type == 'track'")
(constraint clearance (min 0.2mm)))
(rule "PadToEdge"
(condition "A.Type == 'pad' && !A.insideArea('PadsNearEdge*')")
(constraint edge_clearance (min 0.6mm)))
(rule "SilkZoneOverPads"
(condition "A.Type == 'zone' && A.existsOnLayer('*.Silkscreen') && B.existsOnLayer('*.Mask')")
(constraint silk_clearance (min -0.1mm)))
(rule "HvUnderConformal"
(condition "A.NetClass == 'HV' && A.insideArea('Conformal*')")
(constraint clearance (min 0.4mm)))
(rule "TightWSON"
(condition "A.insideCourtyard('U4') || A.insideCourtyard('CW*')")
(constraint clearance (min 0.15mm)))

45000
qa/data/pcbnew/issue11814.kicad_pcb Normal file
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556
qa/data/pcbnew/issue11814.kicad_pro Normal file
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@ -0,0 +1,556 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.09999999999999999,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 0.6,
"fab_text_size_v": 0.6,
"fab_text_thickness": 0.09999999999999999,
"fab_text_upright": true,
"other_line_width": 0.15,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.0,
"height": 2.0574,
"width": 0.5334
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 0.7999999999999999,
"silk_text_size_v": 0.7999999999999999,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.0
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [
"clearance|117659651|138317783|eebbfedb-a3da-45a5-bc48-d905e46a7d82|7eb04688-2f96-46df-aa71-0c7b9302c7d5",
"copper_edge_clearance|40250000|126500000|034f0935-ed69-4eca-8d3a-8151fcfdb2d1|0303c0ea-5967-4c9e-b219-159dd698e422",
"copper_edge_clearance|40250000|132150000|034f0935-ed69-4eca-8d3a-8151fcfdb2d1|02cf519b-dd9d-4256-8bbd-6c85f498badd",
"copper_edge_clearance|59500000|143000000|07f59568-4fd3-4e28-8881-099676cd1e39|cd14467d-48f8-463e-91f1-d96d0a18fd7d",
"copper_edge_clearance|62250000|143000000|07f59568-4fd3-4e28-8881-099676cd1e39|6f5fad4c-b51f-41f7-b1da-d3b683de0b9b",
"copper_edge_clearance|65000000|143000000|07f59568-4fd3-4e28-8881-099676cd1e39|68b533a0-f285-479e-afc1-3bd5daf8f3ae"
],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "ignore",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "ignore",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"overlapping_pads": "warning",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "ignore",
"silk_overlap": "ignore",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "ignore",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.25,
"min_hole_clearance": 0.254,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.15,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.12,
"min_through_hole_diameter": 0.19999999999999998,
"min_track_width": 0.1016,
"min_via_annular_width": 0.125,
"min_via_diameter": 0.44999999999999996,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0,
0.146812,
0.2032,
0.254,
0.3556,
0.4572,
0.508,
0.635
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
}
],
"zones_allow_external_fillets": true,
"zones_use_no_outline": true
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "issue11814.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.15,
"diff_pair_gap": 0.1524,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.11049,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1524,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 1.0,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "HV",
"nets": [
"/ATN_IN",
"/SIG_100XC2",
"/SIG_1X",
"/SIG_1XC",
"/SIG_1XC2",
"/SIG_50_{OPEN}",
"/SIG_IN_{1}",
"/SIG_IN_{2}",
"/SIG_IN_{3}",
"/SIG_{1}",
"/SIG_{2}"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1524,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 0.4,
"diff_pair_gap": 0.1524,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.11049,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "VaricapBias",
"nets": [
"/VFILT'",
"/VFILTER"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1524,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
}
],
"meta": {
"version": 2
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": "${ALEXISVL}/basic.kicad_wks"
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"default_bus_thickness": 12.0,
"default_junction_size": 40.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"default_wire_thickness": 6.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "${ALEXISVL}/basic.kicad_wks",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"6cbca710-7cbe-4156-8860-98558c1f844f",
""
]
],
"text_variables": {}
}

19
qa/unittests/pcbnew/drc/test_drc_regressions.cpp
View File

@ -48,17 +48,18 @@ BOOST_FIXTURE_TEST_CASE( DRCFalsePositiveRegressions, DRC_REGRESSION_TEST_FIXTUR
{
// These documents at one time flagged DRC errors that they shouldn't have.
std::vector<wxString> tests = { "issue4139", // DRC fails wrongly with minimally-spaced pads at 45 degree
"issue4774", // Shape collisions missing SH_POLY_SET - Breaks DRC
std::vector<wxString> tests =
{
"issue4139", // DRC fails wrongly with minimally-spaced pads at 45 degree
"issue4774", // Shape collisions missing SH_POLY_SET
"issue5978", // Hole clearance violation with non-copper pad
"issue5990", // DRC flags a board edge clearance violation
// although the clearance is respected
"issue6443", // Wrong DRC and rendering of THT pads with
// selective inner copper layers
"issue5990", // DRC flags a board edge clearance violation although the clearance is respected
"issue6443", // Wrong DRC and rendering of THT pads with selective inner copper layers
"issue7567", // DRC constraint to disallow holes gets SMD pads also
"issue7975", // Differential pair gap out of range fault by DRC
"issue8407", // PCBNEW: Arc for diff pair has clearance DRC error
"issue10906" // Soldermask bridge for only one object
"issue10906", // Soldermask bridge for only one object
"issue11814" // Bad cache hit in isInsideArea
};
for( const wxString& relPath : tests )
@ -114,7 +115,9 @@ BOOST_FIXTURE_TEST_CASE( DRCFalseNegativeRegressions, DRC_REGRESSION_TEST_FIXTUR
{
// These documents at one time failed to catch DRC errors that they should have.
std::vector< std::pair<wxString, int> > tests = { { "issue1358", 2 },
std::vector< std::pair<wxString, int> > tests =
{
{ "issue1358", 2 },
{ "issue2512", 5 },
{ "issue2528", 1 },
{ "issue5750", 4 }, //Shorting zone fills pass DRC in some cases