Port simulator probing to new connectivity info

This commit is contained in:
Jon Evans 2020-08-30 16:05:16 -04:00
parent 9f7bca38b3
commit cf17a675b4
1 changed files with 5 additions and 12 deletions

View File

@ -637,19 +637,12 @@ int SCH_EDITOR_CONTROL::SimProbe( const TOOL_EVENT& aEvent )
if( !item ) if( !item )
return false; return false;
SCH_SHEET_PATH& sheet = m_frame->GetCurrentSheet();
if( item->IsType( wires ) ) if( item->IsType( wires ) )
{ {
// TODO(JE) Port to connection graph if( SCH_CONNECTION* conn = static_cast<SCH_ITEM*>( item )->Connection( sheet ) )
std::unique_ptr<NETLIST_OBJECT_LIST> netlist( m_frame->BuildNetListBase() ); simFrame->AddVoltagePlot( UnescapeString( conn->Name() ) );
for( NETLIST_OBJECT* obj : *netlist )
{
if( obj->m_Comp == item )
{
simFrame->AddVoltagePlot( UnescapeString( obj->GetNetName() ) );
break;
}
}
} }
else if( item->Type() == SCH_PIN_T ) else if( item->Type() == SCH_PIN_T )
{ {
@ -668,7 +661,7 @@ int SCH_EDITOR_CONTROL::SimProbe( const TOOL_EVENT& aEvent )
else else
param = wxString::Format( wxT( "I%s" ), pin->GetName().Lower() ); param = wxString::Format( wxT( "I%s" ), pin->GetName().Lower() );
simFrame->AddCurrentPlot( comp->GetRef( &m_frame->GetCurrentSheet() ), param ); simFrame->AddCurrentPlot( comp->GetRef( &sheet ), param );
} }
return true; return true;