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ADDED holeWallPlatingThickness to AdvancedCfg. 

Used for zone filling and DRC hole collision testing.  Allows us to
calculate the actual hole size from the finish hole size.

Fixes https://gitlab.com/kicad/code/kicad/issues/5468
This commit is contained in:
Jeff Young 2020-09-03 15:58:49 +01:00
parent e535489a0a
commit d1006138fd
7 changed files with 46 additions and 9 deletions
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20
common/advanced_config.cpp
View File

@ -74,6 +74,13 @@ static const wxChar ExtraFillMargin[] = wxT( "ExtraFillMargin" );
*/
static const wxChar DRCEpsilon[] = wxT( "DRCEpsilon" );
/**
* Used to calculate the actual hole size from the finish hole size.
* IPC-6012 says 15-18um; Cadence says at least 0.020 for a Class 2 board and at least 0.025
* for Class 3.
*/
static const wxChar HoleWallThickness[] = wxT( "HoleWallPlatingThickness" );
/**
* Testing mode for new connectivity algorithm. Setting this to on will cause all modifications
* to the netlist to be recalculated on the fly. This may be slower than the standard process
@ -213,6 +220,10 @@ ADVANCED_CFG::ADVANCED_CFG()
m_extraClearance = 0.0005;
m_DRCEpsilon = 0.0005; // 500nm is small enough not to materially violate
// any constraints.
m_holeWallThickness = 0.020; // IPC-6012 says 15-18um; Cadence says at least
// 0.020 for a Class 2 board and at least 0.025
// for Class 3.
loadFromConfigFile();
}
@ -259,6 +270,9 @@ void ADVANCED_CFG::loadSettings( wxConfigBase& aCfg )
configParams.push_back( new PARAM_CFG_DOUBLE( true, AC_KEYS::DRCEpsilon,
&m_DRCEpsilon, 0.0005, 0.0, 1.0 ) );
configParams.push_back( new PARAM_CFG_DOUBLE( true, AC_KEYS::HoleWallThickness,
&m_holeWallThickness, 0.020, 0.0, 1.0 ) );
configParams.push_back( new PARAM_CFG_INT( true, AC_KEYS::CoroutineStackSize,
&m_coroutineStackSize, AC_STACK::default_stack,
AC_STACK::min_stack, AC_STACK::max_stack ) );
@ -278,12 +292,12 @@ void ADVANCED_CFG::loadSettings( wxConfigBase& aCfg )
configParams.push_back( new PARAM_CFG_BOOL( true, AC_KEYS::StrokeTriangulation,
&m_DrawTriangulationOutlines, false ) );
configParams.push_back(
new PARAM_CFG_BOOL( true, AC_KEYS::PluginAltiumSch, &m_PluginAltiumSch, false ) );
configParams.push_back( new PARAM_CFG_BOOL( true, AC_KEYS::PluginAltiumSch,
&m_PluginAltiumSch, false ) );
wxConfigLoadSetups( &aCfg, configParams );
for( auto param : configParams )
for( PARAM_CFG* param : configParams )
delete param;
dumpCfg( configParams );

5
include/advanced_config.h
View File

@ -94,6 +94,11 @@ public:
*/
double m_DRCEpsilon;
/**
* Hole wall plating thickness. Used to determine actual hole size from finish hole size.
*/
double m_holeWallThickness;
/**
* Do real-time connectivity
*/

9
include/board_design_settings.h
View File

@ -89,9 +89,6 @@
#define MINIMUM_ERROR_SIZE_MM 0.001
#define MAXIMUM_ERROR_SIZE_MM 0.1
#define DRC_EPSILON 500; // An epsilon to account for rounding errors, etc.
// 500nm is small enough not to materially violate
// any constraints.
/**
* Struct VIA_DIMENSION
@ -802,6 +799,12 @@ public:
*/
int GetDRCEpsilon() const;
/**
* Pad & via drills are finish size. Adding the hole plating thickness gives you the
* acutal hole size.
*/
int GetHolePlatingThickness() const;
/**
* Function GetLineThickness
* Returns the default graphic segment thickness from the layer class for the given layer.

6
pcbnew/board_design_settings.cpp
View File

@ -966,6 +966,12 @@ int BOARD_DESIGN_SETTINGS::GetDRCEpsilon() const
}
int BOARD_DESIGN_SETTINGS::GetHolePlatingThickness() const
{
return Millimeter2iu( ADVANCED_CFG::GetCfg().m_holeWallThickness );
}
int BOARD_DESIGN_SETTINGS::GetLineThickness( PCB_LAYER_ID aLayer ) const
{
return m_LineThickness[ GetLayerClass( aLayer ) ];

1
pcbnew/class_board.h
View File

@ -530,7 +530,6 @@ public:
*/
BOARD_DESIGN_SETTINGS& GetDesignSettings() const
{
return *m_designSettings;
}

3
pcbnew/drc/drc_clearance_test_functions.cpp
View File

@ -319,6 +319,9 @@ void DRC::doTrackDrc( BOARD_COMMIT& aCommit, TRACK* aRefSeg, TRACKS::iterator aS
&m_clearanceSource );
}
if( pad->GetAttribute() == PAD_ATTRIB_STANDARD )
minClearance += bds.GetHolePlatingThickness();
if( slot->Collide( &refSeg, minClearance + bds.GetDRCEpsilon(), &actual ) )
{
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_CLEARANCE );

9
pcbnew/zone_filler.cpp
View File

@ -445,8 +445,15 @@ static void setupDummyPadForHole( const D_PAD* aPad, D_PAD& aDummyPad )
aDummyPad.SetCustomShapeInZoneOpt( aPad->GetCustomShapeInZoneOpt() );
// Note: drill size represents finish size, which means the actual holes size is the
// plating thickness larger.
int platingThickness = 0;
if( aPad->GetAttribute() == PAD_ATTRIB_STANDARD )
platingThickness = aPad->GetBoard()->GetDesignSettings().GetHolePlatingThickness();
aDummyPad.SetOffset( wxPoint( 0, 0 ) );
aDummyPad.SetSize( aPad->GetDrillSize() );
aDummyPad.SetSize( aPad->GetDrillSize() + wxSize( platingThickness, platingThickness ) );
aDummyPad.SetShape( aPad->GetDrillShape() == PAD_DRILL_SHAPE_OBLONG ? PAD_SHAPE_OVAL
: PAD_SHAPE_CIRCLE );
aDummyPad.SetOrientation( aPad->GetOrientation() );