ADDED holeWallPlatingThickness to AdvancedCfg.
Used for zone filling and DRC hole collision testing. Allows us to calculate the actual hole size from the finish hole size. Fixes https://gitlab.com/kicad/code/kicad/issues/5468
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@ -74,6 +74,13 @@ static const wxChar ExtraFillMargin[] = wxT( "ExtraFillMargin" );
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*/
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static const wxChar DRCEpsilon[] = wxT( "DRCEpsilon" );
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/**
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* Used to calculate the actual hole size from the finish hole size.
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* IPC-6012 says 15-18um; Cadence says at least 0.020 for a Class 2 board and at least 0.025
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* for Class 3.
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*/
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static const wxChar HoleWallThickness[] = wxT( "HoleWallPlatingThickness" );
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/**
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* Testing mode for new connectivity algorithm. Setting this to on will cause all modifications
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* to the netlist to be recalculated on the fly. This may be slower than the standard process
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@ -213,6 +220,10 @@ ADVANCED_CFG::ADVANCED_CFG()
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m_extraClearance = 0.0005;
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m_DRCEpsilon = 0.0005; // 500nm is small enough not to materially violate
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// any constraints.
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m_holeWallThickness = 0.020; // IPC-6012 says 15-18um; Cadence says at least
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// 0.020 for a Class 2 board and at least 0.025
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// for Class 3.
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loadFromConfigFile();
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}
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@ -259,6 +270,9 @@ void ADVANCED_CFG::loadSettings( wxConfigBase& aCfg )
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configParams.push_back( new PARAM_CFG_DOUBLE( true, AC_KEYS::DRCEpsilon,
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&m_DRCEpsilon, 0.0005, 0.0, 1.0 ) );
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configParams.push_back( new PARAM_CFG_DOUBLE( true, AC_KEYS::HoleWallThickness,
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&m_holeWallThickness, 0.020, 0.0, 1.0 ) );
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configParams.push_back( new PARAM_CFG_INT( true, AC_KEYS::CoroutineStackSize,
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&m_coroutineStackSize, AC_STACK::default_stack,
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AC_STACK::min_stack, AC_STACK::max_stack ) );
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@ -278,12 +292,12 @@ void ADVANCED_CFG::loadSettings( wxConfigBase& aCfg )
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configParams.push_back( new PARAM_CFG_BOOL( true, AC_KEYS::StrokeTriangulation,
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&m_DrawTriangulationOutlines, false ) );
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configParams.push_back(
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new PARAM_CFG_BOOL( true, AC_KEYS::PluginAltiumSch, &m_PluginAltiumSch, false ) );
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configParams.push_back( new PARAM_CFG_BOOL( true, AC_KEYS::PluginAltiumSch,
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&m_PluginAltiumSch, false ) );
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wxConfigLoadSetups( &aCfg, configParams );
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for( auto param : configParams )
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for( PARAM_CFG* param : configParams )
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delete param;
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dumpCfg( configParams );
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@ -94,6 +94,11 @@ public:
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*/
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double m_DRCEpsilon;
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/**
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* Hole wall plating thickness. Used to determine actual hole size from finish hole size.
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*/
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double m_holeWallThickness;
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/**
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* Do real-time connectivity
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*/
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@ -89,9 +89,6 @@
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#define MINIMUM_ERROR_SIZE_MM 0.001
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#define MAXIMUM_ERROR_SIZE_MM 0.1
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#define DRC_EPSILON 500; // An epsilon to account for rounding errors, etc.
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// 500nm is small enough not to materially violate
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// any constraints.
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/**
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* Struct VIA_DIMENSION
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@ -802,6 +799,12 @@ public:
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*/
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int GetDRCEpsilon() const;
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/**
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* Pad & via drills are finish size. Adding the hole plating thickness gives you the
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* acutal hole size.
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*/
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int GetHolePlatingThickness() const;
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/**
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* Function GetLineThickness
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* Returns the default graphic segment thickness from the layer class for the given layer.
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@ -966,6 +966,12 @@ int BOARD_DESIGN_SETTINGS::GetDRCEpsilon() const
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}
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int BOARD_DESIGN_SETTINGS::GetHolePlatingThickness() const
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{
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return Millimeter2iu( ADVANCED_CFG::GetCfg().m_holeWallThickness );
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}
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int BOARD_DESIGN_SETTINGS::GetLineThickness( PCB_LAYER_ID aLayer ) const
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{
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return m_LineThickness[ GetLayerClass( aLayer ) ];
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@ -530,7 +530,6 @@ public:
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*/
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BOARD_DESIGN_SETTINGS& GetDesignSettings() const
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{
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return *m_designSettings;
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}
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@ -319,6 +319,9 @@ void DRC::doTrackDrc( BOARD_COMMIT& aCommit, TRACK* aRefSeg, TRACKS::iterator aS
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&m_clearanceSource );
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}
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if( pad->GetAttribute() == PAD_ATTRIB_STANDARD )
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minClearance += bds.GetHolePlatingThickness();
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if( slot->Collide( &refSeg, minClearance + bds.GetDRCEpsilon(), &actual ) )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_CLEARANCE );
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@ -445,8 +445,15 @@ static void setupDummyPadForHole( const D_PAD* aPad, D_PAD& aDummyPad )
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aDummyPad.SetCustomShapeInZoneOpt( aPad->GetCustomShapeInZoneOpt() );
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// Note: drill size represents finish size, which means the actual holes size is the
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// plating thickness larger.
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int platingThickness = 0;
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if( aPad->GetAttribute() == PAD_ATTRIB_STANDARD )
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platingThickness = aPad->GetBoard()->GetDesignSettings().GetHolePlatingThickness();
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aDummyPad.SetOffset( wxPoint( 0, 0 ) );
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aDummyPad.SetSize( aPad->GetDrillSize() );
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aDummyPad.SetSize( aPad->GetDrillSize() + wxSize( platingThickness, platingThickness ) );
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aDummyPad.SetShape( aPad->GetDrillShape() == PAD_DRILL_SHAPE_OBLONG ? PAD_SHAPE_OVAL
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: PAD_SHAPE_CIRCLE );
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aDummyPad.SetOrientation( aPad->GetOrientation() );
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